JPS58220445A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain an IC which has high reliability by separating a flat ultrafine element being manufactured as designed without using thermal oxidation for a high temperature long period nor mechanical polishing technique and forming an element on an insular region. CONSTITUTION:A hole is opened at an SiO2 film 2 on a p type Si substrate, a reactive ion etching is performed to form grooves 4. An SiO2 film 5 is covered, and a p<+> type layer 6 which has 1/2 or smaller than the width of the groove is superposed on the overall surface. Then, a p<+> type layer 6' is allowed to selectively remain by reactive ion etching on the wall surface of the groove 4, an n<-> type polysilicon 7 is superposed on the overall surface to bury the grooves 4. A p<+> type layer 8 is formed by heat treating it at a low temperature and diffusing from the layer 6 to the layer 7. When the polysilicon 7 is selectively removed with KOH, the surface of the polysilicon unit 9 becomes substantially equal level to the surface of the film 2 on an insular region, thereby completing the isolating region 10. An FET is formed as normally on the insular region. According to the method, the redistribution of the diffused layer before the step of isolating an element can be prevented, characteristics are improved, the isolating layer can be formed by a substantially defined size, and mechanical polishing is not employed. Accordingly the characteristics of the element are not degraded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly to a method for manufacturing a semiconductor integrated circuit in which the process for forming element isolation regions is improved.

[Technical background of the invention and its problems]

Semiconductor integrated circuits are becoming increasingly large in scale due to increased integration capacity and diversification of logical functions. Along with this, there is an endless demand for miniaturization of elements, such as 2μm, 1μm, etc.
μm1 is about to enter the submicron region. The possibility of increasing the scale of integrated circuits through the development of such link graph technology will only be realized when element structures suitable for miniaturization are improved. First, there is a strong demand for innovation in isolation technology between elements, and active efforts have been made to develop isolation technology using dielectrics rather than conventional pn junction isolation technology. For example, ■ Selective oxidation isolation technology (LOCO8, 15oplan*r) that isolates silicon elements by selectively changing a part of the silicon substrate to a thick 5I02 film
) ,■ Technology to separate a part of the silicon substrate by making it redundant and further oxidizing it (lPO3: Inaul
atlanbyoxldlzsd Porous 5l
lIcon), the part that should be separated into 07 figures is anisotropic,
technology (VIP: V
-groo ma・l5olation polyories
tal b'aakflll, V-ATE”.

V@rticIILI Anlsotrople Et
ahlng), etc., and each is being applied to devices.

However, each of these separation techniques has advantages and disadvantages, and it is necessary to take advantage of their characteristics and apply them to devices. Among them, the selective oxidation isolation technology described in (2) is applied to both MOS LSI and bipolar LSI, and is considered the most effective technology for high integration. In order to form a relatively thick oxide film, various problems have arisen in connection with the growth process. For example, in MO8 devices, the width (w) of the channel region, which determines the characteristics, is due to side oxidation.
Changes due to turn deformation, causing variations in characteristics. Further, in the selective oxidation separation method in which a silicon substrate is etched and then oxidized, breaks in the At wiring occur at so-called bird's beaks, bird's holes, holes, and the like. Furthermore, since long-term heat treatment at high temperatures is required to form a thick oxide film, outward expansion from the buried layer occurs in bipolar devices, leading to a reduction in junction breakdown voltage and deterioration of the denoise characteristics. Problems that have a negative impact will occur, and it is necessary to take these into account in advance when designing. ■Separation method book by I-rathization,
The subsequent change in volume causes distortion in the UNINO, resulting in destruction of the UNINO, joint leakage, etc., and it has not yet been put to practical use. Furthermore, the separation technology described in (2) involves anisotropically processing and etching the silicon substrate, oxidizing the surface, depositing polycrystalline silicon on the entire surface, and flattening it by mechanically polishing the surface, which is a process problem. The problems are concentrated in the surface polishing technology, and there are problems with processing accuracy, high costs due to decreased yield, and negative effects on device characteristics due to mechanical polishing, so special devices for color removal have not been put into practical use. .

[Purpose of the invention]

The present invention aims to provide a method for manufacturing a semiconductor integrated circuit in which flat and fine isolation regions are formed without using mechanical polishing techniques. Reactive ion etching (RIE) on the substrate
) forming a groove having substantially vertical sides;
forming a thin insulating film on the inner surface of the trench by oxidation treatment or the like; depositing a first polycrystalline silicon film of a first conductivity type with a thickness of 1/2 or less of the width of the trench over the entire surface including the trench; R.I.
A process of etching and etching a polycrystalline silicon film using E to leave the polycrystalline silicon film only on the inner surface of the groove, and a step of applying a second polycrystalline silicon film of a second conductivity type to the entire surface of the semiconductor substrate so that the groove is fully covered. The first conductivity type impurity in the remaining polycrystalline silicon film is diffused into the second polycrystalline silicon film portion in the trench, converted to the first conductivity type, and the second conductivity type impurity is converted to the first conductivity type. The process of separating the polycrystalline silicon film into conductivity types within the groove and on the substrate, and the second conductivity! By selectively removing only the second polycrystalline silicon film of the mold, a fine element isolation region with a flat surface is formed from the trench and the first conductivity type polycrystalline silicon buried therein. The main point is to do so.

[Embodiments of the invention]

Next, an example in which the present invention is applied to the manufacture of an n-channel MO8IC will be described with reference to FIGS. 1(-) to 1(g).

(1) First, the p-type silicon substrate 1 is thermally oxidized to form an oxide film 2 on its surface, and then the oxide film 2 in the intended element isolation region is removed using photoetching technology to form the opening 3.
... was formed (as shown in Figure 1 (^)). Subsequently, the exposed portion of the substrate 1 is selectively etched away by RIE using a photoresist or (not shown) film 2 as a mask to form a groove 4 having a width of 1.5 μm and a desired depth, for example. , heat treatment is applied to the inner surface of the groove 4 so that the thickness is 3.
An oxide film 5 of 000X was grown (as shown in FIG. 1(b)).
.

(11) Next, a first polycrystalline silicon film 6 containing a high concentration p-type impurity (zolon) was deposited on the entire surface to a thickness of more than 1/2 of the width of the trench 40, for example, 3000× (see FIG. 1(C)). (Illustrated). Continuing with RII, the first polycrystalline silicon film 6
was removed by etching to about one thickness. At this time, since RIE etching progresses only in the direction perpendicular to the substrate 1, the first polycrystalline silicon film 6' remains only on the inner surface of the trench 4. Subsequently, a second polycrystalline silicon film 7 containing a low concentration n-type impurity (arsenic) was deposited on the entire surface to a thickness of, for example, 6000×, to sufficiently fill the trench 4 (as shown in FIG. 1(d)). Note that an undoped second polycrystalline silicon film may be used instead of the second polycrystalline silicon film containing a low concentration of n-type impurity.

(li+) Then, heat treatment was performed. At this time, as shown in FIG. 1(e), zolon diffuses from the remaining polycrystalline silicon film 6' containing high concentration p-type impurities on the inner surface of the trench 4 to the second polycrystalline silicon film 7 within the same trench 4. A p+ type polycrystalline silicon portion 8 was thus formed. In this case, it is necessary to perform heat treatment at a low temperature (800 to 900° C.) so that the second polycrystalline silicon film 7 deposited on the surface does not convert to p-type. In this heat treatment step, since the oxide film 5 is coated on the inner surface of the trench 4, diffusion of p-type impurities to the periphery of the trench 4 can be prevented.

(1) Next, etching was performed using KOH, which is selective etching of n-type polycrystalline silicon. At this time,
- The portion of the second polycrystalline silicon film 7 containing n-type impurities is selectively etched away, and since the polycrystalline silicon in the trench 4 is p-type, it is hardly etched, and the inside of the trench 4 is p-type polycrystalline silicon. The surface of the polycrystalline silicon body 90 is filled with the crystalline silicon body 9 and is at approximately the same level as the surface of the oxide film 2 on the island region.
was formed (as shown in FIG. 1(f)). .

(V) Next, the Q oxide film 2 on the surface of the substrate 1 is removed and thermal oxidation is performed again to form a y-t oxide film 11 on the island-shaped region of the substrate 1 separated by the element isolation region 10. At the same time, a thick oxide film 12 was grown on the exposed surface of the p-type polycrystalline silicon body 9 constituting the element isolation region 10. Continuing,
A polycrystalline silicon film is deposited on the entire surface according to a conventional method, and patterned using photoetching technology to selectively form f-t electrodes 13 on the island-shaped substrate 1 region.
Using the gate electrodes 13 and the element isolation region 10 as a mask, ion-implanted impurities, such as arsenic, are ion-implanted and activated to form n+ type regions 14 as source and drain regions, thereby manufacturing an n-channel MO8IC. (Figure 1)
(Illustrated).

Therefore, the method of the present invention has the following various effects: (1) Since it does not require high-temperature and long-term heat treatment unlike the selective oxidation method, redistribution of the impurity diffusion layer before the element isolation process can be prevented. ■ Since there is no need to selectively grow a thick oxide film as in the selective oxidation method, there is less pattern deformation and it is possible to form fine device isolation regions. Since the dimensions of the element isolation region can be approximately determined by the mask dimensions, the degree of integration can be improved.

■ Unlike conventional V-shape processing and chipping, device separation methods do not use mechanical polishing techniques, so flat device isolation regions can be formed at high yields and at low cost. It is possible to eliminate deterioration of device characteristics due to

■ It also has the same characteristics of dielectric isolation, such as reduced junction capacitance, increased degree of integration, and reduced wiring stray capacitance.

In addition, in the process of forming the groove portion 4 in the above embodiment, as shown in FIG.
was performed as a mask, the silicon nitride film 15 was left, and the first. After depositing the polycrystalline silicon film 6, RIE
Then, the polycrystalline silicon film 6 is etched to form a remaining polycrystalline silicon film 6', and the oxide film 5 exposed on the bottom surface of the trench 4 is selected using the silicon nitride film 16 and the remaining polycrystalline silicon film 6' as a mask. If the etching and etching are removed, the remaining polycrystalline silicon film 6 will be removed in the (li+> step of the embodiment).
'from? A p-type channel region 16 can be simultaneously formed on the bottom surface of the groove portion 4 during the diffusion.

Further, in the above embodiment, the element isolation region was formed by selectively etching the nm-thick second polycrystalline silicon film portion with KOH, but the method is not limited to this. For example i
・The conductivity types of the first polycrystalline silicon film and the second polycrystalline silicon film are reversed, and the first polycrystalline silicon film is doped with a high concentration of n-type impurity, and the second polycrystalline silicon film is doped with a low concentration of p-type impurity. The polycrystalline silicon of the surface layer shown in FIG. 1(e) is made p-type. Subsequently, as shown in FIG. 3, for example, a constant voltage is applied in an HF solution to flow a current, and as shown in FIG.
Only the upper p-type polycrystalline silicon film 18 is selectively made porous.

Thereafter, the porous silicon film may be oxidized at a low temperature in a wet oxygen atmosphere, and the oxide film may be removed to form an element isolation region with a flat surface.

Furthermore, the present invention provides an n-channel MO8I as in the above embodiment.
Not limited to manufacturing only p-channel MO8I C,C
The present invention can be similarly applied to MO8IC, I2L, or the bipolar IC shown in FIG. 4.

However, as shown in FIG.
A groove 23 reaching the substrate 21 is formed in the groove 23.
The trench 23 is filled with a p-type (or n-type) polycrystalline silicon body 25 via an oxide film 24 to form an element isolation region 26. Note that 27 in FIG.
8 is a p-type base region, 29 is an n++ emitter region, 80
3 is an n++ collector extraction region, and 31 is an interlayer insulating film in which a contact hole is opened.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to produce flat and fine elements according to the desired mask design without performing thermal oxidation treatment during high-temperature manufacturing time and without using mechanical polishing techniques such as the VIP method. By forming an isolation region and forming transistors, etc. in the island-shaped element formation area surrounded by this element formation area, highly reliable, high performance, and highly integrated semiconductor integrated circuits can be manufactured at a high yield. We can provide a possible method.

[Brief explanation of drawings]

1(g) to 1(g) are cross-sectional views showing the manufacturing process of an n-channel MO8IC according to an embodiment of the present invention. FIG. FIG. 4 is a cross-sectional view illustrating the formation of an element isolation step by making a silicon film porous, and FIG. 4 is a cross-sectional view showing a bipolar IC obtained by the method of the present invention. 1.21...Groove type silicon substrate, 4.23...Groove portion, 5, 24...Oxide film, 6...First polycrystalline silicon film, 6'...Remaining polycrystalline silicon film, 7... Second polycrystalline silicon film, 8... pm, polycrystalline silicon portion, 9
．． 25... Polycrystalline silicon body, 10. 26... Yonago isolation region, 13... r-to electrode, 14... n+ type region 16... p type channel strike region, 18.
...Porous p-type polycrystalline silicon film, 22...
・N-type silicon layer, 27...n+ type depression layer, 28.
...p type base region, 29...n+ type engineering ξ ivy region,
80...Meter type collector extraction area.

Claims (1)

[Claims] (IJ) A step of selectively forming a groove in a portion of a semiconductor substrate where an element isolation region is to be formed, a step of covering the inner surface of the groove with a thin insulating film, and a step of forming a groove of a first conductivity type on the inner surface of the groove. (1) selectively forming a polycrystalline silicon film, depositing a second polycrystalline silicon film of a second conductivity type over the entire surface of the semiconductor substrate so as to sufficiently fill the trench, and heat-treating the inner surface of the trench. After diffusing the first conductivity type impurity from the first polycrystalline silicon film into the second polycrystalline silicon film portion in the trench and converting it to the first conductivity type, the first conductivity type impurity on the semiconductor substrate is A semiconductor characterized by comprising the steps of: removing a portion of the second polycrystalline silicon film that does not contain the second polycrystalline silicon film; and forming an element including at least one pn junction on the surface of the island-shaped semiconductor substrate surrounded by the groove. A method for manufacturing an integrated circuit. (2) Using a p-type as the first conductivity type and a di-type as the second conductivity type, removing the second polycrystalline silicon film portion on the semiconductor substrate using an etching solution. A method for manufacturing a semiconductor integrated circuit according to claim 1, characterized in that: (3) using n type as the first conductivity type and p type as the second conductivity type, and using the second polycrystalline silicon on the semiconductor substrate; 2. The method of manufacturing a semiconductor integrated circuit according to claim 1, wherein the film portion is removed by making it porous and oxidizing.