JPS6079737A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6079737A
JPS6079737A JP18655383A JP18655383A JPS6079737A JP S6079737 A JPS6079737 A JP S6079737A JP 18655383 A JP18655383 A JP 18655383A JP 18655383 A JP18655383 A JP 18655383A JP S6079737 A JPS6079737 A JP S6079737A
Authority
JP
Japan
Prior art keywords
film
polycrystalline silicon
groove
silicon film
high concentration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18655383A
Other languages
Japanese (ja)
Inventor
Yasutaka Ikushima
生嶋 康孝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP18655383A priority Critical patent/JPS6079737A/en
Publication of JPS6079737A publication Critical patent/JPS6079737A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/763Polycrystalline semiconductor regions

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To make surface smooth by a method wherein polycrystalline silicon films in the groove for separating elements are formed evenly and then the oxidation degree on the surface of these silicon films is adjusted. CONSTITUTION:A buried layer 22, a single crystal film 23, a silicon oxide film 24, a silicon nitride film 25 and a groove 27 are formed on a substrate 21. Then a silicon oxide film 29, a silicon nitride film 30 and polycrystalline silicon film 31 are formed on the side wall of the groove 27. Firstly a polycrystalline film 31' only is left on the side wall of the groove 27. Secondly the film 31' is formed into a P type polycrystalline silicon film 33 with high concentration. Thirdly a polycrystalline silicon film 32 is deposited to form it into a P type polycrystalline silicon film 34 with high concentration. Fourthly the film 32 is removed to make it lower than the surface of the groove 27 by means of etching the film 34. Fifthly the film 34 is oxidized to form a silicon oxide film 35. Finally another silicon oxide film 37 may be formed on the surface of said film 23 to form electrode wirings 38-40.

Description

【発明の詳細な説明】 〔発明の属する技術分野〕 本発明は半導体装置の製造方法に関し、特に素子間に深
い溝が形成され、この溝を絶縁物等で埋設することによ
夕、素子間が分離された半導体装置の製造方法に関する
[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to a method of manufacturing a semiconductor device, and in particular, a method for manufacturing a semiconductor device, in which deep grooves are formed between elements, and by filling the grooves with an insulating material, etc. The present invention relates to a method for manufacturing a semiconductor device in which the semiconductor devices are separated.

〔従来技術〕[Prior art]

最近、素子の微細化が進む中でLSIの高密度化、高集
積化を一層進展させるために1選択酸化による絶縁層分
離で発生するバーズビークを除去することが必要になp
″、その改善方法音種々提案されている。その中の代表
的な方法として溝埋迅分離法がある。
Recently, with the progress of miniaturization of devices, it has become necessary to remove bird's beaks that occur when insulating layers are separated by selective oxidation in order to further increase the density and integration of LSIs.
'', various methods have been proposed to improve this. One of the most representative methods is the groove filling quick separation method.

第1図18)〜(d)は従来の溝埋色分離法による半導
体装置の製造方法を説明するための工程順に示した断面
図である。
FIGS. 18) to 18(d) are cross-sectional views shown in the order of steps for explaining a method of manufacturing a semiconductor device using the conventional trench filling color separation method.

先ず、第1図(a)に示すように、p域中導体基板lと
高濃度n型埋込層2とエピタキシャル法で形成した単結
晶膜3から構成されるi休に周知の方法で溝4會形成し
、引続いて溝4の表面に酸化ケイ素膜5及び窒化ケイ素
膜6全形成し、次いで。
First, as shown in FIG. 1(a), a groove is formed using a well-known method in a substrate consisting of a p-region medium conductor substrate l, a heavily doped n-type buried layer 2, and a single crystal film 3 formed by an epitaxial method. 4, and then a silicon oxide film 5 and a silicon nitride film 6 were completely formed on the surface of the groove 4, and then.

この窒化ケイ素膜6の表面に多結晶ケイ素膜7會堆積し
、m4*埋設する。
Seven polycrystalline silicon films are deposited on the surface of this silicon nitride film 6 and buried in m4*.

次に、第1図(b)に示すように、溝4の上部領域の多
結晶ケイ素膜の表面tホトレジスト膜8で覆い、不要部
の多結晶ケイ素膜を除去する。
Next, as shown in FIG. 1(b), the surface of the polycrystalline silicon film in the upper region of the groove 4 is covered with a photoresist film 8, and unnecessary portions of the polycrystalline silicon film are removed.

しかしながら、この除去工程で、溝以外の多結晶ケイ素
膜のみtエツチング除去することは困難で、溝領域の多
結晶ケイ素がオーバーエツチングされて、第1図(e)
に示すように溝領域に大きな段差9が生じたり、またホ
トレジスト8の位置が正確でないと第1図(ψに示すよ
うに多結晶ケイ素膜に大きな段差lOが生じる。
However, in this removal process, it is difficult to remove only the polycrystalline silicon film other than the groove by etching, and the polycrystalline silicon in the groove area is over-etched, as shown in FIG. 1(e).
If the position of the photoresist 8 is not accurate, a large step 9 will occur in the groove region as shown in FIG.

このような段差が形成されると、金属配線の断線が生じ
やすく、まfC高密度化、高集積化の進展しfc半導体
装置を製造することが出来ないという欠点があった。
When such a step is formed, the metal wiring is likely to be disconnected, and there is a drawback that it is impossible to manufacture an FC semiconductor device despite the progress of high density and high integration of FC semiconductors.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、以上の欠点を除去し、素子間分離用の
溝表面がほぼ平坦化され、高密度化、高集積化に好適な
半導体装置の製造方法を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks, to provide a method for manufacturing a semiconductor device in which the surface of a groove for isolation between elements is substantially flattened, and is suitable for high density and high integration.

〔発明の構成〕[Structure of the invention]

一導電型の半導体基板と逆導電型単結晶膜とから構成さ
れる半導体基体に、前記逆導電型単結晶膜の表面から、
前記−導電型基板まで到達する溝ケ形成する工程と、該
溝の側面および底面に酸化ケイ素膜を形成する工程と、
該酸化ケイ素膜表面に不純物未添加の第1の多結晶ケイ
素膜を堆積する工程と、該第1の多結晶ケイ素膜を異方
性エツチングにより前記溝の側面以外の多結晶ケイ素膜
金除去する工程と、前記溝側面に残存する第1の多結晶
ケイ素膜を高濃度−導電型にする工程と。
From the surface of the opposite conductivity type single crystal film to a semiconductor substrate composed of a semiconductor substrate of one conductivity type and a reverse conductivity type single crystal film,
a step of forming a groove that reaches the conductivity type substrate; a step of forming a silicon oxide film on the side and bottom surfaces of the groove;
Depositing a first polycrystalline silicon film to which no impurities are added on the surface of the silicon oxide film, and removing gold from the polycrystalline silicon film other than the side surfaces of the groove by anisotropic etching the first polycrystalline silicon film. and a step of making the first polycrystalline silicon film remaining on the side surface of the groove into a high concentration-conductivity type.

該高濃度−導電型多結晶ケイ素膜表面と前記耐酸化性膜
表面圧不純物未添加の第2の多結晶ケイ素膜全堆積し溝
を埋設する工程と、該溝内部の第2の多結晶ケイ素膜を
高濃度−導電型にする工程と、前記不純物未添加の第2
の多結晶ケイ素膜のみt選択的に除去する工程と、前記
高濃度−導電を多結晶ケイ素膜の表面領域を除去し該高
濃度−導電型多結晶ケイ素膜表面を該溝内部に残存させ
る工程と、該高濃度−導′FILFM多結晶ケイ素膜の
表面領域全酸化ケイ素膜に変換し、該酸化ケイ素膜表面
と溝以外の領域の表面tはぼ平坦にする工程とt含んで
構成される。
A step of fully depositing a second polycrystalline silicon film to which no impurities are added on the surface of the high-concentration conductive polycrystalline silicon film and the surface pressure of the oxidation-resistant film, and burying a trench, and a second polycrystalline silicon film inside the trench. A step of making the film a high concentration-conductivity type, and a step of making the film a high concentration conductivity type, and
a step of selectively removing only the polycrystalline silicon film, and a step of removing the surface region of the highly-conductive polycrystalline silicon film and leaving the surface of the highly-conductive polycrystalline silicon film inside the groove. and converting the surface area of the high-concentration conductive FILFM polycrystalline silicon film into an all-silicon oxide film, and substantially flattening the surface of the silicon oxide film and areas other than the grooves. .

〔実施例の説明〕[Explanation of Examples]

以下、本発明の実施例について1図面?参照して説明す
る。
The following is a drawing regarding an embodiment of the present invention. Refer to and explain.

第2図18)〜(h、は本発明の一実施例を説明するた
めの工程順に示した断面図である。
FIGS. 18) to 18h are cross-sectional views shown in order of steps for explaining an embodiment of the present invention.

まず、第2図18)に示すように、pをケイ素半導体基
板21、高濃度na埋迅層22及びエピタキシャル法で
形成したn型単結晶膜23i有する半導体基体衆面に酸
化ケイ素膜24及び窒化ケイ素膜25’(形成し、引続
いて、ホトレジスト膜26を耐エツチング材として用い
て、p観ケイ素半導体基板21まで到達する溝27t−
形成する。
First, as shown in FIG. 2 (18), a silicon oxide film 24 and a nitride silicon semiconductor substrate are covered with a silicon semiconductor substrate 21, a high-concentration Na buried layer 22, and an n-type single crystal film 23i formed by an epitaxial method. A silicon film 25' (is formed, and then a trench 27t- reaching the p-view silicon semiconductor substrate 21 is formed using the photoresist film 26 as an etching resistant material.
Form.

上記溝27の形成には、例えば四塩化炭素と酸素の混合
プラズマ上用いて行う。次い゛でf127の底部に反転
チャンネル形成防止用のp型領賊28tイオン注入法に
より形成するつ 次に、第2図(b)に示すように、ホトレジスト膜26
會除去後、溝27の側壁に酸化ケイ素膜29及び窒化ク
イ紫膜30t−形成する。次いで、窒化ケイ素膜30の
表面に厚さ0.1乃至1.0μmの不純物未添加の第1
の多結晶ケイ素膜31′fr:、溝27が未だ完全には
埋設されないように堆積する。
The grooves 27 are formed using, for example, a mixed plasma of carbon tetrachloride and oxygen. Next, as shown in FIG. 2(b), a p-type region 28t for preventing the formation of an inversion channel is formed at the bottom of f127 by ion implantation.
After removal, a silicon oxide film 29 and a nitride film 30t are formed on the side walls of the groove 27. Next, an impurity-free first film having a thickness of 0.1 to 1.0 μm is deposited on the surface of the silicon nitride film 30.
Polycrystalline silicon film 31'fr: is deposited so that the groove 27 is not completely buried.

次に、第2図(C)に示すように、リアクティブイオン
エツチング(ルIE)法を用いて、溝部以外の領域、す
なわち平坦部領域の多結晶ケイ素膜31及び溝27底部
の多結晶ケイ素膜全除去し、溝側壁にのみ不純物未添加
の多結晶ケイ素膜31’を残す。次いで、ホウ素拡散あ
るいは、ホウ素イオン注入を施し、上記溝側壁に残存さ
せた多結晶ケイ素膜31”t−高濃度のp!多結晶ケイ
素膜33にする。 ゛ 次に、第2図(d)に示すように、不純物未添加の第2
の多結晶ケイ素膜32t−厚さ0.5〜3μm堆積し、
上記溝27に完全に埋設する。引続き、900〜120
0℃の熱処理上行い、高濃度pa多結晶ケイ素33から
第2の多結晶ケイ素膜32ヘホウ素全拡散させ、溝領域
の多結晶ケイ素膜32を高濃度p型多結晶ケイ素膜34
にする。
Next, as shown in FIG. 2C, using a reactive ion etching (IE) method, the polycrystalline silicon film 31 in the area other than the groove, that is, the flat area, and the polycrystalline silicon film 31 at the bottom of the groove 27 are etched. The entire film is removed, leaving only the undoped polycrystalline silicon film 31' on the trench sidewalls. Next, boron diffusion or boron ion implantation is performed to form the polycrystalline silicon film 31'' left on the side wall of the trench to a high concentration p! polycrystalline silicon film 33.Next, FIG. 2(d) As shown in
A polycrystalline silicon film 32t of 0.5 to 3 μm thick is deposited,
Completely bury it in the groove 27. Continued from 900 to 120
A heat treatment is performed at 0° C. to completely diffuse boron from the high concentration PA polycrystalline silicon 33 into the second polycrystalline silicon film 32, and convert the polycrystalline silicon film 32 in the groove region into a high concentration p-type polycrystalline silicon film 34.
Make it.

次に、第2図(e)に示すように、水酸化カリウムある
いはヒドラジンとイソプロパツールの混合液音用いて、
多結晶ケイ素膜32のみ全エツチング除去する。上記混
合液は既知の如く、高濃度p型領域でのエツチング速度
が極めて小さくなるので、上記高濃度多結晶ケイ素膜3
4は殆んどエツチングされないで残存する。
Next, as shown in Figure 2(e), using a mixture of potassium hydroxide or hydrazine and isopropanol,
Only the polycrystalline silicon film 32 is completely etched away. As is known, the above-mentioned mixed solution has an extremely low etching rate in the high-concentration p-type region, so the high-concentration polycrystalline silicon film 3
4 remains almost unetched.

′次に、第2図(f)に示すように、827の上部に突
出した高濃度p I!!!多結晶ケイ素膜34?l−弗
酸と硝酸と酢酸等の混合液を用いて、エツチングし、高
濃度PI多結晶ケイ素膜34の表面が溝表面より0.0
5乃至0.5μm低くなるようにする。
'Next, as shown in FIG. 2(f), the high concentration p I! ! ! Polycrystalline silicon film 34? Etching is performed using a mixed solution of l-hydrofluoric acid, nitric acid, acetic acid, etc., so that the surface of the high concentration PI polycrystalline silicon film 34 is 0.0% lower than the groove surface.
The height should be 5 to 0.5 μm lower.

次に、第2図(g)に示すように、窒化ケイ素膜30t
−耐酸化性マスクとして、高濃度p型多結晶ケイ素膜3
4t−選択酸化して、酸化ケイ素膜35を形成し、この
酸化ケイ素膜350表面を窒化ケイ素膜30の表面とほ
ぼ平坦にする。
Next, as shown in FIG. 2(g), a silicon nitride film 30t
-High concentration p-type polycrystalline silicon film 3 as an oxidation-resistant mask
4t-selective oxidation is performed to form a silicon oxide film 35, and the surface of this silicon oxide film 350 is made substantially flat with the surface of the silicon nitride film 30.

最後に、第2図(h)に示すように、エピタキシャル法
で形成しZjn型単結晶膜230表面に、再度、酸化ケ
イ素膜37全形成し、周知の方法により、ベース、エミ
ッタ等の領域全形成し、電極配線3B、39.40等を
形成すると、表面かはは平坦で、かつ素子間t−eによ
シ分離された半導体装置が得られる。
Finally, as shown in FIG. 2(h), the entire silicon oxide film 37 is again formed on the surface of the ZJn type single crystal film 230 formed by the epitaxial method, and the base, emitter, etc. regions are completely covered by a well-known method. By forming the electrode wirings 3B, 39, 40, etc., a semiconductor device having a flat surface and separated by the inter-element t-e can be obtained.

以上説明したとおり1本実施例では自己整合的に溝部の
多結晶ケイ素膜全#1ぼ平坦で、かつ溝表面よシわずか
に低くなるよう形成しその後多結晶ケイ素膜の表面を選
択酸化し、酸化程度を加減することにより窒化ケイ素膜
の表面とほぼ平坦にすることは容易である。このように
得られた平滑表面では後で形成する金属配線の段差部で
の切断問題は生ずることはなり、シかも表面が平滑のた
め高密度化、高集積化にとって有効である。
As explained above, in this embodiment, the polycrystalline silicon film #1 in the groove is formed in a self-aligned manner so that it is flat and slightly lower than the groove surface, and then the surface of the polycrystalline silicon film is selectively oxidized. By adjusting the degree of oxidation, it is easy to make the surface almost flat with the silicon nitride film. With the smooth surface thus obtained, there will be no problem of cutting the metal wiring formed later at the stepped portion, and since the surface is smooth, it is effective for high density and high integration.

〔発明の効果〕〔Effect of the invention〕

以上説明したとお91本発明によれは、溝領域がほぼ平
坦であるので、溝上部に延在する金属配線には断線の生
ずることなく、信頼性の高い半導体装置を得ることがで
きる。
As described above, according to the present invention, since the groove region is substantially flat, there is no disconnection in the metal wiring extending above the groove, and a highly reliable semiconductor device can be obtained.

また、その結果として高密度化、高集積のためにも効果
が大である。
Moreover, as a result, it is highly effective for higher density and higher integration.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(d)は従来の溝埋込分離法による半導
体装置の製造方法を説明するための工程順に示し比断面
図、第2図(a)〜(h)は本発明の一実施例を説明す
るための工程順に示した断面図である。 l・・・・・・p型半導体基板、2・・・・・・n型埋
込層、3・・・・・・単結晶膜、4・・・・・・溝%5
・・・・・・酸化ケイ素膜、6・・・・・・窒化ケイ素
膜、7・・・・・・多結晶ケイ素膜、8・・・・・・ホ
トレジスト膜、9.10・・・・・・段差、21・・・
・・・p型半導体基板、22・・・・・・n型埋込層、
23・・・・・・n型エピタキシャル層、24・・・・
・・酸化ケイ素膜、25・・・・・・窒化ケイ素膜、2
6・・・・・・ホトレジスト膜。 27・・・・・・溝、29・・・・・・酸化ケイ素膜、
30・・・・・・窒化ケイ素膜、31.32・・・・・
・多結晶ケイ素膜。 33.34・・・・・・pH!多結晶ケイ素膜、35・
・・・・・酸化ケイ素膜、37・・・・・・酸化ケイ素
膜、38,39゜40.41・・・・・・電極配#i!
。 ・−1−、 代理人 弁理士 内 原 晋1 ゛) 楽1 回 穿2回
1(a) to 1(d) are comparative cross-sectional views showing the process order for explaining a method of manufacturing a semiconductor device using the conventional trench-buried isolation method, and FIG. FIG. 3 is a cross-sectional view showing the order of steps for explaining one embodiment. l...p-type semiconductor substrate, 2...n-type buried layer, 3...single crystal film, 4...groove%5
...Silicon oxide film, 6...Silicon nitride film, 7...Polycrystalline silicon film, 8...Photoresist film, 9.10...・Step, 21...
. . . p-type semiconductor substrate, 22 . . . n-type buried layer,
23... N-type epitaxial layer, 24...
...Silicon oxide film, 25...Silicon nitride film, 2
6...Photoresist film. 27...Groove, 29...Silicon oxide film,
30...Silicon nitride film, 31.32...
・Polycrystalline silicon film. 33.34...pH! Polycrystalline silicon film, 35.
...Silicon oxide film, 37...Silicon oxide film, 38,39°40.41...Electrode arrangement #i!
.・−1−、Representative Patent Attorney Susumu Uchihara 1 ゛) Raku 1 time 2 times

Claims (1)

【特許請求の範囲】[Claims] 一層1を型半導体基板と透導を型単結晶膜とから構成さ
れる半導体基体に、前記逆導電型単結晶膜の表面から前
記−導電型半導体基板まで到達するSt−形成する工程
と、該溝の側面および底面に酸化ケイ素膜を形成する工
程と、該酸化ケイ素膜表面に耐酸化性膜を形成する工程
と、該耐酸化性膜表面に不純物未添加の第1の多結晶ケ
イ素膜を堆積する工程と、該第1の多結晶ケイ素膜を異
方性エツチングにより、前記溝の側面以外の多結晶ケイ
素膜を除去する工程と、該溝側面に残存する第1の多結
晶ケイ素膜を高濃度−導′NLfiiにする工程と、核
高濃度−導電型多結晶ケイ素膜表面と、前記耐酸化性膜
表面に不純物未添加の第2の多結晶ケイ素膜を堆積し清
音埋設する工程と、該溝内部の第2の多結晶ケイ素膜を
高濃度−導電型にする工程と、前記不純物未添加の第2
0多結晶ケイ素膜のみ?選択的に除去する工程と、前記
高濃度−導電型多結晶ケイ素膜の表面領域に除去し、該
高濃度−導電型多結晶ケイ素膜表面を該溝内部に残存さ
せる工程と、該高濃度−導電型多結晶ケイ素膜の表面領
域全酸化ケイ素膜に変換し、#酸化ケイ素膜表面と溝以
外の領域の表面上はぼ平坦にする工程と金含むことを特
徴とする半導体装置の製造方法。
A step of forming a layer 1 on a semiconductor substrate composed of a conductive type semiconductor substrate and a transparent conductive type single crystal film from the surface of the opposite conductive type single crystal film to the - conductive type semiconductor substrate; a step of forming a silicon oxide film on the side and bottom surfaces of the groove, a step of forming an oxidation-resistant film on the surface of the silicon oxide film, and a step of forming a first polycrystalline silicon film to which no impurities are added on the surface of the oxidation-resistant film. a step of depositing the first polycrystalline silicon film, a step of removing the polycrystalline silicon film other than the side surfaces of the groove by anisotropic etching the first polycrystalline silicon film, and a step of removing the first polycrystalline silicon film remaining on the side surfaces of the groove. a step of forming a high concentration conductive type polycrystalline silicon film; a step of depositing and burying a second polycrystalline silicon film to which no impurities are added on the surface of the core high concentration conductive type polycrystalline silicon film and the surface of the oxidation-resistant film; , a step of making the second polycrystalline silicon film inside the groove a high concentration-conductivity type;
0 Polycrystalline silicon film only? a step of selectively removing the polycrystalline silicon film; a step of removing the surface region of the high concentration conductivity type polycrystalline silicon film and leaving the surface of the high concentration conductivity type polycrystalline silicon film inside the groove; 1. A method for manufacturing a semiconductor device, comprising: converting the entire surface area of a conductive polycrystalline silicon film into a silicon oxide film, and substantially flattening the surface of the silicon oxide film and regions other than the grooves; and containing gold.
JP18655383A 1983-10-05 1983-10-05 Manufacture of semiconductor device Pending JPS6079737A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18655383A JPS6079737A (en) 1983-10-05 1983-10-05 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18655383A JPS6079737A (en) 1983-10-05 1983-10-05 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6079737A true JPS6079737A (en) 1985-05-07

Family

ID=16190527

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18655383A Pending JPS6079737A (en) 1983-10-05 1983-10-05 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6079737A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2614731A1 (en) * 1987-04-30 1988-11-04 Samsung Semiconductor Tele Method of manufacturing a trench-shaped capacitor for an integrated circuit
JPH01304723A (en) * 1988-06-01 1989-12-08 Matsushita Electric Ind Co Ltd Preparation of semiconductor device
JP2018503976A (en) * 2014-11-26 2018-02-08 日本テキサス・インスツルメンツ株式会社 Poly sandwich for deep trench filling

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58220445A (en) * 1982-06-16 1983-12-22 Toshiba Corp Manufacture of semiconductor integrated circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58220445A (en) * 1982-06-16 1983-12-22 Toshiba Corp Manufacture of semiconductor integrated circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2614731A1 (en) * 1987-04-30 1988-11-04 Samsung Semiconductor Tele Method of manufacturing a trench-shaped capacitor for an integrated circuit
JPH01304723A (en) * 1988-06-01 1989-12-08 Matsushita Electric Ind Co Ltd Preparation of semiconductor device
JP2018503976A (en) * 2014-11-26 2018-02-08 日本テキサス・インスツルメンツ株式会社 Poly sandwich for deep trench filling
JP2021061432A (en) * 2014-11-26 2021-04-15 日本テキサス・インスツルメンツ合同会社 Polysandwich for deep trench filling

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