JPS5818784B2 - Hand-crafted construction work - Google Patents

Description

[Detailed description of the invention] The present invention is a shallow PN junction (shallow junction).
The present invention relates to an electrode wiring structure of a type of semiconductor element.

Conventionally, when wiring electrodes in this type of shallow junction type semiconductor device, impurities are added to the silicon dioxide film to prevent lateral etching in the contact hole, resulting in a significant difference in etch rate. Se, Katsu,
When attaching an electrode, a method is used in which polycrystalline silicon is interposed between the joint and the electrode, thereby increasing the distance between the joint and the electrode.

In the latter of these steps, the surface of the semiconductor substrate, excluding the surface of the high impurity concentration region formed by shallow diffusion, is covered with an insulator such as a silicon oxide layer, and the surface of the high impurity concentration region and the silicon oxide layer are covered. Polycrystalline silicon containing a high concentration impurity of the same conductivity type as the high concentration impurity is deposited on the surface.

Next, the polycrystalline silicon layer with high impurity concentration on top of the insulator is removed, followed by depositing electrode metal on the surface of the polycrystalline silicon with high impurity concentration and the surface of the insulator, and finally the electrode metal is etched into a desired shape to form a semiconductor element.

However, in the conventional method for wiring electrode metal to a shallow junction type semiconductor element, the polycrystalline silicon layer with high impurity concentration remains only on the upper surface of the high concentration impurity region, so that the polycrystalline silicon layer and the insulator are There is a large step between the two, and the wiring metal is likely to break at this step.

Therefore, an object of the present invention is to accurately provide a highly reliable semiconductor device that has small steps and is less prone to disconnection of metal wiring.

According to this invention, the surface of a semiconductor layer having high resistivity, such as a polycrystalline silicon layer, is selectively oxidized to change it into a silicon oxide layer, and the exposed high resistivity polycrystalline silicon layer is used as a mask. By infiltrating high-concentration impurities into the crystalline silicon region and forming a high-resistivity polycrystalline silicon region into a highly impurity-concentrated polycrystalline silicon layer, the initially deposited high-resistivity polycrystalline silicon layer is not removed at all. Therefore, metal wiring to a shallow junction type semiconductor element with a small step difference can be easily made.

In the following embodiments, the semiconductor layer on the insulator and single crystal semiconductor substrate will be described as a polycrystalline silicon layer, but it goes without saying that the semiconductor layer on the single crystal semiconductor substrate may be a single crystal silicon layer.

Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIGS. 1A to 1E, the manufacturing process for obtaining the first embodiment of the present invention is as shown in FIG. A silicon film 2 is grown by thermal oxidation, and openings 3 are selectively provided therein.

Next, as shown in FIG. 1B, a high resistivity polycrystalline silicon layer 4 is deposited on the upper surface of the silicon dioxide film 2 and the upper surface of the opening 3 using thermal decomposition of silane (SiH4).

The resistivity of the polycrystalline silicon layer is 104 to 10105Q
- and has a thickness of 0.5 to 1.0 microns.

Next, as shown in FIG. 1C, the upper surface of polycrystalline silicon layer 4 is transformed into silicon oxide layer 5 by oxidation.

Next, as shown in the first diagram, the upper surface of the silicon oxide layer 5 is covered with a photoresist 6, the photoresist and the silicon oxide layer on the upper part of the polycrystalline silicon layer deposited on the upper part of the opening 3 are removed, and the upper surface of the silicon oxide layer 5 is removed. 8 will be provided.

Next, using the silicon oxide layer 5 and the photoresist 6 as a mask, ions 7 of high concentration of phosphorus or arsenic, which are N-type impurities, are implanted to transform the polycrystalline silicon layer directly under the opening 8 into polycrystalline silicon with a high concentration of N-type impurities. Change to area 9.

In this ion implantation, for example, 31P+ ions are
] 016 am-2, implanted at 150 KeV.

Next, the N-type high concentration impurity is diffused into the P-type nested crystal region 1 at 1000° C. for 10 to 20 minutes to form an N-type high concentration impurity region 10.

The junction depth of this N-type high concentration impurity region 10 is 0.1 to 0.3 μ.

Finally, as shown in FIG. 1E, the photoresist 6 is removed, and a metal such as aluminum is deposited on the top surface of the silicon oxide layer 5 and the top surface of the highly impurity concentration polycrystalline silicon region 9, and then etched into a desired shape. As a result, a metal electrode wiring 11 for the high concentration impurity region 10 with a shallow junction depth is obtained.

Next, referring to FIG. 2, the manufacturing process for obtaining the second embodiment of the present invention is as shown in FIG.
2 is grown by thermal oxidation, and an opening 23 is selectively formed in this, and through this opening, an impurity concentration of 1020 particles containing phosphorus or arsenic, which is an N-type impurity, is about cIrL-3 and a diffusion depth of 0. .1 to 0.3μ high concentration N type impurity region 24
form.

Next, in the same order and in the same manner as detailed in FIGS. 1B, 1C, 1D and 1E of the first embodiment, the shallow junction shown in FIG. 1E is constructed. A metal wiring to a semiconductor element having the same structure can also be obtained in the second embodiment.

FIG. 3 shows a conventional method for forming metal electrodes and wiring in a semiconductor element having a shallow junction.

In this structure, a polycrystalline silicon layer 32 and a silicon dioxide layer 3
There is a large gap between 1.

Therefore, when the electrode metal 33 is formed and wired, the electrode metal portions 34 and 35 near the polycrystalline silicon layer 32 and the silicon dioxide layer 31 are likely to be disconnected.

According to the metal wiring method of the embodiment of the present invention, the silicon oxide layer 5
There is a step at the boundary between the polycrystalline silicon layer 9 and the polycrystalline silicon layer 9.

Therefore, the electrode metal 11 does not break.

Therefore, by using this electrode metal formation and wiring method, a shallow junction type semiconductor element can be obtained with high reliability.

In addition, in the example, the highly doped N-type polycrystalline silicon layer 9 was formed by the ion implantation method, and the highly doped N-type region 10 was formed by the diffusion method, but the diffusion coefficient of impurities in the polycrystalline silicon Since this is large, regions 9 and 10 can be formed only by a diffusion method by diffusing phosphorus or arsenic, which are N-type impurities, into the polycrystalline silicon layer and P-type nested crystal layer 1 at 900° C. to 1000° C.

Furthermore, although the embodiment has been described using a P-type silicon single crystal layer, it goes without saying that the conductivity type can be changed as necessary.

[Brief explanation of drawings]

FIG. 1 A-E is a sectional view showing the first embodiment of the present invention according to the manufacturing process, FIG. 2 is a sectional view showing a part of the manufacturing process of the second embodiment, and FIG. 3 is a shallow 1 is a cross-sectional view showing a conventional method for forming and wiring metal electrodes on a semiconductor element having a junction. In the figure, 1: P-type silicon single crystal layer, 2: silicon dioxide layer, 4: high resistivity polycrystalline silicon layer, 5: silicon oxide layer, 9: polycrystalline silicon region containing high concentration impurity, 10 : High concentration impurity region, 11: Metal electrode and wiring, 21: P-type silicon single crystal layer, 22°31: Silicon dioxide layer, 24: High concentration impurity region, 32: Polycrystalline silicon region containing high concentration impurity, 33: Metal electrode and wiring.

Claims (1)

[Claims] 1 A first insulating layer provided on the main surface of a semiconductor substrate of one conductivity type, an opening provided in the first insulating layer reaching the main surface, and a first insulating layer provided on the main surface within the opening. a first semiconductor layer containing impurities of opposite conductivity type; a region of opposite conductivity type provided on the semiconductor substrate under the first semiconductor layer; the first semiconductor layer having a resistivity higher than that of the first semiconductor layer; a second semiconductor layer adjacent to the first semiconductor layer around the opening; a second insulating layer provided on the second semiconductor layer; What is claimed is: 1. A semiconductor device comprising: an electrode connected on one semiconductor layer and on the opening, and extending on the second insulating layer.