JP2659190B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device.

[Conventional technology]

2. Description of the Related Art In recent years, as semiconductor devices have become more highly integrated, the insulated gate field-effect transistor that constitutes the semiconductor device has an increased internal electric field strength due to miniaturization. It is a sexual problem.

One way to address such a problem is to alleviate the electric field strength near the drain region. For example, an LDD (Lightly Doped Drain) structure has been proposed.

FIG. 2 is a sectional view of a semiconductor chip for explaining an example of a conventional semiconductor device.

As shown in FIG. 2, a field insulating film 2 provided on a main surface of a P-type silicon substrate 1 to partition an element formation region.
A gate insulating film 3 selectively provided on the surface of the element formation region; a gate electrode 6 selectively provided on the gate insulating film 3; and a mask using the gate electrode 6 and the field insulating film 2 as masks. An N ⁻ -type diffusion region 7 provided in the element formation region by ion implantation of a low concentration impurity, a silicon oxide film 8 provided on a side wall of the gate electrode 6, An N ⁺ -type diffusion region provided by introducing a high-concentration impurity into the element formation region using the film 2 as a mask and being connected to the N ⁻ -type diffusion region 7.
10, a silicon oxide film (hereinafter referred to as PSG film) 11 containing phosphorus having a contact window on the surface of the deposited and N ⁺ -type diffusion region 10 including the gate electrode 6, the contact window N ⁺ A semiconductor device is configured to include the electrode diffusion region 12 in contact with the mold diffusion region 10 and extending on the PSG film 11.

[Problems to be solved by the invention]

In the above-described conventional semiconductor device, since the low concentration diffusion region exists only in the shallow region on the surface of the element forming region, there is no electric field relaxation effect at the end of the high concentration diffusion region in a region deeper than the low concentration diffusion region. There is a problem that characteristic deterioration due to the hot carrier effect cannot be suppressed.

[Means for solving the problem]

According to the method of manufacturing a semiconductor device of the present invention, a field insulating film for element isolation is selectively provided on a main surface of a semiconductor substrate of one conductivity type to divide an element forming region and a gate insulating film is formed on a surface of the element forming region. Forming a gate electrode by depositing and selectively etching a polycrystalline silicon layer on the surface including the gate insulating film; and inverting the first concentration using the gate electrode and the field insulating film as a mask. Forming a first low-concentration diffusion region of the opposite conductivity type on the surface of the element formation region by ion-implanting a conductivity type impurity; and depositing a silicon oxide film on the surface including the gate electrode and etching by an anisotropic etching method. Backing to form a sidewall spacer leaving the silicon oxide film only on the side surface of the gate electrode; and forming the gate electrode, the sidewall spacer and the field isolation. Using a film as a mask, an impurity of a reverse conductivity type having a higher concentration than the first concentration is ion-implanted and connected to the first low-concentration diffusion region on the surface of the element formation region. Forming a second low-concentration diffusion region of a deep reverse conductivity type; Forming a high concentration diffusion region by ion-implanting a conductive impurity.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

1 (a) to 1 (g) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention.

First, as shown in FIG. 1A, a field insulating film 2 for element isolation is selectively provided on a main surface of a P-type silicon substrate 1 to divide an element formation region. The gate insulating film 3 is formed by a thermal oxidation method. Next, a polycrystalline silicon layer 4 is deposited on the surface including the gate insulating film 3, and a photoresist film 5 having a pattern for forming a gate electrode is selectively provided on the polycrystalline silicon layer 4 on the element formation region.

Next, as shown in FIG.
Is used as a mask to remove the polycrystalline silicon layer 4 by reactive ion etching to form a gate electrode 6 and remove the photoresist film 5. Next, using the gate electrode 6 and the field insulating film 2 as a mask, arsenic is ion-implanted at an acceleration energy of 50 keV and a dose of 5 × 10 ¹³ cm ⁻² to form an N ⁻ type diffusion region 7 on the surface of the element formation region.

Next, as shown in FIG. 1C, a silicon oxide film 8 having a thickness of about 0.3 μm is formed on the surface including the gate electrode 6 by a vapor phase growth method.

Next, as shown in FIG. 1 (d), sidewall spacers are formed by anisotropic etching while leaving the silicon oxide film 8 only on the sidewalls of the gate electrode 6, and the silicon oxide film 8 in other regions is removed. . Next, using the gate electrode 6, the silicon oxide film 8 as a side wall spacer, and the field insulating film 2 as a mask, phosphorus is accelerated at an energy of 70 keV and a dose of 1 × 10 ¹⁴ cm.
^By ion implantation at ⁻² , an N ⁻ -type diffusion region 9 connected to the N ⁻ -type diffusion region 7 and having a junction surface deeper than the N ⁻ -type diffusion region 7 is formed on the surface of the element formation region.

Next, as shown in FIG. 1E, the gate electrode 6, the silicon oxide film 8, and the field insulating film 2 are again used as a mask, and arsenic is used at an acceleration energy of 50 keV and a dose of 3 × 10 ¹⁵ cm ^{− 2} is implanted to form a shallow N ⁺ type diffusion region 10 inside the N ⁻ type diffusion region 9.

Next, as shown in FIG. 1 (f), a PSG film 11 is deposited on the surface including the gate electrode 6 to form an interlayer insulating film.

Next, as shown in FIG. 1 (g), a contact window is selectively provided in the PSG film 11 on the N ⁺ type diffusion region 10, and an aluminum layer is deposited on the surface including the contact window. N ⁺ type diffusion region 10 of the contact window
And an electrode wiring 12 extending on the PSG film 11 is formed.

〔The invention's effect〕

As described above, according to the present invention, an insulating film is formed by forming a first low-concentration diffusion region on the surface of an element forming region in a self-aligned manner using a gate electrode and a field insulating film as a mask, and then covering only the side wall of the gate electrode. And a second low-concentration diffusion region in which a first-concentration impurity is ion-implanted into the surface of the element formation region in a self-aligned manner using the insulating film, the gate electrode, and the field insulating film as a mask. A second low-concentration diffusion region into which impurities having a high concentration are ion-implanted;
By forming a shallow high-concentration diffusion region in which a third concentration impurity is ion-implanted in the low-concentration diffusion region, the electric field intensity of the diffusion region can be reduced, and the deterioration of device characteristics due to the hot carrier effect can be suppressed. Having.

[Brief description of the drawings]

1A to 1G are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention, and FIG. 2 is a sectional view of a semiconductor chip for explaining an example of a conventional semiconductor device. It is sectional drawing. 1 ... P-type silicon substrate, 2 ... Field insulating film, 3
... Gate insulating film, 4 polycrystalline silicon layer, 5 photoresist film, 6 gate electrode, 7 N ^- type diffusion region, 8 silicon oxide film, 9 N ^- type diffusion region ,Ten…
... N ⁺ type diffusion region, 11 ... PSG film, 12 ... Electrode wiring.

Claims (1)

(57) [Claims] A step of selectively providing a field insulating film for element isolation on a main surface of a semiconductor substrate of one conductivity type to divide an element forming region, and forming a gate insulating film on a surface of the element forming region; Depositing a polycrystalline silicon layer on the surface including the gate insulating film and selectively etching to form a gate electrode; and ion-implanting a first concentration of a reverse conductivity type impurity using the gate electrode and the field insulating film as a mask. Implanting to form a first low-concentration diffusion region of the opposite conductivity type on the surface of the element forming region; and depositing a silicon oxide film on the surface including the gate electrode and etching back by anisotropic etching to form the gate. Forming a sidewall spacer while leaving the silicon oxide film only on the side surface of the electrode; and forming a sidewall spacer using the gate electrode, the sidewall spacer, and the field insulating film as a mask. An impurity of a reverse conductivity type having a higher concentration than the first concentration is ion-implanted and connected to the first low concentration diffusion region on the surface of the element forming region and deeper than the first low concentration diffusion region. Forming a second low-concentration diffusion region, and ion-transferring a third concentration of a reverse-conductivity-type impurity having a higher concentration than the second concentration into the second low-concentration diffusion region by using the mask again. Implanting to form a high concentration diffusion region.