KR0149130B1 - A pillar bipolar transistor and method for manufacturing the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a columnar bipolar transistor and a method for manufacturing the same, wherein an active region in which emitter regions, a base region, and a collector region are formed in a first pillar and a second pillar defined by trenches formed in a semiconductor substrate is defined by a first pillar. Since the base connection portion is electrically connected to the base region and a part of the polysilicon base electrode, the contact area is reduced to prevent the increase of the gray region of the base, and the high concentration used as the collector region during the reverse operation of the transistor. The emitter region and the base region do not form a high concentration junction.

Then, a polysilicon emitter electrode having a large surface area self-aligned by the CMP method is formed on the emitter region.

Therefore, since the active region of the transistor is limited to the first pillar, parasitic capacitance of the emitter and the collector and the base can be reduced, and the outer area of the base is increased because the contact area between the base region and the polysilicon base electrode is reduced. It is possible to improve the operating characteristics of the transistors by preventing them from being made, and to obtain a current gain similar to that in the forward operation in the reverse operation of the transistor.

In addition, since the polysilicon emitter electrode having a large surface area is self-aligned with the emitter region, it is easy to form contact openings for forming the emitter electrode.

Description

Columnar bipolar transistor and method of manufacturing the same

1 is a cross-sectional view of a bipolar transistor according to the prior art.

2 is a cross-sectional view of a bipolar transistor manufactured by a conventional wall base contact method.

3 is a cross-sectional view of the columnar bipolar transistor according to the present invention.

4 (a) to 4 (k) are manufacturing process diagrams for manufacturing the transistor of FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar transistor and a method for manufacturing the same, and more particularly, to a pillar bipolar transistor and a method for manufacturing the same, which can reduce parasitic capacitance of a base electrode and have bidirectional operating characteristics.

In recent years, bipolar transistors require high cutoff frequencies, low parasitic capacitances, and low parasitic resistances to improve operating speeds.

1 is a cross-sectional view of a bipolar transistor according to the prior art.

1, reference numeral 1 denotes a P-type semiconductor substrate, reference numeral 2 denotes an N ⁺ type buried region, reference numeral 3 denotes an N type collector region, and reference numeral 4 denotes an N ⁺ type sink region. Reference numeral 7 denotes a P-type base region, reference numeral 8 denotes an N ⁺ type actor region, reference numerals 5, 6 and 10 denote an insulating film, and reference numeral 9 denotes a metal electrode.

The metal electrode 9 is an emitter electrode, a base electrode, a collector electrode and an emitter electrode electrically connected to the emitter region 8, the base region 7 and the sink region 4, respectively.

In this case, the insulating film 5 is formed by filling trenches formed up to a predetermined depth of the semiconductor substrate 1 to separate the devices, thereby reducing the size of the devices and reducing the contact area between the semiconductor substrate 1 and the buried region 2. By reducing the parasitic junction capacitance.

Such a bipolar transistor has a problem in that power consumption is large due to an increase in junction capacitance because the base region is widely bonded to a high concentration of emitter region.

2 is a cross-sectional view of a bipolar transistor fabricated by a conventional wall base contact method and is disclosed in US patent application 443554.

Referring to Fig. 2, reference numeral 13 denotes an N-type collector region, reference numeral 17 denotes a P-type base region, and reference numeral 18 denotes an N ⁺ type emitter region.

The regions 13, 17, and 18 are provided in the cylindrical pillar 100 formed by etching of the P-type semiconductor substrate 11 and become active regions of the device. Reference numeral 15 denotes an N ⁺ type buried region formed on the semiconductor substrate 11, and reference numeral 15 denotes an N ⁺ type sink provided on another cylindrical pillar 101 formed on the semiconductor substrate 11.

The insulating layer 16 was filled to the predetermined height of the pillars 100 and 101 on the etched semiconductor substrate 11, and the poly was in contact with the side surface of the base electrode 17 on the insulating layer 16. The silicon base electrode 14 is formed.

In addition, reference numerals 98 and 99 denote insulating films, and reference numeral 20 denotes an electrical electrode with the emitter region 18, the polysilicon base electrode 14, and the sink 15, respectively, to the emitter electrode, the base electrode, and the collector electrode. The electrode used is shown.

In the bipolar transistor, since the emitter region 18 and the collector region 13 are bonded to the base region 17 in a narrow area, not only the parasitic capacitance is reduced but also the reverse current gain increases, thereby improving the reverse operating characteristics.

When the bipolar transistor operates in the reverse direction, the emitter region 18 in the forward operation becomes the collector tongue region, and the collector region 13 becomes the emitter region.

In the conventional bipolar transistors described above, the contact area of the base region is wider by the thickness of the polysilicon base electrode, so that the extrinsic base region of the base is increased, thereby deteriorating the operating characteristics of the transistor, the emitter region and the collector region. There is a problem that the power consumption is increased by the parasitic capacitor between the polysilicon base electrode.

Since the arbiter region and the base region are bonded at a high concentration, there is a problem in that the current gain is increased during reverse operation. In addition, a process of forming an insulating film and a base polysilicon electrode having a predetermined height in all areas except the pillars has been difficult. In addition, the emitter region has a problem in that it is difficult to form the emitter electrode on the upper part because the emitter region is formed on the upper part of the pillar having a small diameter.

Accordingly, an object of the present invention is to provide a columnar bipolar transistor that can improve the operating characteristics of the transistor by reducing the contact area between the base region and the base electrode.

Another object of the present invention is to provide a columnar bipolar transistor capable of reducing parasitic capacitance between the emitter and the collector tongue region and the base region.

It is still another object of the present invention to form a trench region around a pillar to facilitate the process of forming a polysilicon base electrode around the pillar, and to easily form the base polysilicon electrode by a mechanical chemical polishing process in the trench. The present invention provides a method for manufacturing a columnar bipolar transistor that can be embedded.

It is still another object of the present invention to provide a columnar biplane transistor having forward and reverse operations having similar current gains.

It is still another object of the present invention to provide a method of manufacturing a columnar bipolar transistor in which the emitter electrodes can be easily aligned by a self-aligning method.

A pillar bipolar transistor according to the present invention for achieving the above objects is a semiconductor substrate of a first conductive type having a trench having a predetermined depth defining a device region and having first and second pillars in the trench: within the semiconductor substrate trench. A high concentration of the second conductivity type impurity diffusion region formed around the bottom of the first column and in the entire area of the second column. The high concentration of the second conductivity type emitter region formed on the top of the first pillar. A base region of a first conductivity type formed in an intermediate portion of an impurity diffusion region and an emitter region: A sink of a high concentration second conductivity type which is an impurity diffusion region formed in the second pillar: buried in the trench by a predetermined depth lower than that of the pillar. Polysilicon base electrode of a first conductivity type, wherein the polysilicon base electrode is used to electrically isolate the polysilicon base electrode from the semiconductor substrate First insulating oxide film formed in the tooth: a first conductive type base connection portion formed to partially connect between the base region and the polysilicon base electrode: a highly conductive second conductive type poly formed self aligned with the emitter region Silicon emitter electrode: A second insulating oxide film to prevent the polysilicon emitter electrode and the polysilicon base electrode is electrically connected: Emitter metal electrode formed on the polysilicon emitter electrode, poly silicon base electrode and the sink And a base metal electrode and a collector metal electrode.

According to another aspect of the present invention, there is provided a method of manufacturing a columnar bipolar transistor, in which a trench is etched to form first and second pillars by defining a device region in a silicon substrate of a first conductivity type. Forming a high concentration of impurity diffusion region and a sink in the peripheral region of the lower pillar and the second pillar: depositing a first insulating oxide film and polysilicon of the first conductive type on the entire surface of the semiconductor substrate; Removing the polysilicon so that the first insulating oxide film deposited on the unetched portion of the semiconductor substrate is exposed and burying the inside of the trench: etching the polysilicon layer to a predetermined depth inside the trench to form a polysilicon base electrode Process of defining: etching the first insulating oxide film around the exposed first pillar to a predetermined depth, the first etching oxide film Forming a base connection portion by filling a polysilicon of a conductive type: depositing a second insulating oxide film and polysilicon on the entire surface of the semiconductor substrate and planarizing by removing the polysilicon using the second insulating oxide film as a polishing stop film The process of exposing the surface of a 1st pillar by selectively removing the 2nd oxide film of a said 1st columnar part: The impurity of a 1st conductivity type and an impurity of a 2nd conductivity type are sequentially made to the exposed said 1st pillar. Ion implantation and heat treatment to form a base region of a first conductivity type and an emitter region of a second conductivity type connected to the base connection portion: having a larger surface area than that of the emitter region above the emitter region A step of forming a self-aligned second type of polysilicon emi-tungsten electrode: and an upper portion of the second insulating oxide film and the polysilicon emitter electrode And forming a hole so that the polysilicon base electrode, the polysilicon emitter electrode, and the sink are exposed after forming a protective film on the protective film.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is a cross-sectional view of a columnar bipolar transistor according to an embodiment of the present invention.

The bipolar transistor includes a wrench 22 defining a device region in a predetermined portion of the P-type semiconductor substrate 21 and first and second pillars 41 and 42 inside the trench 22.

The first and second pillars 41 and 42 have a diameter of about 0.3 to 2 μm and a height of about 0.7 μm to about 2 μm, and have phosphorus (P) or arsenic (As) on the substrate 21 at the bottom. An N ⁺ type impurity diffusion region 23 doped with N type impurities such as 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ^{2 at} a high concentration is formed.

An N ⁺ type emitter region 28 doped with a high concentration of about 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ² is formed on the first pillar 41, and boron (B) is formed. A P-type base region 27 doped with P-type impurities of about 5 × 10 ¹⁶ to 5 × 10 ¹⁹ / cm ² is formed between the impurity diffusion region 23 and the emitter region 28. .

Therefore, the active region of the device is limited to the first pillar 41.

In addition, the entirety of the second pillar 42 is an N ⁺ type sink 39 doped with N-type impurities electrically connected to the dust impurity diffusion region 23 at about 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ^2. ) Is formed.

The trench 22 has a first insulating oxide film 34 and a P-type polysilicon base electrode 24 formed therein to fill a predetermined height.

In the above, the polysilicon base electrode 24 is doped with the P-type impurities at about 5 × 10 ¹⁶ to 5 × 10 ¹⁹ / cm ^2, and the upper surface thereof is lower than the top of the base region 27.

The first insulating oxide film 34 has a thickness of about 1500 ~ 2500Å, the upper part of which coincides with the surface of the polysilicon base electrode 24 at the sides of the trench 22 and the second pillar 42, and the first pillar. The lower side of the (41) is formed by a predetermined difference than the polysilicon base electrode 24.

A P-type base connection part 25 in which the P-type impurity is doped about 1 × 10 ¹⁸ to 1 × 10 ¹⁹ / cm ² is formed between the base region 27 and the polysilicon base electrode 24.

The base connecting portion 25 is electrically connected between the base region 27 and the polysilicon base electrode 24, and the upper portion thereof is formed lower than the upper portion of the base region 27.

Therefore, the polysilicon base electrode 24 is not only electrically isolated from the impurity diffusion region 23 and the sink 39 by the first insulating oxide film 34 but also by the base connection portion 25. Is electrically connected to the

An N-type polysilicon emitter electrode 26 having a thickness of about 2000 to 4000 microns doped with N-type impurities at about 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ² is formed on the emitter region 28. It is formed by self-alignment.

A metal electrode 29 used as an emitter electrode, a base electrode and a collector electrode is formed on the polysilicon emitter electrode 26, the polysilicon base electrode 24, and the sink 39.

In FIG. 3, reference numerals 34, 36, and 37 denote first, second, and third insulating phase films, and in particular, the second insulating oxide film 36 includes a polysilicon emitter electrode 26 and a polysilicon base. The electrode 24 is prevented from being electrically connected.

In the above-described bipoly transistor, since the active region is limited to the first pillar 41, the junction surface of the impurity diffusion region 23 and the base region 27 used as the emitter region 28 and the collector region is reduced.

Therefore, the parasitic capacitance between the emitter and the collector and the base can be reduced.

Since the base connecting portion 25 electrically connects the base region 27 and the polysilicon base electrode 24, the contact area is reduced to prevent the external region of the base from increasing, thereby improving the operating characteristics of the transistor. In addition, the high concentration emitter region 28 used as the collector region during the reverse operation of the transistor does not form a high junction with the base region 27, and the junction area between the emitter and the collector region and the base region is the same. Current gain similar to that in forward operation can be obtained.

In addition, although the above-described bipolar transistor has been described as having one first pillar and one second pillar respectively formed inside the trench defining the device region, a plurality of first pillars may be formed, and an impurity diffusion region may be commonly used. have.

4 (a) to 4 (k) show a manufacturing process of the columnar bipolar transistor according to the present invention.

Referring to FIG. 4 (a), an oxide film 32 having a thickness of about 4000 to 6000 μs is formed on the P-type silicon substrate 21 by chemical vapor deposition (hereinafter, referred to as CVD). After that, the oxide film 32 is removed to expose a predetermined portion of the semiconductor substrate 21 by a normal photo process.

Then, using the oxide film 32 as an etching mask, the exposed portion of the semiconductor substrate 21 is anisotropically etched by a dry etching method such as reactive ion etching (hereinafter referred to as RIE) method, and then 0.7 to 2 μm. A trench 22 of depth is formed.

In forming the trench 22, the first and second pillars 41 and 42 each having a diameter of about 0.3 μm to 2 μm are formed so that a predetermined portion inside the trench 22 is not removed.

A pair of the first and second pillars 41 and 42 corresponds to a unit element, and a pair or a plurality of pairs such that a single element unit or a plurality of elements may be formed in the trench 22. Can be formed.

Referring to FIG. 4 (b), the oxide substrate 32 having the above-described structure from which the oxide oxide 32 is removed except for the one formed on the upper portion of the first pillar 41 is about 1500-3000 mm by the oxidation method. An oxide film 33 having a thickness is formed.

At this time, the oxide film 33 is also formed on the oxide film 32.

Then, a photomask (not shown) is formed on the upper portion of the semiconductor substrate 21 except for a predetermined portion including the first and second pillars 41 and 42 inside the trench 22, and then the RIE method is used. The exposed oxide film 33 is removed.

At this time, the oxide film 33 formed on the side surfaces of the first and second pillars 41 and 42 where the photomask is not formed is not removed, and the oxide film 32 on the upper portion of the first pillar 41 is also removed. It is not removed.

After the photomask is removed, N-type impurities such as phosphorus (P) or arsenic (As) are removed in a size of 1 × 10 ²⁰ to 1 × 10 ²¹ / cm using the non-removed oxide layers 32 and 33 as diffusion masks. ^It is leveled to about ² high concentrations, and the N ⁺ type impurity diffusion region 23 and the N ⁺ type sink 39 are formed.

Referring to FIG. 4C, after the oxide films 32 and 33 are removed, the first insulating oxide film 34 having a thickness of about 1500 to 2500 Å is formed on the entire surface of the semiconductor substrate 21 by the CVD method. To form.

In addition, the polysilicon layer 24 ′ doped with P-type impurities such as boron at about 5 × 10 ¹⁸ to 5 × 10 ²⁰ / cm ² by the CVD method on the first insulating oxide film 34 is 1.5 to 2.5 μm. It is formed to a thickness of about.

Referring to FIG. 4 (d), the mechanical mechanical polishing is performed such that the first insulating oxide layer 34 is exposed so that only the polysilicon layer 24 ′ is embedded in the trench 22. CMP) to planarize.

In this case, the first insulating oxide film 34 is used as a polishing stopper.

Referring to FIG. 4E, after the embedded polysilicon layer 24 'is etched at about 3000 to 5000Å by the RIE method, the first insulating oxide film 34 is first and second pillars 41 to be etched. The thickness of the first insulating oxide film 34 is etched so that 42 is exposed without damaging the surface.

Then, a photo mask (not shown) is formed on the semiconductor substrate 21 on the remaining portions except around the first pillar 41.

In addition, the exposed portion of the first insulating oxide layer 34 is selectively wet-etched by about 1000 to 3000 Pa by using the photomask as an etching mask to increase the exposed portion of the side surface of the first pillar 41.

What remains of the polysilicon layer 24 ′ without being polished is the polysilicon base wire 24.

Referring to FIG. 4 (f), 1 × 10 ¹⁸ to 1 × of P-type impurities are formed on the first insulating oxide film 34 between the first pillar 41 and the polysilicon base electrode 24. A P-type base connection portion 25 doped at about 10 ¹⁹ / cm ² is formed.

In the above, the base connecting portion 25 is formed by applying polysilicon and etching so that the upper surface coincides with the upper surface of the polysilicon base electrode 24.

Referring to FIG. 4 (g), a second insulating oxide film 36 having a thickness of about 1500 to 2500 kPa is formed on the entire surface of the structure described above by the CVD method.

The second insulating oxide film 36 is formed to be connected to the first insulating oxide film 34.

Referring to FIG. 4 (h), the polysilicon 35 is deposited on the entire surface of the second insulating oxide film 36 by CVD, and then the polysilicon 35 is deposited on the second insulating oxide film 36. It is polished and planarized by the CMP method used as a polishing stop film.

Referring to FIG. 4 (i), after forming a photomask (not shown) on the remaining portion except for the second insulating oxide film 36 on the first pillar 41, the second insulating oxide film 36 may be formed. The exposed portion is removed to expose the upper portion of the first pillar 41 by a selective etching method.

After removing the photo mask, P-type impurities are sequentially doped with P-type and N-type impurities in the first pillar 41 and heat-treated to obtain P-type impurities of about 5 × 10 ¹⁶ to 5 × 10 ¹⁸ / cm ^2. The base region 27 of the type and the N type impurity form an emitter area 28 of the N ⁺ type doped at a high concentration of about 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ² .

In the above, the base region 27 is formed in the middle of the impurity diffusion region 23 and the emitter region 28 so as not to be bonded at a high concentration.

Referring to FIG. 4 (j), the polysilicon having a thickness of about 2000 to 4000 microns doped with N-type impurities at about 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ² on the entire surface of the structure described above is emitter. Deposited in contact with region 28.

The polysilicon is then patterned to form a self-aligned polysilicon emitter electrode 26 having a larger area than the emitter region 28.

Referring to FIG. 4 (k), an oxide film 37 having a thickness of about 5000 to 7000 Å is deposited on the second insulating oxide film 34 and the polysilicon emitter electrode 26.

Then, the upper portions of the polysilicon base electrode 24, the polysilicon emitter electrode 26 and the sink region 39 are exposed to form a metal electrode 29 used as the base electrode, the emitter electrode and the collector electrode. .

In the above, since the surface area of the polysilicon emitter electrode 26 is wide, it is easy to form contact life with the metal electrode 29.

As described above, the bipolar transistor and the method of manufacturing the same according to the present invention define the active region in which the emitter region, the base region, and the collector region are formed in the first pillar in the first and second pillars defined by the trenches formed in the semiconductor substrate. Since the base connection portion is electrically connected to the base region and a small portion of the polysilicon base electrode, the contact area is reduced to prevent the increase of the external region of the base, and the high concentration used as the collector region during the reverse operation of the transistor. The emitter and base regions of do not form a high concentration junction.

After removing the second insulating oxide layer on the emitter region by the CMP method, a polysilicon emitter electrode having a large surface area that is self-aligned is formed.

Therefore, the present invention can reduce the parasitic capacitance between the emitter and the collector and the base since the active region of the transistor is limited to the first pillar, and reduces the contact area between the base region and the polysilicon base electrode, thereby reducing the external characteristics of the base. It is possible to prevent the area from being increased to improve the operating characteristics of the transistor, and also to obtain an overall gain similar to that in the forward operation during the reverse operation of the transistor.

In addition, since the polysilicon emitter electrode having a large surface area is self-aligned with the emitter region, it is easy to form contact openings for forming the emitter electrode.

Claims (11)

A first conductive semiconductor substrate having a trench having a predetermined depth defining an element region, and having first and second pillars in the trench; A high concentration of second conductivity type impurity diffusion region formed around the lower end of the first pillar and in the entire region of the second pillar in the semiconductor substrate trench; An emitter region of a high concentration second conductivity type formed on the first pillar; A base region of a first conductivity type formed at an intermediate portion of the impurity diffusion region and the emitter region of the first pillar; A highly concentrated second conductive type sink that is an impurity diffusion region formed in the second pillar; A polysilicon base electrode of a first conductivity type buried in the trench by a predetermined depth lower than the pillar; A first insulating oxide film formed in the trench to electrically isolate the polysilicon base electrode and the semiconductor substrate; A base connection portion of a first conductivity type formed to partially connect between the base region and the polysilicon base electrode; A high concentration of the second conductive polysilicon emitter electrode formed in self alignment with the emitter region; A second insulating oxide film preventing electrical connection between the polysilicon emitter electrode and the polysilicon base electrode; And a polysilicon emitter electrode, a polysilicon base electrode, and an emitter metal electrode, a base metal electrode, and a collector metal electrode formed on the sink. The columnar bipolar transistor of claim 1, wherein the first and second pillars have a diameter of 0,3 to 2 μm and a height of 0.7 to 1.5 μm. The columnar bipolar transistor according to claim 1, wherein the first insulating oxide film is formed to a thickness of 1500 to 2500 Å. The pillar-shaped bipolar transistor of claim 1, wherein the first insulating layer has a lower side of the first pillar than the side of the trench and the second pillar by 1000 to 3000 μs. The columnar bipolar transistor according to any one of claims 1 to 4, wherein at least one first pillar is formed in the trench. Trench-etching the first and second pillars by forming a device region in the first conductive silicon substrate; Forming a sink with an impurity diffusion region having a high concentration of the second conductivity type in the peripheral region and the second pillar at the bottom of the first pillar; After depositing a first insulating oxide film and a polysilicon of the first conductivity type on the front surface of the semiconductor substrate, the polysilicon is removed to expose the first insulating oxide film deposited on the unetched portion of the semiconductor substrate to expose the inside of the trench. Buried in; Etching the polysilicon layer to a predetermined depth inside the trench to define a polysilicon base electrode; Etching the first insulating oxide film around the exposed first pillar to a predetermined depth, and filling the etched portion with polysilicon of a first conductivity type to form a base connection portion; Depositing a second insulating oxide film and polysilicon on the entire surface of the semiconductor solid plate and removing and planarizing the polysilicon by using the second insulating underlayer as a polishing stop film; Selectively removing the second oxide film on the first pillar to expose the surface of the first pillar; The first conductive type base region and the second conductive type emitter region which are connected to the base connection part by ion implantation and heat treatment of the first conductive type impurity and the second conductive type impurity in the exposed first column Forming a; Forming a self-aligned polysilicon emitter electrode having a surface area larger than that of the emitter region on top of the emitter region; And forming a hole on the second insulating oxide film and the polysilicon emitter electrode, and forming a hole to expose the polysilicon base electrode, the polysilicon emitter electrode, and the sink, and forming the electrode. Method for producing a bipolar transistor. A columnar bipolar is formed on the upper side of the first pillar to leave the oxide film used as a mask during the trench etching and the oxide film used as a diffusion mask on the side surface, and to diffuse the second conductive type impurities to form the impurity diffusion region and the sink. Method for manufacturing a transistor. The method of manufacturing a columnar bipolar transistor according to claim 7, wherein an oxide film, which is used as a diffusion mask when forming the impurity buried bran and the sink, is formed to a thickness of 1500 to 3000 GPa. The method of claim 6, wherein the polysilicon is defined inside the trench by a mechanical mechanical polishing method using the first insulating oxide film as a polishing stop film. The method of manufacturing a pillar bipolar transistor according to claim 6, wherein the first oxide film around the exposed first pillar is selectively wet etched at about 1000 to 3000 Pa, and the etched portion is filled with polysilicon of first degree typical. . The method of manufacturing a columnar bipolar transistor according to any one of claims 6 to 10, wherein at least one first pillar is formed in the trench.