JP2987850B2 - Semiconductor integrated circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit having a dynamic RAM element.

[Conventional technology]

A dynamic RAM cell having a groove-type capacitance portion has been realized as one method of increasing the degree of integration of a semiconductor integrated circuit.

2 (a) to 2 (f) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a conventional method of manufacturing a semiconductor integrated circuit.

As shown in FIG. 2A, a field oxide film 20 is formed on the surface of the P-type silicon substrate 1 by the LOCOS method.
At this time, boron is ion-implanted immediately below the field oxide film 20 as a channel stopper 21. Further, after forming a thermal oxide film 2 as a sacrificial oxide film, a silicon nitride film 3 is formed by a vapor deposition method, and after selectively removing the silicon nitride film 3, a photoresist film 4 is formed and patterned.

Next, as shown in FIG. 2 (b), the photoresist film 4 is masked, and reactive ion etching (hereinafter referred to as "reactive ion etching") is performed.
The groove 5 is formed by etching the silicon substrate 1 from the surface in the depth direction by RIE. Further, boron ions are implanted using the photoresist film 4 as a mask,
An HiC structure is formed on the surface inside the groove 5, and thereafter, the photoresist film 4 is removed by plasma stripping, and arsenic ions are selectively ion-implanted to form an N-type diffusion layer 7.

Next, as shown in FIG. 2C, 4 to 6 n
A silicon oxide film 8 having a thickness of m and a silicon nitride film 9 having a thickness of 10 to 20 nm are formed. The silicon nitride film 9 is oxidized in a steam atmosphere at 980 ° C. for 10 to 20 minutes in order to improve the dielectric strength. The polycrystalline silicon layer 10 is formed on the dielectric layer (the double layer of the silicon oxide film 8 and the silicon nitride film 9) of the flat capacitor thus formed by repeating the vapor phase growth method and the etch back. be able to. At this time, in order to reduce the resistivity of the polycrystalline silicon layer 10, it is necessary to diffuse an N-type impurity such as phosphorus. Next, a photoresist film 11 is applied on the polycrystalline silicon layer 10 and patterned.

Next, as shown in FIG.
After the polysilicon layer 10 is plasma-etched using the mask as a mask to remove the photoresist film 4, an insulating layer 12 is formed on the surface of the polysilicon layer 10 by oxidation. afterwards,
Using the insulating layer 12 as a mask, boron ions for controlling the threshold voltage of the transistor are implanted to form a P ⁺ type region 13.

Next, as shown in FIG. 2 (e), after removing the silicon nitride film 9 and the silicon oxide film 8 using the insulating film 12 as a mask, a gate oxide film 14 is formed, and further, as a gate electrode of the transistor. Is deposited, and after phosphorus diffusion, patterning is performed. Next, an insulating film 16 is formed by oxidizing the surface of the polycrystalline silicon layer 15 and the silicon substrate 1 is formed using the polycrystalline silicon layer 15 as a mask.
Next, an N-type diffusion layer 17 is formed.

Next, as shown in FIG. 2 (f), a PSG film, a silicon nitride film and the like are deposited on the entire surface by a vapor phase growth method to form an interlayer insulating film 18.
To form Next, a contact hole is provided in the interlayer insulating film 18 on the N-type diffusion layer 17, and an ohmic contact is made with a wiring 19 provided by patterning an aluminum layer, thereby forming a memory cell.

[Problems to be solved by the invention]

The above-described conventional semiconductor integrated circuit has an advantage that the capacitance per unit surface area can be increased as compared with the planar type, but the groove-type capacitance portion has about 5 to 7 μm from the surface of the silicon substrate 1. The depth of the groove must be formed, the shape of the lower part of the groove becomes steep, and sufficient cleaning is not performed, so that the dielectric breakdown voltage of the dielectric layer formed at the bottom of the groove becomes low. There was a point.

In addition, the HiC structure formed on the groove side surface also has a small groove radius with respect to the depth direction, so that a large ion implantation angle cannot be obtained, and it is difficult to form the ion uniformly and efficiently. there were. For this reason, there has been a problem that the dielectric strength of the dielectric layer formed at the bottom of the groove is low.

Further, there is a problem that the field oxide film formed in the lateral direction is a factor that hinders high integration.

[Means for solving the problem]

The semiconductor integrated circuit according to the present invention has a first groove provided on one main surface of a one-conductivity-type semiconductor substrate, and is provided on the entire side surface and bottom surface of the first groove and a part of an outer upper end surface continuous with the side surface. A dielectric layer, a polycrystalline silicon layer provided to fill the inside of the first groove, and a narrower inside the first groove than the width of the first groove and deeper than the first groove. A second groove provided to divide the polycrystalline silicon layer; an insulating film filling the inside of the second groove to insulate the divided polycrystalline silicon layers from each other and cover the surface thereof; A reverse conductivity type diffusion layer provided on the semiconductor substrate at an upper end corner of the first groove so as to include the dielectric layer on the outer upper end surface; and a diffusion layer provided on the surface of the semiconductor substrate including the diffusion layer. An active element.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

1 (a) to 1 (g) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention.

First, as shown in FIG. 1A, a surface of a P-type silicon substrate 1 is thermally oxidized to form a thermal oxide film 2 having a thickness of 40 to 50 nm. Silicon nitride film 3
Is deposited. Next, the silicon nitride film 3 is selectively etched by a photolithography technique to form a first opening, and a photoresist film 4 is applied to a surface including the first opening and patterned to form a first opening. The second opening is provided inside the opening. Next, using the photoresist film 4 as a mask, the thermal oxide film 2 and the silicon substrate 1 are sequentially etched by reactive ion etching (hereinafter referred to as RIE) to form a groove 5.

Next, as shown in FIG.
Is used as a mask to sequentially implant boron ions and arsenic ions to form a HiC structure portion 6 for increasing the capacitance. Next, after removing the photoresist film 4 by plasma stripping, N-type impurities are ion-implanted into the surface of the silicon substrate using the silicon nitride film 3 as a mask to form a first N-type diffusion layer 7 to form a source / drain region. Is provided. Next, the inside surface of the groove 5 is oxidized to form a silicon oxide film 8 having a thickness of 4 to 6 nm, and a silicon nitride film 9 having a thickness of 10 to 20 nm is deposited on the surface including the groove 5. Next, in order to improve the withstand voltage of the silicon nitride film 9, an oxidation treatment is performed for 10 to 20 minutes in a 980 ° C.
And a dielectric layer of a capacitor formed by laminating the silicon nitride film 9. Next, a polycrystalline silicon layer 10 is deposited on the surface including the groove 5 by a vapor phase growth method, and phosphorus is diffused to lower the resistivity.

Next, as shown in FIG. 1 (c), an organic silicon agent containing no oxygen is applied by a spin-on method and heat-treated in an inert atmosphere to form a buried polycrystalline silicon layer 11. Next, the surfaces of the polycrystalline silicon layer 10 and the buried polycrystalline silicon layer 11 are etched to flatten the plane.

Next, as shown in FIG. 1D, the polycrystalline silicon layer 10 and the silicon nitride film 9 on the silicon nitride film 3 other than the groove 5 are formed.
Is selectively removed by etching. Next, the polycrystalline silicon layers 11 and 10 at the center of the groove 5 and the silicon nitride film 9 and the silicon oxide film 8 at the bottom of the groove 5 are sequentially etched by RIE to form a groove 22 deeper than the HiC structure 6. Then, the polycrystalline silicon layer 10 is divided. Next, the grooves 22 are formed by a vapor growth method.
The insulating film 12 is provided by depositing a silicon oxide film on the surface containing Then, a capacitor divided by the insulating film 12 is formed.

Next, as shown in FIG. 1 (e), the oxide film and the silicon nitride film 3 in the region other than the trench 5 are selectively etched and removed sequentially using buffered hydrofluoric acid and hot phosphoric acid. Boron ions for controlling a threshold voltage are ion-implanted to form a P ⁺ type region 13. Next, the thermal oxide film 2 is removed, and a gate oxide film 14 is formed on the surface of the silicon substrate 1 by thermal oxidation.

Next, as shown in FIG. 1 (f), a polycrystalline silicon layer 15 is deposited on the entire surface by vapor phase epitaxy.
Diffusion of phosphorus in 15. Next, the polycrystalline silicon layer 15 is selectively etched to form a gate electrode, and the surface of the polycrystalline silicon layer 15 is oxidized to form an insulating film 16. Next, using the gate electrode made of the polycrystalline silicon layer 15 as a mask,
An N-type diffusion layer 17 is formed by ion-implanting a type impurity.

Next, as shown in FIG. 1 (g), an interlayer insulating film 18 such as a PSG film or a silicon nitride film is deposited on the entire surface and selectively etched to form a contact hole. Next, an aluminum layer is deposited and patterned on the surface including the contact hole, and a wiring 19 that makes ohmic contact with the N-type diffusion layer 17 of the contact hole is provided to form a memory cell.

〔The invention's effect〕

As described above, the present invention relates to one groove,
Since one element is formed, the radius of the groove can be increased by that amount, and the cleaning of the groove after etching becomes easy, and at the same time, the uniformity of ion implantation to the side surface of the groove,
The film quality uniformity of the silicon oxide film and the silicon nitride film constituting the dielectric layer is improved.

Further, since the region corresponding to the field oxide film is formed on the polycrystalline silicon film, the surface area of the substrate is not necessary and the integration can be increased.

Further, in the past, a polycrystalline silicon layer of a capacitor portion was formed on a field oxide film for element isolation, but in the present invention, a polycrystalline silicon layer of a capacitor portion was formed below an insulating film. Therefore, the resistance of alpha rays has also become stronger.

[Brief description of the drawings]

1 (a) to 1 (g) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention, and FIGS. 2 (a) to 2 (f) are conventional semiconductor integrated circuits. FIG. 7 is a cross-sectional view of a semiconductor chip shown in the order of steps for describing the manufacturing method of FIG. DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Thermal oxide film, 3 ... Silicon nitride film, 4 ... Photoresist film, 5 ... Groove, 6 ... HiC
Structure part, 7 ... N-type diffusion layer, 8 ... Silicon oxide film, 9
…… Silicon nitride film, 10… Polycrystalline silicon layer, 11 ……
Buried polycrystalline silicon layer, 12 ... insulating film, 13 ... P ⁺ type region, 14 ... gate oxide film, 15 ... polycrystalline silicon layer,
16 ... insulating film, 17 ... N-type diffusion layer, 18 ... interlayer insulating film,
19: wiring, 20: field oxide film, 21: channel stopper, 22: groove.

Claims (1)

(57) [Claims] A first conductive substrate provided on one principal surface of the semiconductor substrate;
Groove, a dielectric layer provided on the entire side surface and bottom surface of the first groove and a part of an outer upper end surface continuous with the side surface, and polycrystalline silicon provided by filling the inside of the first groove A second groove that is provided inside the first groove and is smaller than the width of the first groove and deeper than the first groove to divide the polycrystalline silicon layer; An insulating film that fills the interior and insulates the divided polycrystalline silicon layers from each other and covers the surface thereof; and the dielectric layer on the outer upper end surface of the semiconductor substrate at the upper end corner of the first groove. A semiconductor integrated circuit comprising: a reverse conductivity type diffusion layer provided so as to include the active layer; and an active element including the diffusion layer and provided on a surface of the semiconductor substrate.