JP2513287B2 - Method for manufacturing stacked memory cell - Google Patents

Description

The present invention relates to a dynamic memory (DRAM) cell including one MOS transistor and one capacitor, and more particularly to a stacked memory cell in which a capacitor is stacked on the transistor. Manufacturing method.

[Conventional technology]

Conventionally, a standard manufacturing method of this type of stacked memory cell will be described with reference to the drawings.

As shown in FIG. 3A, an element isolation oxide film 2 is formed on a P-type silicon substrate 1, a polycrystalline silicon film and a silicon oxide film 5 are deposited and patterned to form a gate electrode 4, and then ion implantation is performed. Then, the n ⁻ layer 6 is formed, sidewalls are formed as shown in FIG. 3 (b), the n ⁺ layer 8 is formed by ion implantation, and then the bit line contact hole 9 and the capacitance contact hole 10 are opened. To do. As shown in FIG. 1 (c), a polycrystalline silicon film 6 is vapor-deposited on the entire surface, and then a bit line electrode 11 and a capacitor electrode 12 are formed by lithography and etching as shown in FIG. 3 (d). To do. Next, as shown in FIG. 3 (e), a capacitive insulating film 13 and an insulating film 14 are formed by thermal oxidation, and then a polycrystalline silicon film 15 is formed. Next, as shown in FIG. 3 (f), the polycrystalline silicon film 15 is patterned to form a cell plate electrode 16.

[Problems to be Solved by the Invention]

In the conventional method for manufacturing a stacked memory cell described above, a polycrystalline silicon film to serve as a capacitor electrode is grown on a step portion formed by a gate electrode, a hole with a substrate is aligned with high accuracy, and a resist is formed. A pattern is formed, and the polycrystalline silicon film is anisotropically etched using this as a mask. Since there is a step in the gate electrode, it is difficult to anisotropically etch the polycrystalline silicon film without leaving any residue, and some side etching occurs. For this reason, the surface area of the capacitance electrode is smaller than the mask size, and there is a drawback that the capacitance is insufficient. Particularly, when the memory cell area becomes 10 μm ² or less, this problem becomes serious, and if the polycrystalline silicon film thickness is increased to increase the capacitance (increasing the capacitance on the side surface), etching becomes more difficult.

Further, due to the step due to the stack capacitance, the bit line contact hole for the diffusion layer of the substrate becomes deep. In order to connect the metal wiring to this diffusion layer, it becomes necessary to fill the contact hole with a conductive material. Therefore, there is a drawback that the manufacturing method becomes more complicated.

[Means for Solving the Problems] A method of manufacturing a stacked memory cell according to the present invention is to provide a gate electrode on one main surface of a semiconductor substrate through a gate insulating film in a self-aligned manner with the source (or drain). ) Region to form a memory cell transistor, a self-alignment with the gate electrode of the memory cell transistor to form a contact hole in an insulating film on the source (or drain) region, and the contact hole. And selectively epitaxially growing silicon on the portion to form one capacitance electrode of the memory cell capacitor.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

1A to 1E are cross-sectional views of semiconductor chips arranged in the order of steps for explaining an embodiment of the present invention.

As shown in FIG. 1A, for example, a P-type silicon substrate
An element isolation oxide film 102 is formed on a 101 substrate by, for example, a selective oxidation method. After growing the gate oxide film 103 by thermal oxidation, after depositing a polycrystalline silicon film and a silicon oxide film 105,
The gate electrode 104 is formed by patterning by usual lithography and etching. Next, an n ⁻ region 106 is formed by ion implantation for the source / drain region of the MOS transistor. Next, a sidewall 107 made of an oxide film is formed on the side surface of the gate electrode. That is, anisotropic etching is performed after depositing a silicon oxide film of about 0.1 to 0.3 μm. Then, the bit line contact hole 109 and the capacitor contact hole 110 can be formed in self-alignment with the gate electrode. Next, an n ⁺ layer 108 is formed for the source / drain region.
Is formed by ion implantation. Next, bit line contact hole 10
Nine portions are covered with a silicon oxide film 118 by the CVD method, and silicon is selectively grown in the portion of the capacitor contact hole 110 where the silicon substrate is exposed to form a capacitor electrode 112. Selective growth of silicon is widely known as a selective epitaxial growth method. In selective epitaxial growth, epitaxial growth proceeds not only vertically but also laterally. Therefore,
As shown in FIG. 1C, a silicon layer having a preferable shape as a capacitor electrode is formed in self-alignment with the capacitor contact hole 110. Strict alignment with respect to the capacitance contact hole and patterning and etching of the capacitance electrode on the step of the gate electrode, which are usually problems in manufacturing a stacked memory cell, are unnecessary. The selectively grown silicon layer that serves as one of the capacitance electrodes of the memory cell capacitor needs to be n-type doped. To this end, it is desirable to dope during selective epitaxial growth. Next, as shown in FIG. 1D, a capacitive insulating film 113 is formed and a cell plate electrode 116 is formed.
By forming (the other electrode of the memory cell capacitor), the storage capacitor section is completed. Next, as shown in FIG. 1 (f), an interlayer insulating film 117 is formed to have a flat surface, and a bit line contact hole 109 'for connecting the bit line 119 to the diffusion layer is opened. If the thickness of the interlayer insulating film is large and the diameter of the contact hole is small, it becomes difficult for the conductor of the bit line to cover the contact hole, and sufficient electrical connection cannot be obtained. It is necessary to fill the conductor 123 in advance before forming the bit line 119. Finally, the bit line 119 is wired to complete the memory cell portion.

2 (a) and 2 (b) are sectional views of semiconductor chips arranged in the order of steps for explaining the second embodiment.

The first embodiment requires a buried conductor to fill the bit line contact hole. The second embodiment is a method in which the filling of the contact hole is also performed by selective epitaxial growth and is formed simultaneously with the capacitor portion. The steps up to forming the sidewall 207 for self-aligned contact and forming the n ⁺ layer 208 are the same as those in the first embodiment. Next, as shown in FIG. 2A, epitaxial silicon films 220a and 220b are simultaneously formed by selective epitaxial growth in the bit line contact hole 209 and the capacitor contact hole 210. Next, as shown in FIG. 2B, only the bit line contact hole portion is covered with the mask silicon oxide film 221, and selective growth of silicon is performed again to perform the epitaxial silicon film 222.
To form a capacitive electrode composed of 220b and 222. In the formation of the epitaxial silicon film 222, the selective epitaxial growth also proceeds in the lateral direction, so that a large area can be taken to some extent, so to speak, patterning can be performed simultaneously. Although the mask silicon oxide film covers the bit line contact portion here, it may be the normal contact portion of the transistor in the peripheral circuit.

The subsequent steps may be performed according to the conventional example. Note that, depending on the case, it is apparent that the selective epitaxial growth may be performed again in contact holes other than the capacitor contact hole.

[Effects of the Invention] As described above, according to the present invention, the selective epitaxial growth of silicon is performed in the contact hole portion provided in the insulating film on the source (or drain) region of the memory cell transistor to form one capacitance electrode of the memory cell capacitor. Since it is formed, the alignment with the contact hole is automatically performed, so that it is not necessary to form the capacitor electrode pattern by lithography. Further, it is not necessary to etch the capacitor electrode on the step of the gate electrode. Therefore, the capacitance electrode can be formed in a short manufacturing process without being restricted by the lithography technique or the etching technique, so that the dynamic semiconductor memory can be easily highly integrated or have high performance.

[Brief description of drawings]

FIGS. 1 (a) to 1 (e) are sectional views of a semiconductor chip arranged in the order of steps for explaining the first embodiment of the present invention, and FIG.
FIGS. 3A to 3B are cross-sectional views of semiconductor chips arranged in the order of steps for explaining the second embodiment, and FIGS.
6F is a sectional view of semiconductor chips arranged in the order of steps for explaining a conventional method of manufacturing a stacked cell. FIG. 1,101,201 …… P-type silicon substrate, 2,102,202 …… Element isolation oxide film, 3,103 …… Gate oxide film, 4,104,204 …… Gate electrode, 5,105 …… Silicon oxide film, 6,106 …… n ^- layer, 7,
107,207 …… Sidewall, 8,108,208 …… n ⁺ layer, 9,10
9 …… bit line contact hole, 10,110 …… capacitance contact hole, 11 …… bit line electrode, 12,112 …… capacitance electrode, 13,1
13 …… Capacitance insulating film, 14 …… Insulating film, 15 …… Polycrystalline silicon film, 16,116 …… Cell plate electrode, 17,117 …… Interlayer insulating film, 118 …… Silicon oxide film, 19,19 ′, 119 …… Bit line, 123 ... Embedded conductor, 220a, 220b ... Epitaxial silicon film, 221 ... Mask silicon oxide film, 222 ...
Epitaxial silicon film.

Claims (2)

(57) [Claims] 1. A step of forming a memory cell transistor by providing a gate electrode on one main surface of a semiconductor substrate via a gate insulating film and providing a pair of source / drain regions in a self-aligned manner with the gate electrode, The pair of sources, which are self-aligned with the gate electrode of the memory cell transistor,
Forming a contact hole in the insulating film on the drain region, and forming a capacitor electrode of the memory cell capacitor by selectively epitaxially growing silicon in the contact hole portion on one of the pair of source / drain regions. And covering the other of the pair of source / drain regions exposed in the contact hole portion with a silicon oxide film and then selectively epitaxially growing silicon to fill the contact hole on one of the pair of source / drain regions and to form the gate. A method of manufacturing a stacked memory cell, comprising forming the capacitor electrode extending above an electrode. 2. A step of forming a memory cell transistor by providing a gate electrode on a main surface of a semiconductor substrate via a gate insulating film and providing a pair of source / drain regions in a self-aligned manner with the gate electrode. The pair of sources, which are self-aligned with the gate electrode of the memory cell transistor,
Forming a contact hole in the insulating film on the drain region, and forming a capacitor electrode of the memory cell capacitor by selectively epitaxially growing silicon in the contact hole portion on one of the pair of source / drain regions. Each of the contact holes is filled to form a first epitaxial silicon film, the first epitaxial silicon film on the other of the pair of source / drain regions is covered with a silicon oxide film, and then the pair of sources is formed. The capacitance is formed by depositing a second epitaxial silicon film on the first epitaxial silicon film on one of the drain regions to fill the contact hole on one of the pair of source / drain regions and spread over the gate electrode. Manufacture of stacked memory cells characterized by forming electrodes Method.