KR100275114B1 - Semiconductor device having low bit line capacitance and method for forming the same - Google Patents

Semiconductor device having low bit line capacitance and method for forming the same Download PDF

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KR100275114B1
KR100275114B1 KR1019970077872A KR19970077872A KR100275114B1 KR 100275114 B1 KR100275114 B1 KR 100275114B1 KR 1019970077872 A KR1019970077872 A KR 1019970077872A KR 19970077872 A KR19970077872 A KR 19970077872A KR 100275114 B1 KR100275114 B1 KR 100275114B1
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bit line
silicon layer
junction
line contact
oxide film
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KR1019970077872A
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Korean (ko)
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KR19990057793A (en
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오민록
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto

Abstract

PURPOSE: A semiconductor device is provided to be capable of obtaining a low bit line junction capacitance, by using a high concentration impurity doping region facing a buried oxide film below a bit line contact junction. CONSTITUTION: The semiconductor device having a low bit line capacitance includes a silicon on insulator(SOI) substrate. The SOI substrate has the first silicon layer(101) acting as a support substrate and the second silicon layer(103) providing a buried oxide film(102) and an active region. A gate is formed on the second silicon layer. Source/drain junctions(106) is formed on the second silicon layer at the both sides of the gate. One of the source/drain functions as a bit line contact junction. A bit line(109) is connected to the bit line contact junction. A high concentration impurity doping region(108) is formed in the second silicon layer between the bit line contact junction and the buried oxide film. An upper portion of the high concentration impurity doping region faces the bit line contact junction and a lower portion of which faces the buried oxide film.

Description

낮은 비트라인 커패시턴스를 갖는 반도체소자 및 그 제조방법{Semiconductor device having low bit line capacitance and method for forming the same}Semiconductor device having low bit line capacitance and method for manufacturing the same

본 발명은 낮은 접합 커패시턴스를 갖는 반도체소자 및 그 제조방법에 관한 것으로, 특히 SOI(Silicon On Insulator) 기판을 사용한 반도체소자에서 비트라인(Bit Line)의 접합 커패시턴스(Junction Capacitance)를 감소시키기 위한 소자 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a low junction capacitance and a method of manufacturing the same, and more particularly to a device for reducing junction capacitance of a bit line in a semiconductor device using a silicon on insulator (SOI) substrate. The manufacturing method is related.

도 1은 실리콘 기판(Si-Substrate)상에 구현된 종래의 DRAM 셀 구조를 나타내는 단면도로서, 도면에 도시된 바와 같이, 종래의 DRAM은 소자분리절연막(2)이 형성된 실리콘 기판(1) 상에 게이트(3) 및 소스/드레인 접합(9)으로 이루어진 모스트랜지스터가 형성되고, 소스(또는 드레인) 접합에 비트라인(4)이 콘택되며, 그 상부로 드레인(또는 소스) 접합에는 스토리지노드(6), 유전막(7) 및 플레이트노드(8)로 이루어지는 커패시터가 형성된다. 그리고, 게이트(3), 비트라인(4) 및 커패시터를 각각 절연시키기 위하여 층간절연막(5)을 갖는다.1 is a cross-sectional view illustrating a conventional DRAM cell structure implemented on a silicon substrate (Si-Substrate). As shown in the drawing, the conventional DRAM is formed on a silicon substrate 1 on which a device isolation insulating film 2 is formed. A morph transistor consisting of a gate 3 and a source / drain junction 9 is formed, a bit line 4 is contacted to the source (or drain) junction, and a storage node 6 to the drain (or source) junction thereon. ), A capacitor consisting of a dielectric film 7 and a plate node 8 is formed. In addition, an interlayer insulating film 5 is provided to insulate the gate 3, the bit line 4, and the capacitor, respectively.

이와 같은 구조에서, 비트라인 커패시턴스는 주로 비트라인 콘택 접합 커패시턴스(Bit Line Contact Junction Capacitance), 비트라인(4)과 게이트(워드라인)(3)사이의 커패시턴스, 그리고 비트라인(4)과 플레이트노드(8)사이의 커패시턴스로 구성되게 되는데, 비트라인 커패시턴스에서 비트라인 콘택 접합 커패시턴스가 가장 큰 비중을 차지하고 있다.In such a structure, the bit line capacitance is mainly the bit line contact junction capacitance, the capacitance between the bit line 4 and the gate (word line) 3, and the bit line 4 and the plate node. It is composed of capacitance between (8), bit line contact junction capacitance is the largest proportion of the bit line capacitance.

한편, 소자의 동작 속도는 비트라인(4)의 저항 및 커패시턴스에 의해 크게 좌우되는데, 비트라인(4)의 저항을 낮추기 위해서는 비트라인을 폴리실리콘에서 폴리사이드(polycide)로 변화시켜 사용하는 등 여러 방법이 시도되고 있다.On the other hand, the operation speed of the device is largely dependent on the resistance and capacitance of the bit line 4, in order to lower the resistance of the bit line 4, the bit line is changed from polysilicon to polycide, and so on. The method is being tried.

그러나, 일반적인 실리콘 기판(1)에 만든 DRAM셀의 비트라인(4) 커패시턴스를 감소시키는 것이 어렵다.However, it is difficult to reduce the capacitance of the bit line 4 of a DRAM cell made in a general silicon substrate 1.

본 발명은 비트라인의 접합 커패시턴스를 크게 감소시켜 비트라인의 전기 전도도를 향상시킨 반도체소자 및 그 제조방법을 제공함을 그 목적으로 한다.SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which greatly reduce the junction capacitance of the bit line to improve the electrical conductivity of the bit line.

도 1은 실리콘 기판 상에 구현된 종래의 DRAM 셀 구조를 나타내는 단면도.1 is a cross-sectional view showing a conventional DRAM cell structure implemented on a silicon substrate.

도 2a 내지 도 2c는 본 발명의 일실시예에 따른 DRAM 제조 공정.2A-2C illustrate a DRAM manufacturing process in accordance with one embodiment of the present invention.

*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

101 : 제1실리콘층 102 : 매몰 산화막101: first silicon layer 102: buried oxide film

103 : 제2실리콘층 104 : 소자분리절연막103: second silicon layer 104: device isolation insulating film

105 : 게이트전극 106 : 소스/드레인 접합105: gate electrode 106: source / drain junction

107 : 층간절연막 108 : 고농도 불순물 도핑 영역107: interlayer insulating film 108: high concentration impurity doping region

109 : 비트라인109 bitline

상기 목적을 달성하기 위한 본 발명은 지지 기판 역할을 하는 제1실리콘층, 매몰 산화막 및 활성영역을 제공하는 제2실리콘층을 갖는 SOI 기판; 상기 제2실리콘층 상에 형성된 게이트; 상기 게이트 양단의 상기 제2실리콘층에 형성되며 그 중 어느 하나가 비트라인 콘택접합으로서 역할하는 소스/드레인; 상기 비트라인 콘택접합에 연결된 비트라인; 상기 비트라인 콘택 접합 및 상기 매몰 산화막 사이의 상기 제2실리콘층에 형성되며, 그 상부가 상기 비트라인 콘택접합과 맞닿고 그 하부가 상기 매몰산화막과 맞닿는 고농도 불순물 도핑영역을 포함하는 반도체소자를 제공한다.The present invention for achieving the above object is an SOI substrate having a first silicon layer serving as a support substrate, a buried oxide film and a second silicon layer providing an active region; A gate formed on the second silicon layer; A source / drain formed on the second silicon layer across the gate, any one of which serves as a bit line contact junction; A bit line coupled to the bit line contact junction; A semiconductor device is formed on the second silicon layer between the bit line contact junction and the buried oxide layer, the semiconductor device including a high concentration impurity doping region in which an upper portion thereof contacts the bit line contact junction and a lower portion thereof contacts the investment oxide layer. do.

또한 상기 목적을 달성하기 위한 본 발명은 지지 기판 역할을 하는 제1실리콘층, 매몰 산화막 및 활성영역을 제공하는 제2실리콘층으로 이루어진 SOI 기판을 준비하는 단계; 상기 제2실리콘층 상에 게이트전극을 형성하고 상기 게이트전극을 마스크로하여 상기 제2실리콘층 내에 불순물을 이온주입함으로써, 상기 매몰 산화막과 떨어진 소스/드레인 접합을 형성하는 단계; 전체 구조 상부에 층간절연막을 형성하고 상기 층간절연막을 선택적으로 식각하여 상기 소스 또는 드레인 중 비트라인 콘택 접합을 노출시키는 단계; 고농도 불순물을 전면 이온주입하여 상기 노출된 비트라인 콘택 접합 아래에, 그 상부가 상기 비트라인 콘택 접합과 맞닿으며 그 하부가 상기 매몰산화막과 맞닿는 고농도 불순물 도핑 영역을 형성하는 단계; 및 상기 비트라인 콘택 접합과 연결되는 비트라인을 형성하는 단계를 포함하는 반도체소자 제조방법을 제공한다.In addition, the present invention for achieving the above object comprises the steps of preparing a SOI substrate consisting of a first silicon layer serving as a support substrate, a buried oxide film and a second silicon layer providing an active region; Forming a gate electrode on the second silicon layer and implanting impurities into the second silicon layer using the gate electrode as a mask to form a source / drain junction separated from the buried oxide film; Forming an interlayer dielectric layer over the entire structure and selectively etching the interlayer dielectric layer to expose a bit line contact junction of the source or drain; Implanting a high concentration impurity into the entire surface to form a high concentration impurity doped region under the exposed bit line contact junction, the upper part of which is in contact with the bit line contact junction and the lower part of which is in contact with the investment oxide film; And forming a bit line connected to the bit line contact junction.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조로 하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. Shall be.

도 2b는 본 발명의 특징적인 구조를 나타내는 DRAM의 일부 단면도로서, 도 2b를 참조하면, 본 발명의 일실시예에 따른 DRAM은 지지 기판 역할을 하는 제1실리콘층(101), 매몰 산화막(102) 및 활성영역을 제공하는 제2실리콘층(103)으로 이루어진 SOI 기판 상에 소자가 형성된다. 제2실리콘층(103)의 활성 영역내에는 매몰산화막(102)과 떨어져 형성된 트랜지스터의 소스/드레인 접합(106)이 형성되며, 비트라인(109)이 콘택되는 소스(또는 드레인) 접합(106)과 매몰산화막(102) 사이에는 비트라인의 접합 커패시턴스를 감소시키기 위한 고농도 불순물 도핑영역(108)이 선택적으로 형성되어 있다. 이 고농도 불순물 도핑영역(108)은 비트라인의 접합 커패시턴스를 감소시키게 되는데, 이는 접합 영역(Junction Area)이 매몰산화막(102)과 만나는 아래 부분은 접합 커패시턴스에서 제외되므로 접촉면적이 줄어드는 효과를 가져오기 때문이다. 그리고, 상기 소스/드레인 접합과 상기 고농도 불순물 도핑영역은 동일한 도전형의 N 또는 P형 불순물 갖는다. 미설명 도면부호는 이후의 제조 공정에서 설명될 것이다.FIG. 2B is a partial cross-sectional view of a DRAM showing a characteristic structure of the present invention. Referring to FIG. 2B, a DRAM according to an embodiment of the present invention may include a first silicon layer 101 and an buried oxide film 102 serving as a supporting substrate. And an element is formed on the SOI substrate consisting of the second silicon layer 103 providing the active region. A source / drain junction 106 of a transistor formed apart from the buried oxide film 102 is formed in the active region of the second silicon layer 103, and a source (or drain) junction 106 to which the bit line 109 is contacted is formed. A high concentration impurity doped region 108 is selectively formed between the buried oxide film 102 and the junction capacitance of the bit line. The highly doped impurity doped region 108 reduces the junction capacitance of the bit line. The lower portion where the junction region meets the buried oxide film 102 is excluded from the junction capacitance, thereby reducing the contact area. Because. The source / drain junction and the highly doped impurity doped region have N or P type impurities of the same conductivity type. Unexplained reference numerals will be described later in the manufacturing process.

도 2a 내지 도 2c는 본 발명의 일실시예에 따른 DRAM 제조 공정도로서, 도 2a를 참조하면, 먼저 지지 기판 역할을 하는 제1실리콘층(101), 매몰 산화막(102), 및 활성영역을 제공하는 제2실리콘층(103)으로 이루어진 SOI 기판 상에 소자분리절연막(104)을 형성하는데, 소자분리절연막(104)은 매몰산화막(102)과 닿지 않도록 형성한다. 이어서, 게이트전극(워드라인)(105)을 형성하고 소스/드레인 접합(106)을 형성한다. 이때 소스/드레인 접합(106) 역시 매몰 산화막(102)과 닿지 않도록 한다.2A to 2C are diagrams illustrating a DRAM manufacturing process according to an embodiment of the present invention. Referring to FIG. 2A, first, a first silicon layer 101, an investment oxide film 102, and an active region serving as a supporting substrate are provided. The device isolation insulating film 104 is formed on the SOI substrate made of the second silicon layer 103, and the device isolation insulating film 104 is formed so as not to contact the buried oxide film 102. Subsequently, a gate electrode (word line) 105 is formed and a source / drain junction 106 is formed. In this case, the source / drain junction 106 may also not contact the buried oxide layer 102.

이어서, 도 2b를 참조하면, 게이트전극(105)과 이후에 형성될 비트라인을 격리시키기 위해서 층간절연막(107)을 형성하고, 비트라인 콘택홀을 형성한 다음 마스크 없이 높은 도즈(Dose)와 높은 에너지(Energy)의 고농도 불순물 이온을 주입하여 기형성된 비트라인 콘택홀 하부의 소스(또는 드레인) 접합(106) 아래에 그리고 매몰산화막(102)과 만나도록 불순물 도핑 영역(108)을 형성한다. 그리고, 비트라인(109)을 콘택시킨다.Subsequently, referring to FIG. 2B, an interlayer insulating film 107 is formed to isolate the gate electrode 105 from the bit line to be formed later, the bit line contact hole is formed, and then a high dose and a high mask without a mask are formed. A high concentration of impurity ions are implanted to form the impurity doped region 108 under the source (or drain) junction 106 under the pre-formed bitline contact hole and to meet the buried oxide film 102. Then, the bit line 109 is contacted.

이로써, 비트라인의 접합 커패시턴스는 감소되는데, 이는 접합 영역(Junction Area)이 매몰산화막과 만나는 아래 부분은 접합 커패시턴스에서 제외되므로 접촉면적이 줄어드는 효과를 가져오기 때문이다.As a result, the junction capacitance of the bit line is reduced because the lower portion where the junction area meets the buried oxide film is excluded from the junction capacitance, resulting in an effect of reducing the contact area.

이어서, 도 2c는 다시 층간절연막(110)을 형성하고, 스토리지노드(111), 유전막(112), 및 플레이트노드(113)로 구성된 셀 커패시터(capacitor)를 형성한 상태를 나타낸다.Next, FIG. 2C illustrates a state in which an interlayer insulating layer 110 is formed again, and a cell capacitor including the storage node 111, the dielectric layer 112, and the plate node 113 is formed.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

본 발명은 비트라인 콘택 접합(소스 또는 드레인) 아래에 매몰산화막과 맞닿는 고농도 불순물 도핑영역을 더 포함하여, 종래의 비트라인 접합 커패시턴스보다 낮은 비트라인 접합 커패시턴스를 얻을 수 있으므로 소자의 동작 속도를 증가시키는 이점이 있다.The present invention further includes a highly doped impurity doped region under the bit line contact junction (source or drain), which contacts the buried oxide layer, so that a bit line junction capacitance lower than that of the conventional bit line junction capacitance can be obtained, thereby increasing the operation speed of the device. There is an advantage.

Claims (4)

지지 기판 역할을 하는 제1실리콘층, 매몰 산화막 및 활성영역을 제공하는 제2실리콘층을 갖는 SOI 기판;An SOI substrate having a first silicon layer serving as a support substrate, a buried oxide film and a second silicon layer providing an active region; 상기 제2실리콘층 상에 형성된 게이트;A gate formed on the second silicon layer; 상기 게이트 양단의 상기 제2실리콘층에 형성되며 그 중 어느 하나가 비트라인 콘택접합으로서 역할하는 소스/드레인;A source / drain formed on the second silicon layer across the gate, any one of which serves as a bit line contact junction; 상기 비트라인 콘택접합에 연결된 비트라인;A bit line coupled to the bit line contact junction; 상기 비트라인 콘택 접합 및 상기 매몰 산화막 사이의 상기 제2실리콘층에 형성되며, 그 상부가 상기 비트라인 콘택접합과 맞닿고 그 하부가 상기 매몰산화막과 맞닿는 고농도 불순물 도핑영역A highly doped impurity doped region formed in the second silicon layer between the bit line contact junction and the buried oxide layer, the upper portion of which is in contact with the bit line contact junction and the lower portion of which is in contact with the investment oxide. 을 포함하는 반도체소자.Semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 소스/드레인 접합과 상기 고농도 불순물 도핑영역은 동일한 도전형인 것을 특징으로 하는 반도체소자.And the source / drain junction and the highly doped impurity doped region are of the same conductivity type. 지지 기판 역할을 하는 제1실리콘층, 매몰 산화막 및 활성영역을 제공하는 제2실리콘층으로 이루어진 SOI 기판을 준비하는 단계;Preparing an SOI substrate comprising a first silicon layer serving as a support substrate, an buried oxide film, and a second silicon layer providing an active region; 상기 제2실리콘층 상에 게이트전극을 형성하고 상기 게이트전극을 마스크로하여 상기 제2실리콘층 내에 불순물을 이온주입함으로써, 상기 매몰 산화막과 떨어진 소스/드레인 접합을 형성하는 단계;Forming a gate electrode on the second silicon layer and implanting impurities into the second silicon layer using the gate electrode as a mask to form a source / drain junction separated from the buried oxide film; 전체 구조 상부에 층간절연막을 형성하고 상기 층간절연막을 선택적으로 식각하여 상기 소스 또는 드레인 중 비트라인 콘택 접합을 노출시키는 단계;Forming an interlayer dielectric layer over the entire structure and selectively etching the interlayer dielectric layer to expose a bit line contact junction of the source or drain; 고농도 불순물을 전면 이온주입하여 상기 노출된 비트라인 콘택 접합 아래에, 그 상부가 상기 비트라인 콘택 접합과 맞닿으며 그 하부가 상기 매몰산화막과 맞닿는 고농도 불순물 도핑 영역을 형성하는 단계; 및Implanting a high concentration impurity into the entire surface to form a high concentration impurity doped region under the exposed bit line contact junction, the upper part of which is in contact with the bit line contact junction and the lower part of which is in contact with the investment oxide film; And 상기 비트라인 콘택 접합과 연결되는 비트라인을 형성하는 단계Forming a bit line connected to the bit line contact junction 를 포함하는 반도체소자 제조방법.Semiconductor device manufacturing method comprising a. 제 3 항에 있어서,The method of claim 3, wherein 상기 소스/드레인 접합과 상기 고농도 불순물 도핑영역은 동일한 도전형으로 형성하는 것을 특징으로 하는 반도체 소자 제조방법.And the source / drain junction and the highly doped impurity doped region are formed of the same conductivity type.
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JPH02143456A (en) * 1988-11-24 1990-06-01 Nec Corp Manufacture of lamination type memory cell
JPH0462869A (en) * 1990-06-25 1992-02-27 Mitsubishi Electric Corp Semiconductor device
JPH0794686A (en) * 1993-06-30 1995-04-07 Nippon Steel Corp Nonvolatile semiconductor device and fabrication thereof

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JPS616858A (en) * 1984-06-20 1986-01-13 Matsushita Electric Ind Co Ltd Semiconductor memory storage and manufacture thereof
JPH02143456A (en) * 1988-11-24 1990-06-01 Nec Corp Manufacture of lamination type memory cell
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