KR100273678B1 - Memory device and method for fabricating the same - Google Patents

Abstract

PURPOSE: A semiconductor memory device and a method for manufacturing the same are provided to prevent a short-circuit between a word line and a bit line by forming a buried bit line. CONSTITUTION: An isolation layer is locally on a semiconductor substrate(101). A bit line(102) is buried an inside of the semiconductor substrate(101) near to an edge of the isolation layer. The bit line(102) is formed by inserting the first insulating layer(103) into the semiconductor substrate(101). An epitaxial layer(104) is formed on a surface of the semiconductor substrate(101) and a surface of the bit line(102). A word line(106) is formed on a predetermined portion of the epitaxial layer(104). A source/drain junction(105a,105b) is formed by injecting a dopant to the epitaxial layer(104). The first storage node(107) is formed by isolating the third insulating layer(108) with the word line(106).

Description

Semiconductor memory device and method for manufacturing the same {Memory device and method for fabricating the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a memory device having a buried bitline and a method of manufacturing the same.

With the development of semiconductor technology, as the degree of integration of memory devices increases, short circuits between word lines and bit lines, and gaps between cell regions and peripheral circuit regions in DRAMs become a problem.

Typically, a DRAM has a bit line contact and a storage node contact of a capacitor formed next to a word line, and a short circuit with a word line occurs due to misalignment of a mask when forming a contact of a bit line or a storage node. This is getting worse as semiconductor devices become more integrated.

In addition, bit lines and capacitors are formed in the cell region of the substrate, whereas bit lines or capacitors are not formed in the peripheral circuit, so that a step is deepened and thus a desired pattern can be formed well due to a lack of mask process margin. There is a problem that cannot be, which is also deepening as the semiconductor memory device becomes more integrated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device and a method for manufacturing the same, which reduce the step and prevent the short circuit between the word line and the bit line in response to high integration with a finer design rule.

It is another object of the present invention to provide a semiconductor memory device suitable for connecting a buried bit line or / and a strip node and a junction of a transistor with an epitaxial silicon layer to simplify the process, and a method of manufacturing the same.

1 is a cross-sectional view of a DRAM cell in accordance with one embodiment of the present invention.

2 is a cross-sectional view of a DRAM cell according to another embodiment of the present invention.

3A-3H illustrate a DRAM cell manufacturing process in accordance with one embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

101: silicon substrate 102: buried bit line

103 and 108 insulating film 104 epitaxial silicon layer

105a, 105b: Junction of transistor 106: Gate (word line) of transistor

107: buried first storage node 109: second storage node

In order to achieve the above object, a semiconductor memory device of the present invention, a semiconductor substrate; A bit line embedded therein from the surface of the semiconductor substrate; An epitaxial layer formed on the bit line surface and the semiconductor substrate surface to provide an active region; A word line formed on a predetermined portion of the epitaxial layer; Source / drain junctions of transistors formed by implanting impurities into the epitaxial layer in regions not covered by the word lines and having one side connected to the buried bit lines; And a first storage node connected to the other side of the source / drain junction and formed thereon.

In addition, the semiconductor device of the present invention further includes a second storage node connected to the other side of the source / drain junction and embedded in the semiconductor substrate below.

In another aspect, a method of manufacturing a semiconductor memory device may include forming a trench by selectively etching a semiconductor substrate at a bit line forming portion to a predetermined depth; Forming an insulating film along a surface of the semiconductor substrate on which the trench is formed; Filling a bitline conductive layer in the trench; Forming an epitaxial layer on the bit line conductive layer and the semiconductor substrate surface; And forming a transistor having the epitaxial layer as an active region and having a junction thereof connected to the bit line conductive layer.

In the method of manufacturing a semiconductor memory device of the present invention, the forming of the transistor may include: stacking and patterning a gate insulating layer and a gate conductive layer on the epitaxial layer in a portion that does not overlap with the bit line conductive layer; And ion implanting impurities into the epitaxial layer to form a source / drain junction, whereby the bit line conductive layer and one side of the source / drain junction are connected.

In another aspect, a method of fabricating a semiconductor memory device may include forming a trench by selectively etching a semiconductor substrate at a bit line forming portion and a storage node portion by a predetermined depth; Forming an insulating film along a surface of the semiconductor substrate on which the trench is formed; Forming a bit line and a first storage node by filling a first conductive film in the trench; Forming an epitaxial layer on the bit line, the storage node, and the semiconductor substrate surface; Forming a transistor having the epitaxial layer as an active region, one junction of which is connected to the bit line, and the other junction of which is connected to the first storage node; And forming an interlayer dielectric layer having the other side junction of the transistor open. And filling the open portion with a second conductive layer to form a second storage node.

In another method of manufacturing a semiconductor memory device of the present invention, the step of forming a transistor includes: stacking and patterning a gate insulating layer and a gate conductive layer on the epitaxial layer in a portion not overlapping the bit line; And implanting impurities into the epitaxial layer to form source / drain junctions respectively connected to the bit line and the first storage node.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

1 is a cross-sectional view of a DRAM cell according to an exemplary embodiment of the present invention. As shown in the drawing, the bit line 102 is embedded in the silicon substrate 101 at a portion close to the edge of the device isolation film FOX. The interface between the buried bit line 102 and the silicon substrate 101 is insulated by an insulating film 103 for electrical separation. An epitaxially grown silicon layer 104 is formed on the buried bit line 102 surface and the silicon substrate 101, and the junctions 105a and 105b of the transistors implanted with impurities are formed in the epitaxial silicon layer 104. do. One side of the junction 105a is connected to the bit line 102 embedded in the silicon substrate 101, and although not shown in the figure, the storage node of the capacitor is connected to the other junction 105b while the silicon layer 104 is connected. It will be formed on the top. A gate (wordline) 106 of the transistor is formed on the silicon layer 104 at the portion that does not overlap the buried bitline 102 and the storage node.

2 is a cross-sectional view of a DRAM cell according to another embodiment of the present invention, in which a structure having parallel storage nodes is shown.

Referring to FIG. 2, the bit line 102 is embedded in the silicon substrate 101, and the embedded bit line 102 is insulated from the silicon substrate 101 by an insulating film 103 for electrical separation. It is. An epitaxially grown silicon layer 104 is formed on the buried bit line 102 surface and the silicon substrate 101, and the junctions 105a and 105b of the transistors implanted with impurities are formed in the epitaxial silicon layer 104. do. One side of the junction 105a is connected to the bit line 102 embedded in the silicon substrate 101, and the first storage node 107 is embedded in the silicon substrate 101 while being connected to the other junction 105b. The second storage node 109 is also formed on the silicon layer 104 while being connected to the other junction 105b. An insulating film 108 for electrical separation is formed at an interface between the first storage node 107 embedded in the silicon substrate 101 and the silicon substrate 101. A gate (wordline) 106 of the transistor is formed on the silicon layer 104 at the portion that does not overlap the buried bitline 102 and the storage node.

As described above, the present invention is to form the storage node of the bit line and / or capacitor under the surface of the silicon substrate, the junction of the transistor and the connection between them is made by the epitaxial silicon layer, the word line (transistor Short-circuit between the gate wiring) and the bit line is prevented, and the storage node of the bit line and / or capacitor is embedded in the silicon substrate in the cell region, thereby alleviating the step with the peripheral circuit region.

3A to 3H are diagrams illustrating a process of fabricating a DRAM cell according to an embodiment of the present invention.

First, as shown in FIG. 3A, a mask pattern 2 having an open bit line forming portion is formed on the silicon substrate 1, and as shown in FIG. 3B, the exposed silicon substrate 1 is etched to a predetermined depth to form a bit line. To form a trench 3.

Subsequently, as shown in FIG. 3C, after removing the mask pattern 2, a thermal oxide film 4 for insulation is grown along the trench-formed silicon substrate 1 surface, and the front surface is sufficiently filled with the trench 3. A polysilicon film 5 for the bit line is formed.

Subsequently, as shown in FIG. 3D, chemical mechanical polishing is performed until the surface of the silicon substrate is exposed. As a result, a thermal oxide film 4 is formed on the inner surface of the trench, and the inside of the trench is filled by the polysilicon film 5.

Subsequently, as shown in FIG. 3E, the field oxide film 6 for device isolation is formed, and as shown in FIG. 3F, the epitaxial silicon layer 7 is formed for the flow of current between electrodes. As described above in detail, the epitaxial silicon layer 7 is for connection between the source / drain junction layer and the bit line of the transistor.

Subsequently, as shown in FIG. 3G, a transistor is formed in the epitaxial silicon layer 7 in a normal process. That is, the gate oxide film 8, the gate silicon polysilicon film 9, and the oxide film 10 for the hard mask are sequentially formed in the epitaxial silicon layer 7, and the stacked thin films 8, 9, and 10 are formed. After the patterning is performed by a word line mask and an etching process, a spacer insulating layer 11 is formed on sidewalls of the patterned thin films, and then a source / drain junction 12 is formed by ion implantation.

FIG. 3H illustrates a state in which the interlayer insulating layer 13 is formed on the entire surface of FIG. 3G, and then the storage node contact hole 14 of the capacitor is formed.

In the present embodiment, when the bit line trench is formed in FIG. 3B, the storage node is also formed in the trench to form the first storage node, and then the transistor is formed, and then the storage node is formed. Memory cells can be formed.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, a storage node of a bit line and / or a capacitor is formed under a surface of a silicon substrate, and a transistor and a connection therebetween are formed by an epitaxial silicon layer, and a word line (gate wiring of a transistor) and a bit line It is effective in preventing short circuits and shortening the gap between the cell region and the peripheral circuit region, thereby greatly improving the process margin of the highly integrated device.

Claims (7)

In a semiconductor memory device, Semiconductor substrates; An isolation layer formed locally on the semiconductor substrate; A bit line embedded in the semiconductor substrate proximate the edge of the device isolation layer and formed through a first insulating layer between the semiconductor substrate; An epitaxial layer formed on the bit line surface and the semiconductor substrate surface; A word line formed on a predetermined portion of the epitaxial layer; Source and drain junctions of transistors defined by injecting impurities into the epitaxial layer in regions not covered by the word lines, and one of which is connected to the buried bit line; And A first storage node that is connected to the other of the source and drain junctions and is formed to be extended to an upper portion thereof and is insulated from the word line by a third insulating layer; A semiconductor memory device comprising a. The method of claim 1, And a second storage node connected to the other of the source and drain junctions, the second storage node being embedded in the lower portion of the semiconductor substrate and interposed with the semiconductor substrate via a second insulating layer. . In the semiconductor memory device manufacturing method of claim 1, Selectively etching the semiconductor substrate at the bit line forming region to a predetermined depth to form a trench; Forming an insulating film along a surface of the semiconductor substrate on which the trench is formed; Filling a bitline conductive layer in the trench; Forming an isolation layer on the semiconductor substrate such that its edge is aligned with the bit line conductive layer; Growing an epitaxial layer on the bit line conductive layer and the semiconductor substrate surface; And Forming a transistor having the epitaxial layer as an active region and a junction thereof connected to the bit line conductive layer A semiconductor memory device manufacturing method comprising a. The method of claim 3, Forming the transistor, Stacking and patterning a gate insulating layer and a gate conductive layer on the epitaxial layer in a portion which does not overlap with the bit line conductive layer; And Implanting impurities into the epitaxial layer to form a source / drain junction, whereby the bit line conductive layer and one side of the source / drain junction are connected. In the semiconductor memory device manufacturing method of claim 2, Selectively etching the semiconductor substrates of the bit line forming portion and the storage node portion to a predetermined depth to form a trench; Forming an insulating film along a surface of the semiconductor substrate on which the trench is formed; Forming a bit line and a first storage node by filling a first conductive film in the trench; Forming an isolation layer on the semiconductor substrate such that its edge is aligned with the bit line conductive layer; Growing an epitaxial layer on surfaces of the bit line, the first storage node, and the semiconductor substrate; Forming a transistor having the epitaxial layer as an active region, one junction of which is connected to the bit line, and the other junction of which is connected to the first storage node; And Forming an interlayer dielectric layer with the other junction of the transistor open; Depositing a second conductive film to form a second storage node in contact with the other junction of the transistor A semiconductor memory device manufacturing method comprising a. The method of claim 5, Forming the transistor, Stacking and patterning a gate insulating layer and a gate conductive layer on the epitaxial layer in a portion not overlapping with the bit line; And Implanting impurities into the epitaxial layer to form a source / drain junction respectively connected to the bit line and the first storage node. The method of claim 5, And the first and second conductive films are polysilicon films.

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