KR100272655B1 - Semiconductor memory device and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor memory device is provided to improve the step coverage between a cell region and a peripheral region, by forming a semiconductor dynamic random access memory(DRAM) device on a silicon-on-insulator(SOI) substrate, and by forming a storage node capacitor between a device layer and a buried insulating layer. CONSTITUTION: A buried insulating layer(11) is formed on a silicon wafer(10) for handling. A conductive layer(12) is formed on the buried insulating layer. A plate electrode(14) in which a pair of spacers have a symmetrical structure is formed in a predetermined portion on the conductive layer. A dielectric layer(15) is formed on the plate electrode and the conductive layer. A storage node electrode(16) is formed on the dielectric layer. A planarization layer(17) is formed to sufficiently bury the storage node electrode. The first hole is to expose a predetermined portion of the storage node electrode. A connection node(18) is formed on the planarization layer including the first hole to be in contact with the exposed storage node electrode. A device layer(19) is formed on the entire structure. A gate electrode(21) is formed in a predetermined portion of the device layer. A source/drain region(22,23) is formed in the device layer at both sides of the gate electrode, wherein the source region is in contact with the connection node.

Description

Semiconductor memory device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a DRAM device having a capacitor formed in a silicon on insulator (SOI) substrate and a method of manufacturing the same.

Among semiconductor memory devices, a DRAM is known as a memory capable of inputting arbitrary information or outputting already stored information, and a general DRAM inputs an external signal and a portion of a memory cell array in which a large amount of information as a storage area is stored. Or a peripheral circuit portion for outputting.

In the DRAM device, as shown in FIG. 1, a field oxide film 2 is formed on a semiconductor substrate 1 in which a cell region C and a peripheral region P are separated by a known method. Subsequently, a gate electrode 3 is formed on the semiconductor substrate 1, and source and drain regions 4A and 4B are formed on both sides of the gate electrode 3 to form a transistor.

Subsequently, a first interlayer insulating film 5 is formed on the semiconductor substrate 1 on which the transistor is formed, and the first interlayer insulating film 5 is etched a predetermined portion to expose the drain region 4B, thereby forming a bit line contact hole (not shown). Not formed) is formed. Then, the bit line 6 is formed to contact the exposed drain region 4B. A second interlayer insulating film 7 is formed on the semiconductor substrate 1 on which the bit lines 6 are formed to have a predetermined thickness, and is etched so that only the source region 4A of the cell region is exposed, thereby forming a storage node contact hole (not shown). ) Is formed. Subsequently, the storage capacitor 8 is formed to contact the exposed source region 4A through the storage node contact hole. Here, the storage capacitor 8 includes a storage electrode 8A contacting the source region 4A, a dielectric film 8B covering the surface of the storage electrode 8A, and a plate electrode 8C formed on the dielectric film 8B. )

In this case, the transistors 4, 4A, and 4B and the bit line 6 are formed simultaneously with the cell region C in the peripheral region P, and the storage electrode 8 is not formed.

However, the conventional DRAM device has the following problems.

First, as the storage capacitor 8 that determines the capacity of the DRAM device is formed only in the cell region C, a severe step is generated between the cell region C and the peripheral region P. FIG.

In addition, since the surface area of the storage capacitor 8 is proportional to the capacity of the DRAM, efforts have been made to increase it. As a result, the height of the storage capacitor is continuously increased, so that a step with the peripheral area P is greatly generated.

In this way, if the surface step becomes severe, it becomes difficult to design the pattern in a desired shape when forming the metal wiring to be advanced later.

In addition, in order to form a highly integrated DRAM device, the diameter of the bit line contact hole and the storage node contact hole must be minute. In this way, over etching of the interlayer insulating film for forming fine contact holes must be accompanied.

However, in such an over-etching process, part of the source and drain regions are removed to increase the leakage current of the DRAM element.

Accordingly, an object of the present invention is to provide a semiconductor memory device capable of eliminating a step between a cell region and a peripheral region in a DRAM device.

Another object of the present invention is to provide a semiconductor memory device with less generation of junction leakage current in the semiconductor memory device.

Still another object of the present invention is to provide a method of manufacturing a semiconductor memory device as described above.

1 is a cross-sectional view showing a conventional semiconductor DRAM device.

2 is a cross-sectional view showing a DRAM device formed on an S.O.I substrate according to the present invention.

3 (a) to 3 (i) are cross-sectional views for explaining a method for manufacturing a DRAM device on an S.O.I substrate of the present invention.

* Explanation of symbols for main parts of the drawings

10 silicon wafer for handling 11 buried insulating film

12 conductive layer 14 plate electrode

15 dielectric film 16 storage node electrode

17 planarization film 18 connection node

19 device layer 20 gate insulating film

21 gate electrode 22 source region

23 drain region 24 interlayer insulating film

25: auxiliary electrode

In order to achieve the above object of the present invention, the present invention is a silicon wafer for handling; A buried insulating layer formed on the silicon wafer; A conductive layer formed on the buried insulating layer; A storage capacitor formed on the conductive layer; A planarization layer formed on the conductive layer including the storage capacitor and having a first hole for exposing the storage capacitor; A connection node formed on the planarization film including the first hole; A device layer formed on the planarization film; A gate electrode formed on a predetermined portion of the device layer; A source electrode and a drain region formed on device layers on both sides of the gate electrode, wherein the storage capacitor includes a plate electrode in contact with the conductive layer and having a pair of spacers symmetrical with each other, and the plate electrode and the conductive layer. A semiconductor memory device comprising a dielectric film to cover and a storage electrode formed on the dielectric film and in contact with the source region through the connection node.

In addition, the present invention comprises the steps of forming a buried insulating film on the silicon wafer for handling; Forming a conductive layer on the buried insulating film; Forming a plate electrode having a structure in which a pair of spacers are symmetrical on a predetermined portion of the conductive layer; Forming a dielectric film on the plate electrode and the conductive layer; Forming a storage node electrode on the dielectric layer; Forming a planarization layer to sufficiently fill the storage node electrode; Forming a first hole to expose a predetermined portion of the storage node electrode; Forming a connection node on the planarization layer including the first hole to be in contact with the exposed storage node electrode; Forming a device layer over the entire structure; Forming a gate electrode on a predetermined portion of the device layer; A source and a drain region are formed in both device layers of the gate electrode, and the source region is formed to be in contact with the connection node.

According to the present invention, the storage capacitor of the semiconductor DRAM device is formed in the SOI substrate, thereby reducing the step between the cell region and the peripheral region at the top of the substrate.

In addition, since the contact hole forming process for exposing the source and drain regions is excluded, the junction leakage current due to the etching of the source and drain regions is not generated.

EXAMPLE

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a cross-sectional view illustrating a DRAM device according to the present invention, and FIGS. 3 (a) to 3 (i) illustrate a method of manufacturing a DRAM device in an SOI substrate according to the present invention.

In the present invention, a DRAM device is formed on an SOI substrate having perfect punch isolation and excellent punch-through characteristics. In addition, a storage capacitor of the DRAM device is formed in the SOI substrate to reduce the step difference between the cell region and the peripheral region.

First, referring to FIG. 2, a configuration of a DRAM device according to the present invention will be described.

Referring to the drawings, the buried insulating layer 11 is formed on the handling silicon wafer 10, and the conductive layer 12 is formed on the buried insulating layer 11. At this time, the conductive layer 12 is a polysilicon film doped with P (phosphorus) atoms.

The planarization film 17 is formed on this conductive layer 12, and the device layer 19 formed on the planarization film 17 is formed. At this time, the planarization film 17 is preferably formed of a BPSG film, and the device layer is a polysilicon film doped with a P-type impurity.

The gate electrode 21 is formed in a predetermined portion above the device layer 19, and the N type source and drain regions 22 and 23 are formed in the device layer 19 on both sides of the gate electrode 21.

At this time, the plate electrode 14 in the form of a spacer contacting the conductive layer 12 in the planarization film 17, the dielectric film 15 and the dielectric film 15 covering the plate electrode 14 and the conductive layer 12. A storage node capacitor is formed to cover a predetermined portion of the (), and includes a storage node electrode 16 contacted through the source region 22 and the connection node 18.

An interlayer insulating film 24 is formed on the device layer 19, and the auxiliary electrode 25 for improving the capacitance of the capacitor is conducted through the interlayer insulating film 24, the device layer 19, and the planarization film 17. Contact with layer 12. In this case, the auxiliary electrode 25 is electrically insulated from the device layer 19.

Hereinafter, the manufacturing method of the present invention will be described in detail.

Referring to FIG. 3 (a), the buried insulating layer 11 is formed on the silicon wafer 10 for handling by a known oxide film deposition method, and the conductive layer is formed on the buried insulating layer 11. 12) is deposited to a predetermined thickness. At this time, the conductive layer 12 is a polysilicon film doped with P (phosphorus) atoms or a film in which impurities are ion-implanted into the polysilicon film. Thereafter, since a P ₂ O ₅ film or a P ₂ O ₅ -silicon glass material may be formed on the surface of the conductive layer 12, a deglaze process is performed.

Then, as shown in FIG. 3 (b), a PSG (phosphorus silica glass) film 13 is deposited on the conductive layer 12 and flows at a predetermined temperature. Thereafter, the PSG film 13 is patterned to expose a predetermined portion of the conductive layer 12, and then a polysilicon film coated with impurities is deposited on the resultant. Subsequently, the doped polysilicon film is blanket etched until the surface of the patterned PSG film 13 is exposed, so that both sides of the patterned PSG film 13 are formed with spacers 14. Here, the spacer 14 is the plate electrode of the storage capacitor together with the conductive layer 12 in the DRAM of the present invention.

Then, as shown in FIG. 3 (c), the PSG film 13 is removed by anisotropic blanket etching or wet etching, leaving only spacers 14 on the conductive layer 12.

Then, as shown in FIG. 3 (d), on the surfaces of the conductive layer 12 and the spacer 14, a dielectric film 15, for example, an ONO (oxide-nitride-oxide) film and a BaTiO ₃ dielectric film Is covered. Subsequently, a doped polysilicon layer is deposited on the dielectric layer 15 and patterned to form a storage node electrode 16. Accordingly, a capacitor including the plate electrode 14, the dielectric layer 15, and the storage node electrode 16 is formed on the buried insulating layer 11.

Referring to FIG. 3 (e), the planarization film 17, for example, BPSG (boro-phosphorus silicate glass) is deposited on the conductive layer 12 on which the storage capacitor is formed to a predetermined thickness, and then heat-treated at a predetermined temperature. And flow to have a flat surface. At this time, instead of the flow process by heat treatment, the storage capacitor is deposited to be sufficiently buried, and then by chemical mechanical polishing process, the resultant to have a flat surface. Next, the planarization layer 17 is etched to expose a predetermined portion of the storage node electrode 16 of the storage capacitor so that the first hole H1 is formed.

Then, as shown in FIG. 3 (f), a polysilicon film doped to contact the exposed storage node electrode 16 is deposited and patterned so as to exist only in the upper portion of the storage capacitor so that the connection node 18 is formed. Is formed. Here, the connection node 18 is a connection path connecting the storage node electrode 16 and the junction region of the MOS transistor to be formed later. Thereafter, a device layer 19 on which the MOS transistor is to be formed, for example, a polysilicon film doped with impurities, is formed on the planarization film 17.

Subsequently, as shown in FIG. 3 (g), a mask pattern (not shown) is formed so that only the device layer 19 on the connection node 18 is covered, and the P type is exposed on the exposed device layer 19. For example, boron ions are ion implanted. At this time, the P type impurity is injected into the device layer 19 to form an N MOS transistor in the device layer 19. Then, the mask pattern is removed in a known manner, and a gate oxide film 20 is formed on the surface of the semiconductor layer 19 by a known thermal oxidation method. Thereafter, a doped polysilicon film is deposited on the gate oxide film 20, and then the doped polysilicon film and the gate oxide film are partially patterned to form a gate electrode 21. At this time, the gate electrode 21 is preferably patterned such that the connection node 18 is located at one lower end thereof. Thereafter, a mask pattern (not shown) is formed to expose both sides of the gate electrode 21, and an N-type impurity is ion-implanted in the exposed portion to form source and drain regions 22 and 23. At this time, the source region 22 is formed to be located on the connection node 18.

Thereafter, as shown in FIG. 3 (h), an interlayer insulating film 24 is formed on the device layer 19. In this case, the interlayer insulating film 24 may be a planarization film such as a BPSG film. Then, a predetermined portion of the conductive layer 12 is patterned to expose the second hole H2.

Next, as shown in FIG. 3 (i), an auxiliary electrode 25 made of polysilicon doped to form contact with the exposed conductive layer 12 is formed. In this case, in order to fully insulate the device layer 19 and the auxiliary electrode 25, an oxide film spacer may be formed on the inner wall of the second hole H2, and then the auxiliary electrode 25 may be formed. Here, the auxiliary electrode 25 is formed to apply a positive voltage in order to improve the storage capacity of the capacitor under the device layer 19.

Thereafter, although not shown, the process of forming a bit line and the process of forming a metal wiring are performed as in the known DRAM forming method, thereby completing the DRAM device.

As described in detail above, according to the present invention, a semiconductor DRAM device is formed on an SOI substrate, and a storage node capacitor of the DRAM is formed between the device layer and the buried insulating layer to remove a portion protruding above the surface.

Therefore, the step difference between the cell area and the peripheral area due to the storage node capacitor can be reduced.

In addition, since the contact hole forming process for exposing the source and drain regions is excluded, the junction leakage current due to the etching of the source and drain regions is not generated.

Therefore, no leakage current of the DRAM element is generated.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (18)

Silicon wafers for handling; A buried insulating layer formed on the silicon wafer; A conductive layer formed on the buried insulating layer; A storage capacitor formed on the conductive layer; A planarization layer formed on the conductive layer including the storage capacitor and having a first hole for exposing the storage capacitor; A connection node formed on the planarization film including the first hole; A device layer formed on the planarization film; A gate electrode formed on a predetermined portion of the device layer; A source electrode and a drain region formed on device layers on both sides of the gate electrode, wherein the storage capacitor includes a plate electrode in contact with the conductive layer and having a pair of spacers symmetrical with each other, and the plate electrode and the conductive layer. And a storage electrode formed on the dielectric film, the storage electrode being formed to be in contact with the source region through the connection node. The semiconductor device of claim 1, further comprising: an interlayer insulating layer formed over the device layer; A second hole formed in the interlayer insulating film, the semiconductor layer and the planarization film; And an auxiliary electrode formed on the interlayer insulating film including the second hole so as to contact the conductive layer to increase capacitance of the capacitor. The semiconductor memory device according to claim 2, wherein the interlayer insulating film is a BPSG film. The semiconductor memory device of claim 2, wherein the auxiliary electrode is made of a conductive polysilicon film. The semiconductor memory device according to claim 1, wherein the connection node is made of a conductive polysilicon film. The semiconductor memory device according to claim 1, wherein the conductive layer is a conductive polysilicon film. The semiconductor memory device according to claim 1, wherein the device layer is a polysilicon film doped with P-type impurities. The semiconductor memory device according to claim 7, wherein the source drain region is an N-type impurity region. The semiconductor memory device of claim 1, wherein the storage node electrode and the plate electrode are conductive polysilicon layers. Forming a buried insulating film on the silicon wafer for handling; Forming a conductive layer on the buried insulating film; Forming a plate electrode having a structure in which a pair of spacers are symmetrical on a predetermined portion of the conductive layer; Forming a dielectric film on the plate electrode and the conductive layer; Forming a storage node electrode on the dielectric layer; Forming a planarization layer to sufficiently fill the storage node electrode; Forming a first hole to expose a predetermined portion of the storage node electrode; Forming a connection node on the planarization layer including the first hole to be in contact with the exposed storage node electrode; Forming a device layer over the entire structure; Forming a gate electrode on a predetermined portion of the device layer; And forming a source and a drain region in both device layers of the gate electrode, wherein the source region is formed to be in contact with the connection node. The method of claim 10, further comprising, after forming the source and drain regions, forming an interlayer insulating film on the device layer; Etching the interlayer insulating film, the device layer, the planarization film, and the dielectric film to expose a predetermined portion of the conductive layer to form a second hole; And forming an auxiliary electrode in contact with the conductive layer on the interlayer insulating film including the second hole. The method of manufacturing a semiconductor memory device according to claim 10, wherein the conductive layer is formed of a conductive polysilicon film. The method of claim 10, wherein the forming of the plate electrode comprises: forming a predetermined pattern on the conductive layer; Forming conductive spacers on both sides of the pattern; And removing the pattern. The method of claim 13, wherein the spacer is made of a conductive polysilicon film. The method of claim 10, wherein the device layer is a polysilicon film doped with P-type impurities. 16. The method of claim 15, wherein the source and drain regions are formed by ion implantation of N-type impurities. The method of claim 10, wherein the forming of the planarization film comprises: depositing a BPSG film; And flowing the BPSG film at a predetermined temperature. The method of claim 11, wherein the forming of the interlayer insulating film comprises: depositing a BPSG film; And flowing the BPSG film at a predetermined temperature.

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