KR100390041B1 - Method for forming the DRAM memory cell - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a DRAM memory cell. In particular, before the word line forming process, a bit line is formed in a semiconductor substrate using a damascene technique, and an interlayer insulating film is deposited on the semiconductor substrate to a predetermined thickness. Isolation process for device-to-device isolation is performed to form the entire DRAM cell region as an active region.As a result, the bit line formed in the semiconductor substrate serves as isolation between devices, thereby simplifying the isolation process of the DRAM cell region. In addition to reducing the probability of DRAM memory cell failure due to a site isolation process, the process for connecting the bit line and the section can be omitted, thereby simplifying the manufacturing process of the DRAM memory cell. It is about.

Description

Method for forming the DRAM memory cell

The present invention relates to a method of manufacturing a DRAM memory cell, and more particularly, to form a bit line in a semiconductor substrate using a damascene technique prior to the word line forming process, and to deposit an interlayer insulating film on the semiconductor substrate to a predetermined thickness. After the isolation process between the devices, the entire DRAM cell region is formed as an active region, thereby reducing the probability of DRAM memory cell failure caused by a specific region isolation process and connecting the bit line and the function. The DRAM memory cell, which can omit a process to simplify the manufacturing process of the DRAM memory cell, relates to a manufacturing method.

In general, a MOS (Metal-Oxide-Semiconductor) type DRAM (Dynamic Random Access Memory, hereinafter referred to as DRAM) has a memory cell consisting of one MOS transistor and one capacitor.

The bit line of a conventional DRAM cell is usually composed of metal lines, and is formed on the interlayer insulating layer stacked on the word line, and the bit line is formed in the junction region, which is the source and drain regions of the transfer gate transistor, through contact holes in the interlayer insulating layer. Connected.

1 is a plan view illustrating a DRAM memory cell array in order to describe a DRAM memory cell according to the related art.

As shown in FIG. 1, a plurality of bit lines 10 running in parallel in a row direction on a surface of a semiconductor substrate, a plurality of word lines 20 running in parallel in a column direction, and A plurality of memory cells arranged at adjacent intersections of the word line 20 and the bit line 10 are formed.

In this case, the memory cell is composed of one tracer gate transistor and one capacitor, and the transfer gate transistor forms an active region 50 by performing an isolation process for isolation between devices on the surface of the semiconductor substrate. A word line formed by stacking a gate insulating layer between the formed source and drain regions and the source and drain regions is formed.

After an interlayer insulating film (not shown) having a predetermined thickness is stacked on the word line, a contact hole for exposing source and drain regions of a transfer gate transistor is formed in the interlayer insulating film.

In this case, the contact hole 40 is a capacitor node connection part, and the contact hole 30 is a bit line connection part formed by photo and etching.

Subsequently, after gap filling with a plug of a conductive layer such as a polysilicon layer doped in the contact hole 40, an insulating film is deposited on the entire product formed with the plug to insulate the plug, and a bit line connection part using a photo and etching method. After forming the contact hole 30 on the plug, a conductive layer such as a doped polysilicon layer or a metal layer is patterned to form a bit line.

However, when using the conventional DRAM memory cell manufacturing method as described above, since the word line is formed and then the bit line is formed, an insulating film is formed between the word line and the bit line to prevent short between the word line and the bit line. There was a problem that the process is complicated by additional processes such as depositing.

In addition, since the bit line is formed on the word line, the height of the memory cell portion is increased, thereby reducing the process margin of the peripheral circuit portion.

As a result, there is a problem in that the cost of the memory cell manufacturing is increased by lowering the height of the memory cell part using an expensive chemical mechanical polishing process to secure the reduced margin.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to form a bit line in a semiconductor substrate using a damascene technique prior to a word line forming process, and to form an interlayer with a predetermined thickness on the semiconductor substrate. After the deposition of the insulating film, the isolation process between devices is formed to form the entire DRAM cell region as an active region, which simplifies the isolation process of the DRAM cell region, thereby reducing the probability of DRAM memory cell failure caused by the specific region isolation process. In addition, the process for connecting the bit line and the caption can be omitted, thereby simplifying the manufacturing process of the DRAM memory cell.

1 is a plan view illustrating a DRAM memory cell array in order to describe a DRAM memory cell according to the related art.

2 is a plan view illustrating a DRAM memory cell array to describe a DRAM memory cell according to an exemplary embodiment of the present invention.

3A through 3E are cross-sectional views sequentially illustrating a method of manufacturing a DRAM memory cell according to an exemplary embodiment of the present invention.

-Explanation of symbols for the main parts of the drawing-

100 semiconductor substrate 115 first interlayer insulating film

120: bit line 125: second photosensitive film

135: word line 145: spacer

150: third interlayer insulating film 155: polycrystalline polysilicon

160: fourth interlayer insulating film 165: capacitor

In order to achieve the above object, the present invention comprises the steps of: patterning a first photoresist film so that a bit line is formed on a semiconductor substrate, using the mask as a mask to form a bit line forming region by etching a predetermined thickness; Sequentially depositing a first interlayer dielectric layer and polycrystalline silicon on the resultant, and then performing a chemical mechanical polishing process to form a bit line; Forming an active region by forming a second photoresist layer on the resultant product on which the bit lines are formed, and performing an isolation process; Removing the second photoresist film, patterning a third photoresist film for ion implantation for adjusting the threshold voltage of a transistor, and performing ion implantation using the photoresist as a mask; Stacking a second interlayer insulating film on the resultant, and performing a photolithography and etching process to form a word line in the second interlayer insulating film; Forming a source and a drain by source and drain ion implantation on a semiconductor substrate using the word line as a mask, and then forming an spacer by applying an insulating material to the sidewalls of the word line; Stacking a third interlayer insulating film on the resultant, applying a fourth photosensitive film to etch the third interlayer insulating film, and depositing polycrystalline polysilicon on the etched portion to planarize the surface of the semiconductor substrate; Stacking a fourth interlayer insulating film on the planarized semiconductor substrate, patterning a fifth photoresist film, and forming a contact hole using the mask as a mask; And depositing a conductive material on the fourth interlayer insulating layer having the contact hole, thereby filling the contact hole to form a capacitor.

The present invention is characterized in that the bit line is formed in the semiconductor substrate before the word line is formed, thereby directly connecting the junction of the bit line and the cell transistor to the plug polycrystalline silicon without using the bit line contact.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a plan view illustrating a DRAM memory cell array to describe a DRAM memory cell according to an exemplary embodiment of the present invention.

As shown in FIG. 2, a plurality of bit lines 200 running in parallel in a row direction on the surface of the semiconductor substrate, a plurality of word lines 300 running in parallel in a column direction, and A plurality of memory cells arranged at adjacent intersections of the word line 300 and the bit line 200 are formed.

In this case, the memory cell is composed of one tracer gate transistor and one capacitor, and the transfer gate transistor forms a bit line in a semiconductor substrate, and performs an isolation process for isolation between devices on the semiconductor substrate, thereby forming an active region. After the 500 is formed, the word line 300 formed by stacking a gate insulating layer between the formed source and drain regions and the source and drain regions is formed.

After the interlayer insulating layer having a predetermined thickness is stacked on the word line 300, a contact hole 400 exposing the source and drain regions of the transfer gate transistor is formed in the interlayer insulating layer.

In this case, the contact hole 400 is formed by the photolithography and etching operations to the capacitor node connection portion.

Subsequently, after gap filling with a plug of a conductive layer such as a polysilicon layer doped in the contact hole 400, an insulating film is deposited on the entire product on which the plug is formed, and the plug is insulated. After forming contact holes (not shown) on the substrate, a capacitor is formed by patterning a conductive layer such as a doped polysilicon layer or a metal layer.

As a result, in the memory cell array, the word line 300 and the bit line 200 have a predetermined width and are orthogonal to each other at a predetermined spacing.

3A through 3E are cross-sectional views sequentially illustrating a method of manufacturing a DRAM memory cell according to an exemplary embodiment of the present invention.

As shown in FIG. 3A, after the first photoresist film (not shown) is patterned to form a bit line on the semiconductor substrate 100, the semiconductor substrate 100 is etched by a predetermined thickness to form a bit line using the mask as a mask. Form a site (not shown).

Subsequently, the first interlayer insulating film 115 is laminated and insulated on the resultant to have a thickness of about 100 to 3000 GPa, and then polycrystalline silicon is laminated to form a bit line 120.

Thereafter, a chemical mechanical polishing process is performed on the polycrystalline silicon film to planarize the semiconductor substrate.

As shown in FIG. 3B, the second photoresist layer 125 is formed on the resultant product on which the bit line 120 is formed to perform an isolation process to form an active region (not shown).

In this case, the second photoresist layer 125 is formed in a box shape to cover the entire cell region.

Subsequently, after removing the second photoresist film 125, a third photoresist film (not shown) for ion implantation for controlling the threshold voltage of the transistor is patterned, and ion implantation (not shown) for controlling the threshold voltage is performed using the mask as a mask. do.

In this case, the third photoresist layer (not shown) is patterned so that the portion where the cell transistor and the bit line are connected and the active region of the cell transistor are opened.

After that, as shown in FIG. 3C, a second interlayer insulating film (not shown) is stacked on the resultant, and a word line 135 is formed in the second interlayer insulating film by performing a photolithography and etching process.

After the source and drain ions are implanted on the semiconductor substrate 100 using the word line 135 as a mask to form a source and a drain (not shown), an insulating material is formed on the sidewalls of the word line 135. Is applied to form the spacer 145.

Subsequently, as shown in FIG. 3D, after stacking the third interlayer insulating film 150 on the resultant, a fourth photoresist film (not shown) is patterned, and the third interlayer insulating film 150 is used as a mask. Etch it.

In this case, the fourth photoresist layer (not shown) is patterned so that the portion where the cell transistor and the bit line are connected and the active region of the cell transistor are opened.

Thereafter, after the polycrystalline polysilicon 155 is deposited on the etched third interlayer dielectric layer 150, a chemical mechanical polishing process is performed to planarize the surface of the semiconductor substrate.

Subsequently, as shown in FIG. 3E, a fourth interlayer insulating film 160 is deposited on the planarized semiconductor substrate, and a fifth photoresist film (not shown) is patterned to form a contact hole, and then used as a mask. The fourth interlayer insulating layer 160 is etched to form a contact hole (not shown).

The contact hole is buried by depositing a conductive material on the fourth interlayer insulating layer 160 where the contact hole is formed to form a capacitor 165.

Therefore, as described above, when the DRAM memory cell manufacturing method according to the present invention is used, the bit line is formed in the semiconductor substrate by using the damascene technique before the word line forming process, and the semiconductor substrate has a predetermined thickness. After the deposition of the interlayer dielectric layer, an isolation process for device isolation is performed to form the entire DRAM cell region as an active region, thereby reducing the probability of DRAM memory cell failure caused by a specific region isolation process, as well as the bit line and section. The process for connecting the circuits may be omitted, thereby simplifying a manufacturing process of the DRAM memory cell.

Claims (5)

Patterning the first photoresist layer to form a bit line on the semiconductor substrate, and then etching the semiconductor substrate by a predetermined thickness to form a bit line forming portion using the mask as a mask; Sequentially depositing a first interlayer dielectric layer and polycrystalline silicon on the resultant, and then performing a chemical mechanical polishing process to form a bit line; Forming an active region by forming a second photoresist layer on the resultant product on which the bit lines are formed, and performing an isolation process; Removing the second photoresist film, patterning a third photoresist film for ion implantation for adjusting the threshold voltage of a transistor, and performing ion implantation using the photoresist as a mask; Stacking a second interlayer insulating film on the resultant, and performing a photolithography and etching process to form a word line in the second interlayer insulating film; Forming a source and a drain by source and drain ion implantation on a semiconductor substrate using the word line as a mask, and then forming an spacer by applying an insulating material to the sidewalls of the word line; Stacking a third interlayer insulating film on the resultant, applying a fourth photosensitive film to etch the third interlayer insulating film, and depositing polycrystalline polysilicon on the etched portion to planarize the surface of the semiconductor substrate; Stacking a fourth interlayer insulating film on the planarized semiconductor substrate, patterning a fifth photoresist film, and forming a contact hole using the mask as a mask; And depositing a conductive material on the fourth interlayer dielectric layer having the contact hole, thereby filling the contact hole to form a capacitor. 2. The method of claim 1, wherein the first interlayer dielectric film is laminated and insulated to a thickness of 100 to 3000 GPa. The method of claim 1, wherein the second photoresist layer is formed in a box shape covering the entire cell region. The method of claim 1, wherein the third photoresist layer is formed such that a portion of the cell transistor and the bit line is connected and an active region of the cell transistor is opened. The method of claim 1, wherein the fourth photoresist layer is formed such that a portion of the cell transistor and the bit line is connected and an active region of the cell transistor is opened.