KR0155840B1 - Mosfet and their manufacture - Google Patents

Abstract

A MOS transistor and a manufacturing method thereof are described. This includes a semiconductor substrate, a buried insulating layer formed on the semiconductor substrate, a bit line formed on the buried insulating layer, an insulating layer formed on the bit line and having a contact hole formed therein, inside and inside the contact hole. And a channel conductive layer of the transistor formed to extend to an upper portion of the layer, a gate insulating layer formed on the channel conductive layer, and a gate conductive layer formed in a direction perpendicular to the bit line on the gate insulating layer.

Therefore, the amount of change in the threshold voltage is reduced, and the process can be simplified.

Description

MOS transistor and its manufacturing method

1 is a cross-sectional view showing a conventional general MOS transistor.

2 is a cross-sectional view showing a MOS transistor formed of a conventional SOI structure.

3 is a cross-sectional view illustrating a MOS transistor according to an embodiment of the present invention.

4A through 4G are flowcharts illustrating a method of manufacturing a MOS transistor according to an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor and a method of manufacturing the same, and more particularly, to a MOS transistor having a structure of a silicon on insulator (hereinafter referred to as SOI) and a method of manufacturing the same.

In general, a cell transistor of a semiconductor memory device is formed of a MOS (hereinafter, referred to as a MOS) transistor, which is formed between a source and a drain formed by ion implantation of a conductive impurity opposite to a substrate on a semiconductor substrate, and is formed between the source and the drain. A gate and a gate are formed on the substrate via a gate insulating film.

1 is a cross-sectional view showing a conventional general MOS transistor, wherein reference numeral 1 denotes a semiconductor substrate, 3 denotes a gate oxide film, 5 denotes a gate conductive layer, and 7 and 9 denote source and drain, respectively.

When the cell transistor of the semiconductor memory device is formed using the conventional MOS transistor, the following problems occur due to high integration.

First, since a device isolation region is required for device and device isolation, it is disadvantageous in terms of chip size reduction for high integration. Second, decreasing the channel width to increase the current driveability decreases the transistor reliability due to an increase in the hot carrier effect due to the high electrin field at the edge of the field oxide layer.

Third, since the depletion region is formed in a relatively large region of the substrate, a large number of charges affect the threshold voltage, so that the sub-threshold swing is large.

Fourth, when the MOS transistor is applied to CMOS, latch-up occurs due to the operation of the parasitic junction transistor, which adversely affects the reliability of the device.

Therefore, in recent years, many researches have been conducted on MOS transistors having an SOI structure capable of reducing chip size and eliminating parasitic effects such as latch-up. SOI technology is a technology for more effectively separating the semiconductor devices formed on the semiconductor substrate, forming a buried oxide on the silicon substrate, and then partially forming the upper silicon layer on the buried oxide film, and then It is a technique of forming a semiconductor element in this upper silicon layer.

2 is a cross-sectional view showing a MOS transistor formed of a conventional SOI structure, in which reference numeral 11 denotes a semiconductor substrate, 13 denotes a buried insulating layer, 15 denotes a silicon layer, 17 denotes a gate insulating layer, and 19 denotes a gate conductive layer. , 21 and 23 represent the source and the drain, respectively.

The MOS transistor having the SOI structure is formed in a silicon layer stacked on the buried insulating layer 13, and the silicon layer under the gate conductive layer 19 becomes a channel region. The silicon layer at the right becomes the source and drain 21 and 23.

The SOI structure is stronger in light and stronger in supply voltage than a semiconductor device formed by junction isolation technology. Also, in general, the number of processes required by the semiconductor device formed on the SOI is smaller than the semiconductor device formed on the bulk silicon, and the capacitive coupling between semiconductor devices formed in the IC chip is reduced. Thin-film SOI devices also outperform conventional bulk devices by improving sub-threshold swings, high charge mobility, and reduced hot-carrier effects. Has characteristics.

However, there is a limit in forming a cell transistor of a memory device highly integrated with the MOS transistor of the conventional general SOI structure. Problems caused by a decrease in chip size due to an increase in integration density of 1 gigabit or more, in particular, instability of a transistor threshold voltage caused by a short channel effect cannot be solved.

Accordingly, it is an object of the present invention to provide a MOS transistor with an SOI structure that can solve the above problems.

Another object of the present invention is to provide a manufacturing method suitable for manufacturing the MOS transistor of the SOI structure.

The present invention to achieve the above object, a semiconductor substrate; A buried insulating layer formed on the semiconductor substrate; A bit line formed on the buried insulating layer; An insulating layer formed on the bit line and having a contact hole formed therein; A channel conductive layer of the transistor formed inside the contact hole and extending to an upper partial region of the insulating layer; A gate insulating film formed on the channel conductive layer; A cell transistor is provided on the gate insulating layer, the gate conductive layer being formed in a direction perpendicular to the bit line.

According to a preferred embodiment of the present invention, the contact hole formed inside the insulating layer is formed in a cylindrical shape, and the channel conductive layer is patterned to be spaced apart from the channel conductive layer of the adjacent transistors by a predetermined distance to electrically insulate the adjacent transistors. do.

The bit line may be formed of two layers having different dielectric constants, and the dielectric constant of the upper layer may be large, and may have a double layer structure of an upper layer formed of polycrystalline silicon and a lower layer formed of tungsten silicide.

The channel conductive layer may be formed of polysilicon, and may be formed using epitaxial growth or MBE (Molecular Beam Epitaxial).

Meanwhile, in the cell transistor according to the present invention, an oxide film may be formed on the channel conductive layer and the gate electrode to reduce an electric field generated at the boundary edge of the channel conductive layer and the gate conductive layer, wherein the oxide film is 50 kV. It is formed to a thickness of ˜100 mm 3. In addition, the cell transistor according to the present invention may further include a storage electrode formed to contact one side of the upper channel conductive layer of the insulating layer through the planarization layer on the channel conductive layer, or the planarization layer on the channel conductive layer. The display device may further include a storage electrode formed to contact both sides of the insulating layer upper channel conductive layer.

In order to achieve the above another object, the present invention, forming a buried insulating layer on a semiconductor substrate; Forming a bit line on the buried insulating layer; Forming an insulating layer on the bit line; Forming a contact hole in the insulating layer to expose a portion of the bit line; Forming a channel conductive layer on the resultant in which contact holes are formed; Forming a gate oxide film on the channel conductive layer; And forming a gate conductive layer on the gate oxide film.

According to a preferred embodiment, after the step of forming the gate conductive layer, forming a planarization layer by depositing an insulator on the resultant formed gate conductive layer;

Forming a contact hole in the planarization layer to expose a portion of the channel conductive layer; And

The method may further include forming a storage electrode by depositing a conductive material on the resultant.

The contact hole may be formed in a cylindrical shape, and the gate conductive layer may be formed to fill an upper portion of the channel conductive layer formed in a cylindrical shape.

According to the present invention, since the depletion region for controlling the threshold voltage is reduced, the amount of change in the threshold voltage is reduced, and since the individual elements are patterned so as to be insulated, the process does not require a photolithography process for separation between the elements. It is possible.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

3 is a cross-sectional view illustrating a MOS transistor having an SOI structure according to an embodiment of the present invention.

Reference numeral 50 is a semiconductor substrate, 52 is a buried insulating layer, 54 is a bit line, 56 is an insulating layer, 58 is a channel conductive layer, 60 is a gate insulating layer, 62 is a gate conductive layer, 64 is a planarization And 66 denote storage electrodes.

Here, the channel conductive layer 58 and the bit line 54 are connected through a contact hole formed in the insulating layer 56. Therefore, the channel conductive layer 58 in the portion adjacent to the bit line 54 at the bottom of the contact hole becomes the drain of the transistor. In addition, the channel conductive layer 66 to which the channel conductive layer 58 formed on the insulating layer 56 is connected becomes a source of the transistor.

On the other hand, the contact hole formed in the insulating layer 56 may be formed in a cylindrical shape so that the current flows more smoothly and the thickness of the gate oxide film is uniformly formed.

The channel conductive layer 58 is preferably patterned to be electrically insulated from adjacent transistors, and may be formed of polycrystalline silicon. In addition, the channel conductive layer 58 may be formed using an epitaxial growth method or may be formed by a MBE (Moleculer Beam Epitaxial) method.

The bit line 54 may be formed of two conductive layers, and may have a double layer structure of an upper layer formed of polycrystalline silicon and a lower layer formed of tungsten silicide.

On the other hand, an oxide film may be formed on the channel conductive layer and the gate electrode to reduce the electric field generated at the boundary between the channel conductive layer 58 and the gate conductive layer 62, the oxide film is 50 ~ 100Å It is preferable that it is formed in thickness.

4A through 4G are flowcharts illustrating a method of manufacturing a MOS transistor having an SOI structure according to an embodiment of the present invention.

4A is a cross-sectional view showing the step of forming the buried insulating layer 52, wherein the buried insulating layer 52 is formed on the semiconductor substrate 50 using a conventional thermal oxidation process or a CVD method. do.

FIG. 4B is a cross-sectional view illustrating the formation of the bit line 54 and the insulating layer 56. A conductive material such as polysilicon is deposited on the buried insulating layer 52, and then patterned to form the bit line 54. FIG. To form. Subsequently, an insulating material, for example, nitride, is deposited on the bit line 54 to form the insulating layer 56.

Here, the bit line 54 may be formed in a double layer structure of two different conductive layers, for example, an upper layer formed of polycrystalline silicon and a lower layer formed of tungsten silicide.

4C is a cross-sectional view illustrating the step of forming the contact hole h by patterning the insulating layer 56. The photoresist is applied on the insulating layer 56, and then patterned to form the first photoresist pattern 57. FIG. ) And forming a contact hole h exposing a portion of the bit line 54 by etching the insulating layer 56 using the first photoresist pattern 57 as an etching mask.

In this case, the contact hole h may be formed in a cylindrical shape so that the current flows more smoothly and the thickness of the gate oxide film is uniformly formed.

Here, impurities, such as arsenic (As) or the like, are formed in the bit line 54 exposed by the contact hole h to form an ohmic contact with a channel conductive layer to be formed later, that is, to reduce contact resistance. An ion of n-type impurity may be ion-implanted, or a fockle (POCl ₃ ) may be deposited to increase conductivity of the bit line. Meanwhile, a highly doped polysilicon layer may be formed on the bit line 54 using a chemical vapor deposition method, or an epitaxial layer may be formed.

FIG. 4D is a cross-sectional view illustrating the formation of the channel conductive layer 58, wherein a contact hole removes the first photoresist pattern 57, and then a conductive material is formed in the contact hole and on the insulating layer 56. For example, the channel conductive layer 58 is formed by depositing polysilicon doped with impurities. Subsequently, a photoresist is applied on the channel conductive layer 58 and then patterned to form a second photoresist pattern 59.

Here, the channel conductive layer 58 may be formed of polycrystalline silicon doped with n-type or p-type impurities using the CVD method or the MBE method. In addition, the channel conductive layer 58 may be formed as an epitaxial layer doped with n-type impurities.

The channel conductive layer 58 and the bit line 54 are connected through the contact hole h, and the channel conductive layer 58 adjacent to the bit line 54 at the bottom of the contact hole is connected to the transistor. It becomes a drain. In addition, the channel conductive layer 58 formed on the second insulating layer 56 becomes a source of the transistor and is connected to the storage electrode of the capacitor.

FIG. 4E is a cross-sectional view illustrating the step of patterning the channel conductive layer 58 and forming the gate insulating layer 60. The channel conductive layer is etched using the second photoresist pattern 59 as an etch mask. The gate insulator 60 60 is formed on the 58 by using a conventional thermal oxidation process.

Here, the channel conductive layer 58 is patterned to be formed only on a portion of the insulating layer 56 and electrically insulated from the channel conductive layer (not shown) of adjacent transistors.

4F is a cross-sectional view showing the formation of the gate conductive layer 62, in which, for example, polycrystalline silicon is deposited on the resultant on which the channel conductive layer 58 is formed, and then patterned to form the gate conductive layer 62. FIG. do.

Here, the gate conductive layer 62 may be buried in the recessed portion formed by the contact hole, it may be formed in the form of a square so as to have a predetermined thickness on the channel conductive layer (58).

On the other hand, if necessary, an oxide film is formed on the resultant in which the gate conductive layer is formed to reduce the electric field generated at the edges of the channel conductive layer 58 and the gate conductive layer 62. It can be formed in thickness.

4G is a cross-sectional view illustrating a step of forming a storage electrode 66 of a capacitor, wherein the planarization layer 64 applies an insulator, for example, BPSG, to planarize the surface of the resultant by applying an insulator, for example, BPSG, on the resultant having the gate conductive layer 62 formed thereon. ), And then the planarization layer 64 is etched to expose a portion of the channel conductive layer 58 corresponding to the source of the transistor. Subsequently, a polysilicon doped with a conductive material such as impurities is deposited on the planarization layer 64 to form a storage electrode 66 connected to the channel conductive layer 58.

Here, a portion of the channel conductive layer 58 connected to the storage electrode 66 corresponds to a source of a transistor, and the storage electrode and the source are in contact with two portions on the left and right sides of the gate conductive layer, so that the current Ability is bigger than conventional.

The storage electrode 66 may be connected to a channel conductive layer formed on a left side of a portion of the channel conductive layer 58, for example, a gate conductive layer.

According to the present invention, since the depletion region controlling the threshold voltage is reduced, the amount of change in the threshold voltage is reduced, and since the individual elements are patterned so as to be insulated, the process does not require a photolithography process for separation between the elements. It is possible.

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical idea to which the present invention pertains.

Claims (16)

Semiconductor substrates; A buried insulating layer formed on the semiconductor substrate; A bit line formed on the buried insulating layer; An insulating layer formed on the bit line and having a contact hole formed therein; A channel conductive layer of the transistor formed inside the contact hole and extending to an upper portion of the insulating layer; A gate insulating film formed on the channel conductive layer; And a gate conductive layer formed on the gate insulating layer in a direction perpendicular to the bit line. The cell transistor of claim 1, wherein the contact hole formed in the insulating layer is cylindrical. The cell transistor of claim 1, wherein the channel conductive layer is patterned to be spaced apart from the channel conductive layer of an adjacent transistor by a predetermined distance and electrically insulated from the adjacent transistor. The cell transistor of claim 1, wherein the bit line is formed of two different conductive layers. The cell transistor of claim 4, wherein the bit line has a double layer structure of an upper layer formed of polycrystalline silicon and a lower layer formed of tungsten silicide. The cell transistor of claim 1, wherein the channel conductive layer is formed of polycrystalline silicon. The cell transistor of claim 1, wherein the channel conductive layer is formed using an epitaxial growth method. The cell transistor of claim 1, wherein the channel conductive layer is formed by a molecular beam epitaxial (MBE) method. The cell transistor of claim 1, wherein an oxide layer is formed on the channel conductive layer and the gate electrode to reduce an electric field generated at a boundary edge between the channel conductive layer and the gate conductive layer. 10. The cell transistor according to claim 9, wherein the oxide film has a thickness of 50 mV to 100 mV. The cell transistor of claim 1, further comprising a storage electrode formed on the channel conductive layer to contact one side of the upper channel conductive layer of the insulating layer through a planarization layer. The cell transistor of claim 1, further comprising a storage electrode formed on the channel conductive layer to contact both sides of the upper channel conductive layer of the insulating layer through a planarization layer. Forming a buried insulating layer on the semiconductor substrate; Forming a bit line on the buried insulating layer; Forming an insulating layer on the bit line; Forming a contact hole in the insulating layer to expose a portion of the bit line; Forming a channel conductive layer on the resultant in which contact holes are formed; Forming a gate oxide film on the channel conductive layer; And forming a gate conductive layer on the gate oxide film. 15. The method of claim 13, further comprising, after forming the gate conductive layer, forming an planarization layer by depositing an insulator on the resultant formed gate conductive layer; Forming a contact hole in the planarization layer to expose a portion of the channel conductive layer; And depositing a conductive material on the resultant to form a storage electrode. The method of claim 13, wherein the contact hole is formed in a cylindrical shape. The method of claim 15, wherein the gate conductive layer is formed to fill an upper portion of the channel conductive layer having a cylindrical shape.