KR100390920B1 - Vertical structure transistor having multi-channel and method for fabricating the same - Google Patents

Abstract

The present invention discloses a vertical structure transistor having a multi-channel and a method of manufacturing the same. The disclosed multi-channel vertical structure transistor includes a silicon substrate; A source region formed on a surface of the silicon substrate; An insulating film formed to expose a portion of the silicon substrate including the source region; A silicon pillar formed on the exposed substrate region and an insulating layer portion adjacent thereto and having a hole in a central portion thereof; A gate insulating film formed on a surface of the silicon pillar including the hole and an insulating film; An outer gate formed in the hole of the silicon pillar to be in contact with the outside of the silicon pillar through the inner gate and the gate insulating film; A drain region formed in a horizontal plane of the silicon pillar; An interlayer insulating film formed on the gate insulating film, the inner gate and the outer gate; And a first metal wiring formed on the interlayer insulating layer, the first metal wiring formed to electrically connect the inner gate and the outer gate, the second metal wiring formed to contact the source region, and the third metal wiring formed to contact the drain region. Include.

Description

Vertical structure transistor having multi-channel and manufacturing method therefor {VERTICAL STRUCTURE TRANSISTOR HAVING MULTI-CHANNEL AND METHOD FOR FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical structure transistor, and more particularly, to a vertical structure transistor having a multi-channel capable of suppressing short channel effects while implementing a deep sub 0.1 μm channel length and a method of manufacturing the same. It is about.

As the degree of integration of semiconductor devices increases, the size of the patterns included in the circuit is reduced, and in particular, the miniaturization of the gate is required. The miniaturization of the gate also means a reduction in the channel length, which is very important for high speed circuit operation in that the propagation delay in the circuit is approximately proportional to the square of the channel length.

However, the miniaturization of gates requires improved photolithography equipment and techniques, and difficulties remain.

Accordingly, various techniques for miniaturizing the gate, that is, reducing the channel length have been proposed, and as an example, a vertical structure transistor has been proposed.

In the vertical transistor, since the channel is formed in the vertical direction, the channel length is determined by the thickness of the active layer, not the width of the active layer. Thus, the vertical structure transistor can reduce the channel length more effectively compared to a typical planar structure transistor without having to rely on the existing photolithography process.

1 is a cross-sectional view illustrating a vertical structure transistor according to the prior art, which will be described below.

As shown, a silicon substrate 1 having a silicon pillar (Si pillar 1a) is provided in place through selective etching or the like, and ions of impurities are formed on the surface of the substrate 1 and the surface of the silicon pillar 1a. Source and drain regions 3 and 4 are formed through implantation. A gate insulating film 5 is formed on the surface of the silicon pillar 1a and the substrate 1 including the source and drain regions 3 and 4, and the gate is in contact with the source region 3 and the drain region 4, respectively. A source electrode 6 and a drain electrode 7 are formed on the insulating film 5, and a gate electrode 8 is formed on the gate insulating film portion between the source region 3 and the drain region 4. Here, the gate electrode 8 and the source and drain electrodes 6 and 7 are simultaneously formed of a predetermined metal film.

In such a vertical structure transistor, a channel is formed at the side of the silicon pillar 1a between the source region 3 and the drain region 4, where the channel length is not the width of the silicon pillar 1a but the silicon pillar. It is determined by the height of (1a), that is, the thickness.

Therefore, the vertical structure transistor can adjust the channel length by adjusting the thickness of the silicon pillar, so that the channel length can be easily adjusted without depending on the photolithography process.

However, the vertical structure transistor as described above has a problem that it is difficult to form a structurally shallow junction despite the above advantages.

In addition, in the proposed structure, the source and drain regions are formed through ion implantation of impurities into a horizontal plane of a silicon pillar serving as a channel. In this case, since the horizontal planes of the silicon pillar are both source and drain junction surfaces, In addition to a large leakage current, there is a problem in that the short channel effect is very vulnerable. In particular, considering that the biggest advantage of the vertical structure transistor can realize a deep sub 0.1 μm channel length, a countermeasure for the short channel effect is required.

Accordingly, an object of the present invention is to provide a vertical structure transistor having a multi-channel capable of suppressing short channel effects while implementing a deep sub 0.1 μm channel length and a method of manufacturing the same. There is this.

1 is a cross-sectional view showing a vertical structure transistor according to the prior art.

2A is a plan view of a vertical structure transistor having multiple channels according to an embodiment of the present invention.

FIG. 2B is a cross-sectional view taken along the line AA ′ of FIG. 2A; FIG.

3A and 3B show voltage / current characteristic curves for vertical and vertical structure transistors of the present invention.

4A to 4F are cross-sectional views of processes for describing a method of manufacturing a vertical transistor according to an embodiment of the present invention.

5A and 5B are cross-sectional views illustrating a method of manufacturing a vertical transistor according to another embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

11 semiconductor substrate 12 insulating film

13: source region 14: silicon pillar

15 gate insulating film 16 polysilicon film

16a: inner gate 16b: outer gate

17 drain region 18 interlayer insulating film

19a, 19b: Contact hole 20a, 20b: Metal wiring

H: Hall

Vertical structure transistor having a multi-channel of the present invention for achieving the above object, a silicon substrate; A source region formed on a surface of the silicon substrate; An insulating film formed to expose a portion of the silicon substrate including the source region; A silicon pillar formed on the exposed substrate region and an insulating layer portion adjacent thereto and having a hole in a central portion thereof; A gate insulating film formed on a surface of the silicon pillar including the hole and an insulating film; An outer gate formed in the hole of the silicon pillar to be in contact with the outside of the silicon pillar through the inner gate and the gate insulating film; A drain region formed in a horizontal plane of the silicon pillar; An interlayer insulating film formed on the gate insulating film, the inner gate and the outer gate; And a first metal wiring formed on the interlayer insulating layer, the first metal wiring formed to electrically connect the inner gate and the outer gate, the second metal wiring formed to contact the source region, and the third metal wiring formed to contact the drain region. Include.

In addition, a method of manufacturing a multi-channel vertical structure transistor of the present invention for achieving the above object comprises the steps of providing a silicon substrate with an insulating film formed on the surface; Forming a source region on the surface of the silicon substrate through ion implantation; Patterning the insulating film to expose a predetermined region of a silicon substrate; Forming a silicon pillar having a hole in a central portion of the exposed substrate region and an insulating layer portion adjacent thereto; Forming a gate insulating film on a surface of the silicon pillar including the hole and an insulating film; Depositing a doped polysilicon film on a gate insulating film to completely fill the hole; Etching the doped polysilicon film to expose a portion of the gate insulating film on the silicon pillar to form an outer gate outside the silicon pillar while forming an inner gate inside the hole of the silicon pillar; Forming a drain region through ion implantation in a horizontal plane of the silicon pillar; Forming an interlayer insulating film on the resultant product; Forming a first metal interconnection electrically connecting the inner gate and the outer gate to the interlayer insulating layer, a second metal interconnection contacting the source region, and a third metal interconnection contacting the drain region.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A is a plan view illustrating a vertical structure transistor having multiple channels according to an embodiment of the present invention.

Referring to FIG. 2A, a multi-channel vertical structure transistor of the present invention has a cylindrical or hexahedral shape in which a silicon pillar (not shown) in which a channel is formed may be filled, and in particular, the gate is a silicon pillar. It is composed of an inner gate (16a) disposed in the inner side and an outer gate (16b) disposed in the outside of the silicon pillar to surround the silicon pillar as a whole, that is, a double surround gate (double surround gate) Has a structure. In addition, the first metal wiring 20a is formed to connect the inner gate 16a and the outer gate 16b, and the second metal wiring 20b and the third metal wiring 20c are source and drain regions, respectively. And not shown).

FIG. 2B is a cross-sectional view taken along the line A-A 'of FIG. 2A, which will be described below.

As shown, the source region 13 is formed inside the surface of the silicon substrate 11 through ion implantation, and the insulating film 12 is formed on the surface thereof. A portion of the insulating layer 12 is removed to expose a portion of the substrate 11, and the silicon may have a shape in which a hole may be formed in the center of the exposed portion of the substrate and the portion of the insulating layer adjacent thereto. Pillar 14 is formed. Here, the silicon pillar 14 may be formed through selective epitaxial growth (SEG) or a deposition process.

Subsequently, a gate insulating film 15 is formed on the substrate 11 including the source region 13 and the silicon pillar 14, and an inner layer made of a doped polysilicon film on each of the inside and the outside of the silicon pillar 14. A gate 16a and an outer gate 16b are formed, and a drain region 17 is formed on the horizontal surface of the silicon pillar 14 through ion implantation.

An interlayer insulating film 18 is formed on the gate insulating film 15, the inner gate 16a, and the outer gate 16b, and the inner gate (eg, through the first contact holes 19a) is formed on the interlayer insulating film 18. The first metal wiring 20a is formed to electrically connect the 16a and the outer gate 16b, and at the same time, the second metal wiring 20b is brought into contact with the source region 13 through the second contact hole 19b. ) Is formed, and a third metal wiring (not shown) is formed to contact the drain region 17 through the third contact hole (not shown).

In the vertical structure transistor according to the present invention, the channel is formed in the vertical direction in each of the silicon pillar portion adjacent to the outer side of the inner gate (16a) and the inner side of the outer gate (20b), accordingly, Vertical structure transistors have multiple channels.

Accordingly, the vertical structure transistor of the present invention having multiple channels has an increased channel controllability of the gate, so that the short channel effect can be suppressed as compared with the vertical structure transistor having a single channel as shown in FIG. Is improved.

3A and 3B are diagrams illustrating voltage / current characteristic curves of the vertical structure transistors of the related art and the present invention. As illustrated, the vertical structure transistors of the present invention have a double surround gate structure. It can be seen that the voltage / current characteristic (see FIG. 3B) is greatly improved compared to that in the conventional vertical structure transistor (see FIG. 3A).

That is, the vertical transistor of the present invention has multiple channels due to the formation of gates on both the inner and outer portions of the silicon pillar serving as a channel, and thus, the short channel effect, which is a problem in the transistor having one channel, is greatly reduced. It can greatly reduce and maximize the driving current per unit area.

As a result, the vertical structure transistor of the present invention can easily implement a deep sub 0.1 μm channel length by forming the channel in the vertical direction, and can also effectively suppress the short channel effect due to having multiple channels.

Hereinafter, a method of manufacturing a vertical structure transistor having a multichannel according to the present invention as described above will be described with reference to FIGS. 4A to 4F.

Referring to FIG. 4A, an insulating film 12, such as a silicon oxide film (SiO 2), is formed on a silicon substrate 11, and then penetrated through the insulating film 12 to form a source region. An impurity of a predetermined conductivity type is implanted into the surface of the c).

Referring to FIG. 4B, annealing is performed on the resultant to form a source region 13 inside the surface of the substrate 11. Then, the insulating film 12 is patterned so that a portion of the substrate 11 is exposed, and then a silicon pillar 14 is formed on the exposed substrate region through the SEG process and the portion of the insulating film adjacent thereto.

Here, the SEG process is preferably performed at a temperature of 700 to 800 ° C. During the SEG process, impurities that are already implanted onto the surface of the substrate 11 to form the source region 13 are formed of silicon pillars ( 14) or by diffusing to the substrate portion below the silicon pillar 15, the electrical characteristics of the manufactured transistor may be degraded. This is because the diffusion of impurities may occur very actively through defects generated during ion implantation to form the source region 13 at a temperature at which the SEG process proceeds.

Therefore, in the exemplary embodiment of the present invention, RTA (Rapid Thermal Annealing) is performed prior to performing the SEG process to cure defects generated during ion implantation, thereby diffusing the implanted impurities during the SEG process. It is suppressed, thereby preventing the deterioration of the electrical properties.

Referring to FIG. 4C, in order to obtain a double surround gate structure, the silicon pillar 14 is patterned into a predetermined shape, and a hole H is formed in a central portion thereof so as to fill the inside thereof.

Here, the overall shape of the patterned silicon pillar 14 may be variously changed according to the purpose of use of the transistor. For example, in the case of cylindrical patterning, since there is no corner where the electric field is concentrated, deterioration of the gate insulating film can be prevented. In addition, when patterning into a hexahedral shape, a channel may be formed first at an edge portion, and although the channel formed at the edge only contributes to on-current, such a channel may be formed inside and outside the hexahedron. Since eight pieces are formed in all, sufficient driving current characteristics can be obtained, and therefore, the characteristics bonded to the low voltage driving circuit can be realized.

Subsequently, a gate insulating film 15 made of a silicon oxide film or the like is formed on the surface of the substrate 11 including the patterned silicon pillars 14 and on the gate insulating film 15 so that the hole H is completely buried. The doped polysilicon film 16 is deposited.

Referring to FIG. 4D, the doped polysilicon film 16 is polished or etched back using the CMP process until the gate insulating film portion on the silicon pillar 14 is exposed. In this case, an inner gate 16a is formed in the hole H of the silicon pillar 14. Subsequently, an ion implantation process for forming a drain is performed on the resultant without using a mask, and an ion of a predetermined conductivity type is implanted into the surface of the silicon pillar 14 through the exposed gate insulating layer.

Referring to FIG. 4E, the resultant region is annealed to form a drain region 17 on a horizontal surface of the silicon pillar 14. Then, the doped polysilicon layer is patterned to contact the silicon pillar 14 via the gate insulating layer 15 to form an outer gate 16b. Subsequently, after the interlayer insulating film 18 is formed on the gate insulating film 15, the inner gate 16a, and the outer gate 16b, the interlayer insulating film 18, the interlayer insulating film 18, and the gate insulating film 15 are formed. And first contact holes 19a and source regions exposing the inner gate 16a and the outer gate 16b by etching the insulating layer 12, the interlayer insulating layer 18, and the gate insulating layer 15. The second contact hole 19b exposing the 13 and the third contact hole (not shown) exposing the drain region 17 are formed.

Referring to FIG. 4F, a predetermined metal film is deposited on the interlayer insulating film 18 so that the first, second and third contact holes are completely filled, and then the metal film is patterned to form the inner gate 16a. A first metal wiring 20a electrically connecting the outer gates 16b, a second metal wiring 20b in contact with the source region 13, and a third metal wiring in contact with the drain region 17; (Not shown) are formed at the same time, respectively, and as a result, the multi-channel vertical structure transistor of the present invention is completed.

On the other hand, the vertical structure transistor having a multi-channel according to the present invention can maximize the size of the drive current per unit area, while the minimum size that can be manufactured is relatively larger than that of the conventional. This is because the gate surrounds the silicon pillar, and in order to form an inner gate, it is difficult to reduce the length of one side of the silicon pillar, for example, the diameter to 2 lambda or less in the case of a cylinder. Here, lambda represents the minimum pitch size that can be defined.

Therefore, in order to overcome this disadvantage, after the deposition of the doped polysilicon film corresponding to Fig. 4d in the above-described embodiment as another embodiment of the present invention, as shown in Fig. 5a, the doped polysilicon film is RIE (Reaction Ion Etching) by performing a blanket etching to form the outer gate 16b in the form of a spacer, not in the form of a square pattern in the above-described embodiment, and then, as shown in Figure 5b, Ion implantation for drain region formation is performed.

In this case, it is possible to reduce the device area than the previous embodiment, and in particular, since a separate patterning process for the subsequently doped polysilicon film is not necessary, a side effect of the process reduction can be obtained.

As another embodiment of the present invention, in the previous embodiments, the silicon pillar was formed through the SEG process, but may be formed through the polysilicon deposition process instead of the SEG process. In this way, the production of a three-dimensional device is also possible by using a polysilicon device.

As described above, since the present invention forms a transistor in a vertical structure, it is possible to easily implement a deep sub 0.1 μm channel length without performing a complex photolithography device and a process using the same, and also to use the complex photolithography device. Omitting the production cost can be reduced.

In addition, the present invention is to form a transistor in a vertical structure, but due to the adoption of a double surround gate structure in which the gate is disposed on each of the inner and outer sides of the silicon pillar in which the channel is formed, it is possible to improve the current driving force, accordingly, short The channel effect can be effectively suppressed, and consequently, the improvement of device characteristics enables the manufacture of high performance devices.

In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.

Claims (13)

Silicon substrates; A source region formed on a surface of the silicon substrate; An insulating film formed to expose a portion of the silicon substrate including the source region; A silicon pillar formed on the exposed substrate region and an insulating layer portion adjacent thereto and having a hole in a central portion thereof; A gate insulating film formed on a surface of the silicon pillar including the hole and an insulating film; An outer gate formed in the hole of the silicon pillar to be in contact with the outside of the silicon pillar through the inner gate and the gate insulating film; A drain region formed in a horizontal plane of the silicon pillar; An interlayer insulating film formed on the gate insulating film, the inner gate and the outer gate; And A first metal wiring formed on the interlayer insulating layer, the first metal wiring formed to electrically connect the inner gate and the outer gate, a second metal wiring formed to contact the source region, and a third metal wiring formed to contact the drain region; A vertical structure transistor having a multi-channel, characterized in that. The vertical structure transistor of claim 1, wherein the silicon pillar has a cylindrical or hexahedral shape. The vertical structure transistor of claim 1, wherein the silicon pillar is made of single crystal silicon formed through a selective epitaxial growth process. The vertical structure transistor of claim 1, wherein the silicon pillar is made of polycrystalline silicon formed through a deposition process. The vertical structure transistor of claim 1, wherein the outer gate is formed in a rectangular pattern or a spacer shape. Providing a silicon substrate having an insulating film formed on the surface thereof; Forming a source region on the surface of the silicon substrate through ion implantation; Patterning the insulating film to expose a predetermined region of a silicon substrate; Forming a silicon pillar on the exposed substrate region and the portion of the insulating film adjacent thereto, the silicon pillar having a hole in a central portion thereof; Forming a gate insulating film on a surface of the silicon pillar including the hole and an insulating film; Depositing a doped polysilicon film on the gate insulating film to completely fill the hole; Etching the doped polysilicon layer to expose a portion of the gate insulating layer on the silicon pillar to form an outer gate outside the silicon pillar while forming an inner gate inside the hole of the silicon pillar; Forming a drain region through ion implantation in a horizontal plane of the silicon pillar; Forming an interlayer insulating film on the resultant product; Forming a first metal interconnection electrically connecting the inner gate and the outer gate to the interlayer insulating layer, a second metal interconnection contacting the source region, and a third metal interconnection contacting the drain region; A method of manufacturing a vertical transistor having a multi-channel transistor, characterized in that. The method of claim 6, wherein the forming of the silicon pillar having a hole in the central portion, Growing a single crystal silicon layer on the exposed substrate region and adjacent insulating film portions in a selective epitaxial growth process; And And patterning the single crystal silicon layer so as to have a hole in a central portion thereof while having a predetermined shape. The method of claim 7, wherein the silicon pillar is patterned to have a cylindrical or hexahedral shape as a whole. 8. The vertical structure of claim 7, further comprising performing rapid thermal annealing (RTA) on the silicon substrate before growing the single crystal silicon layer by the selective epitaxial growth process. Method for manufacturing a transistor. The method of claim 6, wherein the forming of the silicon pillar having a hole in the central portion, Depositing a polycrystalline silicon layer on the exposed substrate region and the insulating film by a deposition process; And And patterning the polycrystalline silicon layer so as to have a hole at a central portion thereof while having a predetermined shape. The method of claim 6, wherein the forming of the inner gate and the outer gate, Polishing or etching back the doped polysilicon layer to expose a portion of the gate insulating layer on the silicon pillar; And And patterning the doped polysilicon film remaining on the outside of the silicon pillar. The method of claim 6, wherein the forming of the inner gate and the outer gate, The doped polysilicon layer is etched by a Reaction Ion Etching (RIE) process to form an inner gate inside the hole, and at the same time, an outer gate is formed on the outer side of the silicon pillar in the form of a spacer, the vertical structure having a multi-channel Method for manufacturing a transistor. The method of claim 6, wherein the forming of the first, second and third metal wires comprises: A second contact hole for etching the interlayer insulating film, the interlayer insulating film, the gate insulating film and the insulating film, and the interlayer insulating film and the gate insulating film to expose first contact holes and the source region exposing the inner and outer gates, respectively. Forming a third contact hole exposing the drain region; Depositing a metal film on the interlayer insulating film to fill the contact holes; And And patterning the metal film.