KR100386452B1 - Method for manufacturing semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, wherein a drain region and an impurity region are simultaneously formed in a first region (region in which a vertical transistor is to be formed) and a second region (region in which a horizontal transistor is to be formed) of a semiconductor substrate. The first insulating film, the second insulating film, and the third insulating film are sequentially formed on the substrate, and the first insulating film, the second insulating film, and the third insulating film are sequentially formed and etched to form contact holes in the first region. Then, the doped polysilicon is embedded to form a channel. In addition, a doped polysilicon film is formed on the third insulating layer and patterned to form a source region connected to the drain region through a channel in the first region, and then the third to first insulating layers of the first region are patterned and formed. 2 Remove the insulation film. Then, an oxide film is formed on the entire structure, doped polysilicon is deposited and patterned to form a vertical double gate electrode and a gate insulating film in the first region, and a horizontal gate electrode and a gate insulating film in the second region. . Therefore, it is possible to simultaneously fabricate a vertical double gate structure transistor and a horizontal transistor in one semiconductor substrate, satisfy the gate electrode length of the line width set in each transistor, and add a capping film to the vertical double gate electrode to provide a source / It is possible to insulate between the drain electrodes.

Description

Method for manufacturing semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a vertical double gate structure transistor and a horizontal transistor.

As semiconductor devices have been highly integrated, reductions in device size and line width have become inevitable. Accordingly, the technology for implementing fine line widths has become a key technology in the fabrication of semiconductor devices.

In general, it is difficult to pattern the gate electrode in the manufacturing process of the micro device having the length of the gate electrode of less than 10nm. In recent years, with the high integration of semiconductor devices, vertical devices in which the thickness of a thin film becomes the length of a gate electrode have emerged. Accordingly, a transistor having a double gate electrode capable of reducing the punch failure caused by the drain induced barrier lowering (DIBL) shown in the short channel and doubling the current has attracted much attention. This is because each channel is formed under two gate electrodes in one transistor, so that the current is twice as large as the actual transistor width.

However, such a transistor having a vertical double gate structure has a problem in designing a gate electrode of another transistor (for example, a horizontal transistor) in a circuit having various devices because the thickness of the film becomes the length and channel of the gate electrode. In addition, it was very difficult to insulate between the gate electrode having the vertical structure and the source / drain regions.

In order to solve the problems of the prior art as described above, a vertical double gate structure transistor and a horizontal transistor can be simultaneously manufactured on a single semiconductor substrate, and the gate electrode length of the line width set in each transistor can be satisfied. The present invention provides a method of manufacturing a semiconductor device capable of insulating the source / drain electrodes by adding a capping film to the vertical double gate electrode.

1 to 11 are process flowcharts of a semiconductor device having a vertical double gate structure transistor and a horizontal transistor according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

10 semiconductor substrate 12 first conductive layer

14 impurity region 16 first insulating film

18: second insulating film 20: third insulating film

22: contact hole 24 ': channel

26: second conductive layer 28: capping film

30a, 30b: gate insulating film 32: gate conductor film

32a: vertical double gate electrode 32b: horizontal gate electrode

34 interlayer insulating film 36 contact electrode

A: transistor area of vertical double gate structure

B: horizontal transistor region

In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device including a transistor having a vertical double gate structure and a horizontal transistor, wherein the first conductive layer and the impurity region are respectively formed in the first region and the second region of the semiconductor substrate. Simultaneously forming, sequentially forming a first insulating film, a second insulating film, and a third insulating film on the substrate and etching the same to form contact holes in the first region, and then filling a conductor to form a channel; Forming and patterning a conductive film on the third insulating film to form a second conductive layer connected to the first conductive layer through a channel in the first region, and patterning the third to first insulating films of the first region. And removing the second insulating film, forming an insulating thin film on the entire surface of the structure, depositing and patterning a conductive film, and forming a vertical double gate electrode and a gate in the first region. And simultaneously forming a smoke screen and forming a horizontal gate electrode and the gate insulating film in the second region.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 to 11 are process flowcharts of a semiconductor device having a vertical double gate structure transistor and a horizontal transistor according to an embodiment of the present invention. In these drawings, reference numeral A denotes a first region where a vertical double gate structure transistor is to be formed in a semiconductor substrate, and B denotes a second region where a horizontal transistor is to be formed.

As shown in FIG. 1, a device isolation process is performed on a silicon substrate as a semiconductor substrate 10 to form a device isolation film (not shown), and an ion implantation process using a dopant is used to form the first region A in the first region A. FIG. The impurity region 14 is formed in the conductive layer 12 and the second region B. In this case, since the first conductive layer 12 is a region to be a source of the vertical transistor, doping may be increased through an ion implantation process using a separate mask. The impurity region 14 is a portion to be a source / drain of the horizontal transistor.

The first insulating film 16 / the second insulating film 18 / the third insulating film 20 are sequentially formed on the substrate. In this case, the first insulating layer 16 and the third insulating layer 20 are formed of a material having an etching selectivity with respect to the second insulating layer 18. For example, when the second insulating film 18 is an oxide film, the first insulating film 16 and the third insulating film 20 are nitride films.

Next, as shown in FIGS. 2 and 3, an etching process using a mask defining a position at which a channel region of the transistor having a vertical double gate structure is to be formed is performed to stack the third insulating film 20 and the second insulating film ( 18), the first insulating film 16 is etched. As a result, contact holes (not shown) are formed in the insulating layers 20, 18, and 16 of the first region A. FIG. Then, the doped polysilicon 24 is deposited on the insulating layers on which the contact holes are formed to fill the contact holes.

Then, as shown in FIG. 4, chemical mechanical polishing (CMP) is performed to grind the doped polysilicon 24, but proceeds until the third insulating layer 20 is exposed. As a result, the doped polysilicon embedded in the contact hole becomes the channel 24 'of the transistor of the vertical double gate structure.

The present invention may perform an additional in-situ doping process in the channel 24 'to vary the doping concentrations of polysilicon in the LDD region adjacent to the source 12 and the drain to be subsequently formed and polysilicon in the other channel region.

Subsequently, as shown in FIG. 5, a doped polysilicon is formed as a conductor layer on the third insulating layer 20 and patterned to form the first conductive layer 12 through the channel 24 ′ in the first region A. FIG. ) To form a second conductive layer 26. In this case, the second conductive layer 26 is used as a drain in the transistor of the vertical double gate structure.

6, a capping film 28 made of an insulating material (for example, a nitride film) is formed on the entire structure as described above.

As shown in FIG. 7, the etching process using the drain mask of the transistor having the vertical double gate structure is performed to pattern the capping films 28 to 16 of the first region A together. , 20 ', 18', 16 '). At this time, the second region B in which the horizontal transistor is to be formed removes all layers so that the active region of the substrate is exposed. The patterned capping layer 28 'is used to increase the insulating property between the drain / source region and the double gate electrode to be formed later.

Then, as shown in FIG. 8, only the patterned second insulating layer 18 ′ is removed by wet etching.

Next, as shown in FIG. 9, an oxidation process is performed to form an oxide film 30 on the entire surface of the structure and to deposit doped polysilicon as the conductor film 32 thereon.

As shown in FIG. 10, the etch process using the vertical and horizontal gate masks is performed to pattern the doped polysilicon 32 and the oxide layer 30 to form a vertical double gate electrode in the first region A. FIG. 32a and the gate insulating film 30a are formed. At the same time, the horizontal gate electrode 32b and the gate insulating film 30b are formed in the second region B. FIG. In this case, the doped polysilicon layer 32 is etched until the drain side gate insulating layer 30a of the vertical transistor is exposed during the gate electrode manufacturing process, and the left and right sides of the structure pattern in the first region A are separated. The vertical double gate electrode 32a is formed.

As shown in FIG. 11, after the interlayer insulating film 34 is formed on the entire surface of the substrate on which the vertical and horizontal transistors are formed as described above, and the surface thereof is planarized by the CMP process, an etching process using a contact mask is performed to interlayer. Contact holes are formed in the insulating film 34. A contact such as a metal is embedded in the contact hole to form the gate electrode contact and the source / drain contact 36. Here, the gate contact of the transistor of the vertical double gate structure is not seen by the vertical cross section of the semiconductor device.

As described above, the present invention can simultaneously manufacture a transistor having a vertical double gate structure and a horizontal transistor on one semiconductor substrate, and satisfy a gate electrode length having a line width set in each transistor. Capping layers may be added to insulate between the source and drain electrodes.

Therefore, the present invention can overcome the limitations of the vertical transistor while maintaining the advantages of the vertical double gate transistor by forming the vertical double gate transistor at the same time as the horizontal transistor.

Claims (4)

In the method of manufacturing a semiconductor device including a transistor having a vertical double gate structure and a horizontal transistor, Forming a first conductive layer and an impurity region in the first region and the second region of the semiconductor substrate, respectively; Forming a contact hole in the first region by sequentially forming a first insulating film, a second insulating film, and a third insulating film on the substrate and etching the same to form a contact hole in the first region; Forming a conductive layer on the third insulating layer and patterning the conductive layer to form a second conductive layer connected to the first conductive layer through the channel in the first region; Patterning the third to first insulating films of the first region and removing the second insulating film; And Forming an insulating thin film on the entire surface of the structure, depositing and patterning a conductor film to form a vertical double gate electrode and a gate insulating film in a first region, and simultaneously forming a horizontal gate electrode and a gate insulating film in a second region. The manufacturing method of the semiconductor device characterized by including the. The method of claim 1, further comprising: stacking a capping film made of an insulating material on the entire surface of the structure after forming the second conductive layer, and then patterning the capping film and the first insulating film in the first region together. A method of manufacturing a semiconductor device. The channel conductor of claim 1, wherein the channel conductor is formed of doped polysilicon, and the polysilicon of the LDD region adjacent to the first conductive layer and the second conductive layer and the other channel region are doped by an in-situ doping process. A method of manufacturing a semiconductor device, characterized in that the concentration is adjusted differently. The method of claim 1, wherein during the patterning of the gate electrode conductive film, the conductive film is etched until the gate insulating film of the second conductive layer is exposed to form vertical double gate electrodes separated on left and right sides of the structure of the first region. A method for manufacturing a semiconductor device.