KR20030000962A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR20030000962A KR20030000962A KR1020010037238A KR20010037238A KR20030000962A KR 20030000962 A KR20030000962 A KR 20030000962A KR 1020010037238 A KR1020010037238 A KR 1020010037238A KR 20010037238 A KR20010037238 A KR 20010037238A KR 20030000962 A KR20030000962 A KR 20030000962A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000012535 impurity Substances 0.000 claims abstract description 6
- 239000010408 film Substances 0.000 claims description 53
- 239000000758 substrate Substances 0.000 claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 229920005591 polysilicon Polymers 0.000 claims description 11
- 238000000059 patterning Methods 0.000 claims description 8
- 239000004020 conductor Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 239000010409 thin film Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 238000011065 in-situ storage Methods 0.000 claims description 2
- 239000011810 insulating material Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 25
- 239000011229 interlayer Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000779 smoke Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체 장치의 제조방법에 관한 것으로서, 특히 수직형 더블 게이트구조의 트랜지스터 및 수평형 트랜지스터를 갖는 반도체장치의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a vertical double gate structure transistor and a horizontal transistor.
반도체장치가 고집적화 됨에 따라 소자의 크기 및 선폭 등의 감소는 필연적인 사항이 되었으며, 이에 따라 미세선폭의 구현 기술은 반도체장치 제작에 핵심 기술이 되고 있다.As semiconductor devices have been highly integrated, reductions in device size and line width have become inevitable. Accordingly, the technology for implementing fine line widths has become a key technology in the fabrication of semiconductor devices.
일반적으로, 10㎚이하의 게이트전극의 길이를 갖는 미세 소자의 제조 공정시 게이트전극을 패터닝하는데 어려움이 있다. 최근에는 반도체 소자의 고집적화에 따라 박막의 두께가 게이트전극의 길이가 되는 수직형 소자가 출현되었다. 이에, 쇼트 채널에서 나타난 DIBL(Drain Induced Barrier Lowering)에 의한 펀치 불량을 줄이고 전류를 2배로 늘릴 수 있는 더블 게이트전극을 갖는 트랜지스터가 많은 주목을 받고 있다. 이는 하나의 트랜지스터에 있는 2개의 게이트전극 아래서 각각의 채널이 형성되기 때문에 실제 트랜지스터 폭의 2배가 되어 2배의 전류가 흐르게 되는 것이다.In general, it is difficult to pattern the gate electrode in the manufacturing process of the micro device having the length of the gate electrode of less than 10nm. In recent years, with the high integration of semiconductor devices, vertical devices in which the thickness of a thin film becomes the length of a gate electrode have emerged. Accordingly, a transistor having a double gate electrode capable of reducing the punch failure caused by the drain induced barrier lowering (DIBL) shown in the short channel and doubling the current has attracted much attention. This is because each channel is formed under two gate electrodes in one transistor, so that the current is twice as large as the actual transistor width.
그러나, 이러한 수직형 더블 게이트 구조의 트랜지스터는 막의 두께가 게이트 전극의 길이 및 채널이 되므로 다양한 소자를 갖는 회로에서 다른 트랜지스터(예를 들면 수평형 트랜지스터)의 게이트 전극을 설계하는데 문제점이 있었다. 또한, 수직 구조를 갖는 게이트전극과 소오스/드레인 영역사이를 절연하기가 매우 어려웠다.However, such a transistor having a vertical double gate structure has a problem in designing a gate electrode of another transistor (for example, a horizontal transistor) in a circuit having various devices because the thickness of the film becomes the length and channel of the gate electrode. In addition, it was very difficult to insulate between the gate electrode having the vertical structure and the source / drain regions.
본 발명의 목적은 상기와 같은 종래 기술의 문제점을 해결하기 위하여 하나의 반도체 기판에 수직형 더블 게이트구조의 트랜지스터와 수평형 트랜지스터를 동시에 제작할 수 있으며 각각의 트랜지스터에서 설정된 선폭의 게이트전극 길이를 만족시킬 수 있으며 수직형 더블 게이트전극에 캐핑막을 추가하여 소오스/드레인 전극사이를 절연할 수 있는 반도체 장치의 제조방법을 제공하는데 있다.In order to solve the problems of the prior art as described above, a vertical double gate structure transistor and a horizontal transistor can be simultaneously manufactured on a single semiconductor substrate, and the gate electrode length of the line width set in each transistor can be satisfied. The present invention provides a method of manufacturing a semiconductor device capable of insulating the source / drain electrodes by adding a capping film to the vertical double gate electrode.
도 1 내지 도 11은 본 발명의 일 실시예에 따른 수직형 더블 게이트구조의 트랜지스터 및 수평형 트랜지스터를 갖는 반도체장치의 공정 순서도.1 to 11 are process flowcharts of a semiconductor device having a vertical double gate structure transistor and a horizontal transistor according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
10 : 반도체 기판 12 : 제 1도전층10 semiconductor substrate 12 first conductive layer
14 : 불순물 영역 16 : 제 1절연막14 impurity region 16 first insulating film
18 : 제 2절연막 20 : 제 3절연막18: second insulating film 20: third insulating film
22 : 콘택홀 24' : 채널22: contact hole 24 ': channel
26 : 제 2도전층 28 : 캐핑막26: second conductive layer 28: capping film
30a, 30b : 게이트절연막 32 : 게이트용 도전체막30a, 30b: gate insulating film 32: gate conductor film
32a : 수직형 더블 게이트전극 32b : 수평형 게이트전극32a: vertical double gate electrode 32b: horizontal gate electrode
34 : 층간 절연막 36 : 콘택전극34 interlayer insulating film 36 contact electrode
A : 수직형 더블 게이트구조의 트랜지스터 영역A: transistor area of vertical double gate structure
B : 수평형 트랜지스터 영역B: horizontal transistor region
상기 목적을 달성하기 위하여 본 발명은 수직형 더블 게이트구조의 트랜지스터 및 수평형 트랜지스터를 포함한 반도체장치의 제조방법에 있어서, 반도체 기판의 제 1영역과 제 2영역내에 각각 제 1도전층과 불순물 영역을 동시에 형성하는 단계와, 기판상부에 제 1절연막/제 2절연막/제 3절연막을 순차 형성하고 이들을 식각하여 제 1영역에 콘택홀을 형성한 후에, 도전체를 매립하여 채널을 형성하는 단계와, 제 3절연막 상부에 도전체막을 형성하고 이를 패터닝하여 제 1영역에 채널을 통해 제 1도전층과 연결되는 제 2도전층을 형성하는 단계와, 제 1영역의 제 3절연막 내지 제 1절연막을 패터닝하고 제 2절연막을 제거하는 단계와, 구조물 전면에 절연 박막을 형성하고 도전체막을 증착하고 이를 패터닝하여 제 1영역에 수직형 더블 게이트전극 및 게이트절연막을 형성함과 동시에 제 2영역에 수평형 게이트전극 및 게이트절연막을 형성하는 단계를 포함한다.In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device including a transistor having a vertical double gate structure and a horizontal transistor, wherein the first conductive layer and the impurity region are respectively formed in the first region and the second region of the semiconductor substrate. Simultaneously forming, sequentially forming a first insulating film, a second insulating film, and a third insulating film on the substrate and etching the same to form contact holes in the first region, and then filling a conductor to form a channel; Forming and patterning a conductive film on the third insulating film to form a second conductive layer connected to the first conductive layer through a channel in the first region, and patterning the third to first insulating films of the first region. And removing the second insulating film, forming an insulating thin film on the entire surface of the structure, depositing and patterning a conductive film, and forming a vertical double gate electrode and a gate in the first region. And simultaneously forming a smoke screen and forming a horizontal gate electrode and the gate insulating film in the second region.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세하게 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 11은 본 발명의 일 실시예에 따른 수직형 더블 게이트구조의 트랜지스터 및 수평형 트랜지스터를 갖는 반도체장치의 공정 순서도이다. 이들 도면에서 도면 부호 A는 반도체 기판에서 수직형 더블 게이트구조의 트랜지스터가 형성될 제 1영역이고 B는 수평형 트랜지스터가 형성될 제 2영역이다.1 to 11 are process flowcharts of a semiconductor device having a vertical double gate structure transistor and a horizontal transistor according to an embodiment of the present invention. In these drawings, reference numeral A denotes a first region where a vertical double gate structure transistor is to be formed in a semiconductor substrate, and B denotes a second region where a horizontal transistor is to be formed.
도 1에 도시된 바와 같이, 반도체 기판(10)으로서 실리콘 기판에 소자분리 공정을 실시하여 소자분리막(미도시함)을 형성하고, 도펀트를 이용한 이온 주입공정으로 제 1영역(A)에 제 1도전층(12)과 제 2영역(B)에 불순물 영역(14)을 형성한다. 이때, 제 1도전층(12)은 수직형 트랜지스터의 소오스가 될 영역이므로 별도의 마스크를 이용한 이온 주입공정을 통해 도핑을 높일 수 있다. 그리고, 불순물 영역(14)은 수평형 트랜지스터의 소오스/드레인이 될 부분이다.As shown in FIG. 1, a device isolation process is performed on a silicon substrate as a semiconductor substrate 10 to form a device isolation film (not shown), and an ion implantation process using a dopant is used to form the first region A in the first region A. FIG. The impurity region 14 is formed in the conductive layer 12 and the second region B. In this case, since the first conductive layer 12 is a region to be a source of the vertical transistor, doping may be increased through an ion implantation process using a separate mask. The impurity region 14 is a portion to be a source / drain of the horizontal transistor.
그리고 기판 상부에 제 1절연막(16)/제 2절연막(18)/제 3절연막(20)을 순차 형성한다. 이때, 제 1절연막(16)과 제 3절연막(20)은 제 2절연막(18)에 대해 식각 선택성이 있는 물질로 형성한다. 예를 들면, 제 2절연막(18)이 산화막일 경우 제 1절연막(16)과 제 3절연막(20)은 질화막이다.The first insulating film 16 / the second insulating film 18 / the third insulating film 20 are sequentially formed on the substrate. In this case, the first insulating layer 16 and the third insulating layer 20 are formed of a material having an etching selectivity with respect to the second insulating layer 18. For example, when the second insulating film 18 is an oxide film, the first insulating film 16 and the third insulating film 20 are nitride films.
그 다음 도 2 및 도 3에 도시된 바와 같이, 수직형 더블 게이트구조의 트랜지스터의 채널 영역이 형성될 위치를 정의한 마스크를 이용한 식각 공정을 진행하여 적층된 제 3절연막(20), 제 2절연막(18), 제 1절연막(16)을 식각한다. 이로 인해, 제 1영역(A)의 절연막들(20, 18, 16)에 콘택홀(미도시함)이 형성된다. 그리고 콘택홀이 형성된 절연막들에 도전체막으로서 도프트 폴리실리콘(24)을 증착하여 콘택홀을 매립한다.Next, as shown in FIGS. 2 and 3, an etching process using a mask defining a position at which a channel region of the transistor having a vertical double gate structure is to be formed is performed to stack the third insulating film 20 and the second insulating film ( 18), the first insulating film 16 is etched. As a result, contact holes (not shown) are formed in the insulating layers 20, 18, and 16 of the first region A. FIG. Then, the doped polysilicon 24 is deposited on the insulating layers on which the contact holes are formed to fill the contact holes.
그런 다음 도 4에 도시된 바와 같이, CMP(Chemical Mechanical Polishing)을 진행하여 도프트 폴리실리콘(24)을 연마하되, 제 3절연막(20)이 드러날 때까지 진행한다. 이로 인해, 콘택홀내에 매립된 도프트 폴리실리콘이 수직형 더블 게이트구조의 트랜지스터의 채널(24')이 된다.Then, as shown in FIG. 4, chemical mechanical polishing (CMP) is performed to grind the doped polysilicon 24, but proceeds until the third insulating layer 20 is exposed. As a result, the doped polysilicon embedded in the contact hole becomes the channel 24 'of the transistor of the vertical double gate structure.
본 발명은 채널(24')에 추가 인시튜 도핑 공정을 실시하여 소오스(12)와 이후 형성될 드레인에 인접한 LDD 영역의 폴리실리콘과 그 외 채널 영역의 폴리실리콘의 도핑 농도를 다르게 조절할 수도 있다.The present invention may perform an additional in-situ doping process in the channel 24 'to vary the doping concentrations of polysilicon in the LDD region adjacent to the source 12 and the drain to be subsequently formed and polysilicon in the other channel region.
이어서 도 5에 도시된 바와 같이, 제 3절연막(20) 상부에 도전체막으로서 도프트 폴리실리콘을 형성하고 이를 패터닝하여 제 1영역(A)에 채널(24')을 통해 제 1도전층(12)과 연결되는 제 2도전층(26)을 형성한다. 이때, 제 2도전층(26)은 수직형 더블 게이트 구조의 트랜지스터에서 드레인으로 사용된다.Subsequently, as shown in FIG. 5, a doped polysilicon is formed as a conductor layer on the third insulating layer 20 and patterned to form the first conductive layer 12 through the channel 24 ′ in the first region A. FIG. ) To form a second conductive layer 26. In this case, the second conductive layer 26 is used as a drain in the transistor of the vertical double gate structure.
그 다음 도 6에 도시된 바와 같이, 상기와 같은 구조물 전면에 절연물질(예를 들어 질화막)로 이루어진 캐핑막(28)을 형성한다.6, a capping film 28 made of an insulating material (for example, a nitride film) is formed on the entire structure as described above.
그리고 도 7에 도시된 바와 같이, 수직 더블 게이트구조의 트랜지스터의 드레인 마스크를 이용한 식각 공정을 진행하여 제 1영역(A)의 캐핑막(28) 내지 제 1절연막(16)을 함께 패터닝(28', 20', 18', 16')한다. 이때, 수평형 트랜지스터가 형성될 제 2영역(B)은 기판의 활성 영역이 드러나도록 모든 층을 제거한다. 여기서 패터닝된 캐핑막(28')은 드레인/소오스 영역과 이후 형성될 더블 게이트전극 사이의 절연 특성을 높이기 위해 사용된다.As shown in FIG. 7, the etching process using the drain mask of the transistor having the vertical double gate structure is performed to pattern the capping films 28 to 16 of the first region A together. , 20 ', 18', 16 '). At this time, the second region B in which the horizontal transistor is to be formed removes all layers so that the active region of the substrate is exposed. The patterned capping layer 28 'is used to increase the insulating property between the drain / source region and the double gate electrode to be formed later.
그 다음 도 8에 도시된 바와 같이, 패터닝된 제 2절연막(18')만을 습식 식각을 통해 제거한다.Then, as shown in FIG. 8, only the patterned second insulating layer 18 ′ is removed by wet etching.
이어서 도 9에 도시된 바와 같이, 산화 공정을 진행하여 구조물 전면에 산화막(30)을 형성하고 그 위에 도전체막(32)으로서 도프트 폴리실리콘을 증착한다.Next, as shown in FIG. 9, an oxidation process is performed to form an oxide film 30 on the entire surface of the structure and to deposit doped polysilicon as the conductor film 32 thereon.
그리고 도 10에 도시된 바와 같이, 수직형 및 수평형 게이트 마스크를 이용한 식각 공정을 진행하여 도프트 폴리실리콘(32)과 산화막(30)을 패터닝하여 제 1영역(A)에 수직형 더블 게이트전극(32a) 및 게이트절연막(30a)을 형성한다. 이와 동시에, 제 2영역(B)에 수평형 게이트전극(32b) 및 게이트절연막(30b)을 형성한다. 이때 게이트전극 제조 공정시 수직형 트랜지스터의 드레인측 게이트절연막(30a)이 노출될 때까지 도프트 폴리실리콘막(32)을 식각하여 제 1영역(A)에 있는 구조물 패턴의 좌/우측에 분리된 수직형 더블 게이트전극(32a)을 형성한다.As shown in FIG. 10, the etch process using the vertical and horizontal gate masks is performed to pattern the doped polysilicon 32 and the oxide layer 30 to form a vertical double gate electrode in the first region A. FIG. 32a and the gate insulating film 30a are formed. At the same time, the horizontal gate electrode 32b and the gate insulating film 30b are formed in the second region B. FIG. In this case, the doped polysilicon layer 32 is etched until the drain side gate insulating layer 30a of the vertical transistor is exposed during the gate electrode manufacturing process, and the left and right sides of the structure pattern in the first region A are separated. The vertical double gate electrode 32a is formed.
도 11에 도시된 바와 같이, 상기와 같이 수직형 및 수평형 트랜지스터가 형성된 기판 전면에 층간 절연막(34)을 형성하고 그 표면을 CMP 공정으로 평탄화한 후에, 콘택 마스크를 이용한 식각 공정을 진행하여 층간 절연막(34)에 콘택홀을 형성한다. 그리고 콘택홀에 금속 등의 도전체를 매립하여 게이트전극의 콘택 및 소오스/드레인의 콘택(36)을 형성한다. 여기서, 반도체 장치의 수직 단면에 의해 수직형 더블 게이트 구조의 트랜지스터의 게이트 콘택은 보이지 않는다.As shown in FIG. 11, after the interlayer insulating film 34 is formed on the entire surface of the substrate on which the vertical and horizontal transistors are formed as described above, and the surface thereof is planarized by the CMP process, an etching process using a contact mask is performed to interlayer. Contact holes are formed in the insulating film 34. A contact such as a metal is embedded in the contact hole to form the gate electrode contact and the source / drain contact 36. Here, the gate contact of the transistor of the vertical double gate structure is not seen by the vertical cross section of the semiconductor device.
상기한 바와 같이, 본 발명은 하나의 반도체 기판에 수직형 더블 게이트구조의 트랜지스터와 수평형 트랜지스터를 동시에 제작할 수 있으며 각각의 트랜지스터에서 설정된 선폭의 게이트전극 길이를 만족시킬 수 있으며 수직형 더블 게이트전극에 캐핑막을 추가하여 소오스/드레인 전극사이를 절연할 수 있다.As described above, the present invention can simultaneously manufacture a transistor having a vertical double gate structure and a horizontal transistor on one semiconductor substrate, and satisfy a gate electrode length having a line width set in each transistor. Capping layers may be added to insulate between the source and drain electrodes.
그러므로, 본 발명은 고집적 반도체장치에 있어서, 수직형 더블 게이트 트랜지스터를 수평형 트랜지스터도 동시에 형성함에 따라 수직 더블 게이트 트랜지스터의 장점을 그대로 가지면서도 수직형 트랜지스터가 가지는 한계를 극복할 수 있다.Therefore, the present invention can overcome the limitations of the vertical transistor while maintaining the advantages of the vertical double gate transistor by forming the vertical double gate transistor at the same time as the horizontal transistor.
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| KR100787193B1 (en) * | 2006-05-23 | 2007-12-21 | 한국단자공업 주식회사 | Device for separating PCB unit in process of manufacturing PCB module |
| KR100929335B1 (en) * | 2001-09-10 | 2009-12-03 | 에이저 시스템즈 가디언 코포레이션 | A vertical replacement-gate junction field-effect transistor |
| US7977736B2 (en) | 2006-02-23 | 2011-07-12 | Samsung Electronics Co., Ltd. | Vertical channel transistors and memory devices including vertical channel transistors |
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| KR100927400B1 (en) | 2007-09-11 | 2009-11-19 | 주식회사 하이닉스반도체 | Pillar pattern manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100929335B1 (en) * | 2001-09-10 | 2009-12-03 | 에이저 시스템즈 가디언 코포레이션 | A vertical replacement-gate junction field-effect transistor |
| KR100931816B1 (en) * | 2001-09-10 | 2009-12-14 | 에이저 시스템즈 가디언 코포레이션 | Vertical Alternating Gate Junction Field Effect Transistor |
| US7977736B2 (en) | 2006-02-23 | 2011-07-12 | Samsung Electronics Co., Ltd. | Vertical channel transistors and memory devices including vertical channel transistors |
| KR100787193B1 (en) * | 2006-05-23 | 2007-12-21 | 한국단자공업 주식회사 | Device for separating PCB unit in process of manufacturing PCB module |
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