KR100880377B1 - Verticalally integrated nano-shell field effect transistor and fusion memory device, and the method of manufacturing the same - Google Patents

Abstract

A vertical type nano shell field effect transistor and manufacturing method thereof are provided to manufacture low power device capable of controlling threshold voltage by supplying each different voltage to independent two gates. A vertical type nano shell field effect transistor includes a second gate(208) with a first vertical pillar shape. A side part of the second gate is surrounded by a channel(206) of a second vertical pillar shape. A side part of the channel is surrounded by a first gate(202). A source(204) is connected to a bottom part of the channel. A drain(209) is connected to a top part of the channel, and is isolated with the source. The first gate and the second gate are formed by material in which work functions is different.

Description

VERTICALALLY INTEGRATED NANO-SHELL FIELD EFFECT TRANSISTOR AND FUSION MEMORY DEVICE, AND THE METHOD OF MANUFACTURING THE SAME

The present invention relates to field effect transistors and fusion memory devices. More specifically, the present invention relates to a field effect transistor having a vertical nanoshell structure, a fused memory device having a nonvolatile flash memory characteristic and a capacitorless DRAM characteristic, and a method of manufacturing the same.

With the demand of the semiconductor market to reduce the production cost of electronic products and to increase the density due to the emergence of ultra-high integrated circuits, continuous scaling down of the device is absolutely necessary.

1 is a view showing a conventional planar field effect transistor. Referring to FIG. 1, as the physical channel size of the planar device size and the length of the device channel 101 representing the device size are reduced, the phenomenon of seriously degrading the performance of a device called a short channel effect is reduced. As a result, simple device size reduction has reached its limit.

To overcome these limitations, two approaches can be considered. The first is to reduce the size of the device while maintaining or reducing the short-channel effect, and the second is to apply a structure to the device to increase the density. will be. The first approach is to use multiple gates rather than single gates or silicon on insulator (SOI) wafers to increase the gate controllability of the gates to body potential. A device structure having an ultra thin body has been studied, and the short channel effect can be effectively reduced. In the second method, the degree of integration can be dramatically improved by using a three-dimensional vertical structure instead of the conventional planar structure.

The present invention includes a second gate that is independently operable with a first gate of a gate-all-around that surrounds a vertical channel formed thin body due to solid phase crystallization. Accordingly, an object of the present invention is to provide a field effect transistor having a three-dimensional double gate structure formed around a nanoshell-shaped channel.

In addition, an object of the present invention is to provide a low power device capable of adjusting the threshold voltage by using two gates having different work functions or applying different voltages to two independent gates.

Another object of the present invention is to provide a fused memory device having both a nonvolatile memory characteristic capable of retaining stored data and a capacitorless DRAM even when a power supply is interrupted in one transistor.

Field effect transistor according to the present invention for achieving the above object, the first vertical columnar second gate, the second vertical columnar channel surrounding the side of the second gate, the channel surrounding the side A first gate, a source connected to the channel, and a drain connected to the channel and spaced apart from the source.

Here, preferably, further comprising a semiconductor substrate formed below the channel, the source is formed in the semiconductor substrate, the drain is formed surrounding the outer peripheral portion of the upper portion of the channel.

Here, preferably, further comprising a semiconductor substrate formed below the channel, wherein the source is connected to a portion of the outer peripheral portion of the upper portion of the channel, the drain is connected to another portion of the outer peripheral portion of the upper portion of the channel Is formed.

Here, preferably, the channel is insulated by the first gate and the second gate and an insulating film, and the insulating film is any one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a high-k metal oxide film. It consists of one substance.

Here, preferably, the first gate and the second gate are formed of a material having a different work function.

Here, preferably, the semiconductor substrate is made of one of silicon, silicon germanium, strained silicon, and tensile silicon germanium.

Here, preferably, said first and / or second vertical pillars are cylindrical or polygonal pillars.

The fusion memory device according to the present invention further includes a floating gate formed between the second gate and the channel in addition to the field effect transistor according to claim 1 and surrounding the side of the second gate.

Here, preferably, the floating gate may include a polysilicon layer, a nitride layer forming a silicon oxide nitride oxide (SONOS) or a metal nitride oxide silicon (MNOS) structure, an amorphous silicon layer, a metal oxide layer, a silicon nitride layer, One or more than one of the silicon nanocrystal layer, the metal nanocrystal layer, or the metal oxide nanocrystal layer is mixed.

Here, preferably, the floating gate is insulated by the second gate, the channel and the insulating film, and the insulating film is made of any one material of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a high dielectric constant metal oxide film.

In the method of manufacturing a field effect transistor according to the present invention, (a) implanting an impurity into a semiconductor substrate to form a source, (b) forming a first interlayer insulating film, a first gate, a second interlayer insulating film on the semiconductor substrate Stacking sequentially; (c) forming holes in the vertical direction through the first interlayer insulating film, the first gate, and the second interlayer insulating film; and (d) forming a first gate insulating film in the holes. Exposing the source through an etch back process; (e) forming a nanoshell-shaped channel on the exposed source and the first gate insulating film, and (f) a second gate insulating film on the channel. Forming a second gate in the hole, and (h) injecting impurities into the nanoshell channel to form a drain.

Here, preferably, the channel is formed by enhancing the size of the silicon crystal, such as annealing the deposited amorphous silicon or polysilicon at a high temperature or using a laser.

In the method of manufacturing a fusion memory device according to the present invention, in addition to the above-described method of manufacturing a field effect transistor, between (f) and (g), (i) a floating gate is formed on the second gate insulating film. And forming a control insulating film on the floating gate, wherein the second gate insulating film is a tunneling insulating film.

In the method of manufacturing a field effect transistor according to the present invention, (a) sequentially stacking a first interlayer insulating film, a first gate, and a second interlayer insulating film on a semiconductor substrate, (b) the first interlayer insulating film, the first Forming a first gate, a vertical hole through the second interlayer insulating film, (c) forming a first gate insulating film in the hole, and exposing the semiconductor substrate through an etch back process, (d ) Forming a nanoshell-shaped channel on the exposed semiconductor substrate and the first gate insulating film, (e) forming a second gate insulating film on the channel, (f) a second gate inside the hole Forming a, and (g) injecting impurities into the nanoshell channel to form a source and a drain.

Here, preferably, the channel is formed by enhancing the size of the silicon crystal, such as annealing the deposited amorphous silicon or polysilicon at a high temperature or using a laser.

In the method of manufacturing a fusion memory device according to the present invention, in addition to the above-described method of manufacturing a field effect transistor, between (e) and (f), (i) a floating gate is formed on the second gate insulating film. And (j) forming a control insulating film on the floating gate, wherein the second gate insulating film is a tunneling insulating film.

The method for driving the field effect transistor according to the present invention may be performed by applying the same voltage to each gate as if the first and second gates are tied to each other, or applying the same voltage to each of the first and second gates to implement a low power consumption transistor. Different gate voltages are applied.

In the driving method of a memory device having a field effect transistor as a unit cell according to the present invention, holes are accumulated or removed in the channel by using a floating body effect.

In the method of driving a memory device having a field effect transistor as a unit cell according to the present invention, holes are accumulated or evicted in the channel by using a gate induced drain leakage effect.

In the method of driving a memory device having a field effect transistor as a unit cell according to the present invention, in order to operate the memory device in a DRAM mode when a high speed operation of the memory is required, each of the gate, the source, and the drain of the unit cell is provided. Information is written or erased as a bias is applied to accumulate or eject holes in the channel.

In the method of driving a memory device having a fused memory device as a unit cell according to the present invention, in order to operate the memory device as a nonvolatile memory when a nonvolatile characteristic of the memory is required, the gate, source, and drain of the unit cell may be used. A bias is applied to each so that information is written or erased as electrons are injected or erased into the floating gate.

In the method of driving a memory device having a unit cell as a fusion memory device according to the present invention, the operation of the fusion memory device may be performed in a DRAM mode or a nonvolatile mode according to a required memory operation speed and power supply to the fused memory device. Switch between memory modes.

According to the present invention a second gate operable independently of the first gate of the gate-all-around, which encloses a vertical channel formed thin due to solid phase crystallization, is provided. A field effect transistor having a three-dimensional double gate structure formed around a nanoshell-shaped channel is provided. This vertical structure has the advantage of being highly integrated and having the advantage of being able to easily define the short gate length by the thickness of the deposited film, compared to defining the gate length using expensive lithography equipment in the planar structure. The ideal structure of the gate surrounding the inside and outside of the channel effectively reduces the short channel effect.

In addition, a low power device capable of adjusting a threshold voltage is provided by using two gates having different work functions or applying different voltages to two independent gates.

In addition, a fusion memory device having both a nonvolatile memory characteristic and a capacitorless DRAM characteristic capable of retaining stored data even when power supply is interrupted in one transistor is provided.

Hereinafter, a field effect transistor and a fusion memory according to the present invention will be described in detail with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the drawings.

[First Embodiment]

2A to 2H are diagrams illustrating a field effect transistor having a vertical nanoshell structure according to a first embodiment of the present invention in order of manufacturing process. First, referring to FIG. 2G, which shows a cross-sectional view of the final structure, the field effect transistor according to the present invention includes a vertical columnar channel surrounding a side of the vertical columnar second gate 208 and the second gate 208. 206, a first gate 202 surrounding the side of the channel 206, a source 204 connected to the channel 206, a drain connected to the channel 206 and spaced apart from the source 204 ( 209). Here, the source 204 is formed below the channel 206, and the drain 209 is formed surrounding the outer periphery of the top of the channel 206.

Hereinafter, a structure of a field effect transistor and a method of manufacturing the same according to an embodiment of the present invention will be described in detail with reference to FIGS. 2A to 2G. Referring to FIG. 2A, a shallow source 204 is formed using a diffusion process or an implantation process prior to stacking the gate structure on the surface of the semiconductor substrate 200. The semiconductor substrate 200 refers to a general material, and may use a silicon substrate or silicon germanium, strained silicon, tensile silicon germanium, and insulating layer embedded silicon (SOI).

Referring to FIG. 2B, an oxide film as an interlayer dielectric 201 is stacked on a semiconductor substrate 200 on which a source 204 is formed, and a first gate 202 is stacked thereon, and an interlayer is again thereon. The insulating film 201 'is laminated. The interlayer insulating films 201 and 201 'may be formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a metal oxide film, or the like. The metal oxide film is preferably a high-k metal oxide film. The interlayer insulating film 201 serves to isolate the previously formed source 204 and the first gate 202. The field effect transistor according to the present invention has a vertical structure, and the deposition thickness of the material of the first gate 202 refers to a gate length.

Referring again to FIG. 2B, a hole 203 is formed in the above-described structure through a lithography process. The hole 203 formed to form a channel vertically is formed to the depth of the semiconductor substrate 200 through anisotropic dry etching, and the shape of the hole 203 is not limited to the cylinder as shown in the drawing, It can be formed into a column or a polygonal column.

2C to 2G are cross-sectional views taken along the line i-i 'of FIG. 2B. 2C illustrates that the first gate insulating layer 205 is formed in the hole 203. The first gate insulating film 205 may be formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a metal oxide film having a high dielectric constant, or the like.

Next, as shown in FIG. 2D, the source 204 is exposed through an etch-back process using dry etching. Since the first gate insulating film 205 may be thinned or degraded through an etch back process, the first gate insulating film 205 may have a sufficient thickness so that the first gate 202 may be well isolated from the channel 206 to be formed later. It is desirable to form with.

Next, an amorphous silicon or polysilicon to be the channel 206 is deposited on the source 204 and the first gate insulating layer 205 of the semiconductor substrate 200 as shown in FIG. 2E, and the formed thin film is deposited. Solid phase crystallization forms a monocrystalline nanoshell-shaped polysilicon channel 206 in a desired region. Solid phase crystallization is an amorphous silicon deposited on a silicon substrate for a long time to anneal (annealing) at a temperature higher than 600 ℃ for a long time grows regular crystals amorphous silicon of irregular molecular structure is a polysilicon with a lot of regular crystals. Phase is a phenomenon that changes. In this case, if the polysilicon grain size is further improved through the control of temperature and time conditions, the polysilicon channel 206 having a single crystallized channel region may be obtained. In addition to the solid phase crystallization, the channel may be monocrystalline by improving the size of the crystal through a method of lowering the annealing temperature by further depositing a metal, or using an excimer laser instead of annealing.

Next, referring to FIG. 2F, a second gate insulating film 207 is formed on the channel 206, and a second gate 208 is formed thereon. The second gate insulating film 207 may be formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a metal oxide film, or the like. It is preferable that a metal oxide film is a high dielectric constant metal oxide film. A size of the second gate 208 is defined through a lithography process for a self-aligning process of the drain 209 to be described later.

Next, referring to FIG. 2G, when impurities are implanted into the channel 206 using the second gate 208 formed as a mask, a self-aligned drain 209 is formed in an edge region of the polysilicon channel 206. .

FIG. 2H is a plan view of the ii-ii 'direction and VII-VII' in FIG. 2G. The plan view in the ii-ii 'direction is a plan view of the position where the drain 209 is formed. Region 208 'is the shape of second gate 208 viewed from above, where drain 209 is self-aligned at the edge of channel 206 along region 208'. Looking at the plan view in the ⅲ-ⅲ 'direction, the channel 206 of the device is surrounded by the first gate 202 and the second gate 208 can provide a high channel control performance by the gate.

Second Embodiment

3A and 3B illustrate a vertical nanoshell structured field effect transistor according to another embodiment of the present invention. As shown in FIG. 3A, a field effect transistor having a vertical nanoshell structure according to another embodiment of the present invention provides a source to the semiconductor substrate 300 when compared to the field effect transistor according to the first embodiment shown in FIG. 2G. In the case of forming the drain 309 of the first embodiment, the source 304 and the drain 309 are simultaneously formed at the edge of the channel 206 by self-alignment at the edge of the channel 206 to form the horizontal source 304 and the drain 309. There is a difference in what it has.

In addition, the roles of the semiconductor substrate 300, the channel insulating layers 301, 301 ′, 305, and 307, the channel 306, the first gate 302, the second gate 308, and the drain 309 are illustrated in FIG. Same as the role of the corresponding component of the field effect transistor shown in 2g.

FIG. 3B is a plan view taken along the line '-' in FIG. 3A. The source 304 and the drain 309 are separated from each other at the time of impurity injection by the shape of the second gate 308 ′ elongated in one direction.

Third Embodiment

4A through 4C are diagrams illustrating a fusion memory device according to an embodiment of the present invention, according to a manufacturing process sequence. The role and formation method of the semiconductor substrate 400, the insulating layers 401, 401 ′, 405, 407, the first gate 402, and the channel 406 are the same as those of the field effect transistor shown in FIG. 2G.

Thereafter, as shown in FIG. 4A, a floating gate 410 capable of storing electrons is formed after formation of the channel 406 and the second gate insulating film 407 (see FIG. 2A to FIG. 2F). . Here, the floating gate 410 may include a polysilicon layer, a nitride layer forming a silicon oxide nitride oxide (SONOS) or a metal nitride oxide silicon (MNOS) structure, an amorphous silicon layer, a metal oxide layer, a silicon nitride layer, and a silicon nanocrystal. It is preferable that any one of the layer, the metal nanocrystal layer or the metal oxide nanocrystal layer or mixed.

Next, as shown in FIG. 4B, another second gate insulating film 411 (control insulating film) is formed on the floating gate 410. The second gate insulating film 411 may be formed to insulate the second gate 408 to be described later, and may be formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a metal oxide film having a high dielectric constant.

4C illustrates that the second gate 408 is formed on the second gate insulating layer 411. Since electrons are injected into or erased from the floating gate 410 by a bias applied to the second gate 408, the size of the second gate 408 is preferably aligned with the floating gate 410. If impurities are implanted after the formation of the second gate 408, the second gate 408 acts as a mask, and thus, around the second gate 408 in the edge region of the channel 406 according to the shape of the second gate 408. The drains 409 connected to each other are formed in self-alignment.

The electron storage for operation as the nonvolatile memory is the floating gate 410 region in FIG. 4C, and the charge storage becomes the floating body region 412 in the capacitorless DRAM operation. In general, nonvolatile memory requires a wider memory window than DRAM and exhibits such characteristics in basic operation. Accordingly, the voltage characteristics of the logic value of the nonvolatile DRAM fusion memory having the vertical nanoshell structure according to the present invention are shown in FIG. 6.

FIG. 6 is a diagram illustrating a threshold voltage change in a current-voltage curve according to an operation of a fusion memory according to an embodiment of the present invention. First, the mechanism according to the nonvolatile memory operation, the I _drain -V _gate curve 601b of the initial logic "1" state is a high threshold voltage (V _T. As the electrons are stored (programmed) in the floating gate 410 _{. H0} ), which represents the shift to the I _drain -V _gate curve 602b, meaning logic "0". When erasing the stored electrons in the floating gate back 410 is moved in the _drain I -V curve _gate (601b) having an initial state of the low threshold voltage (V _{T. L0).}

In the case of the capacitor-less dynamic random access memory and the threshold voltage is lowered in accordance with the accumulation of the storage stand alone with the floating body 412, the charge (V _{T. H0} ⇒ V _{T. H1} or _{V T. L0 ⇒ V T.} L1).

A sensing scheme for applying the aforementioned nonvolatile memory operating characteristics and the capacitorless DRAM operating characteristics to a single device is as follows. As a nonvolatile memory, the device has a state of an I _drain -V _gate curve 601b or 602b depending on whether electrons are stored in the floating gate 410. In this state, when the hole is stored in the floating body 412 for the storage of logic "1" in the operation as the capacitorless DRAM, the curve 601b or 602b moves to the curve 601a or 602a, respectively, and the threshold that appears difference between the voltage V _{T. L0} -V _{T. L1} or V _{T. H0} -V _{T. The H1} value determines whether the logic of the DRAM is "1" or "0". The memory margin that occurs during DRAM operation is V _T , the worst case for which the memory margin that occurs in nonvolatile memory operation is the smallest _{. H1} -V _T. Compared to _L0 , the sense current is small, so a sense amplifier is required through a current sensing scheme having a high sensitivity.

[Example 4]

5 illustrates a fused memory device according to another embodiment of the present invention. The nonvolatile DRAM fusion memory shown in FIG. 5 has no process of forming the source 404 as compared to the nonvolatile DRAM fusion memory shown in FIG. 4C described above, and at the edge of the channel 506 at the time of forming the drain 509. There is a difference in the configuration in which the source 504 and the drain 509 are formed at the same time by self-alignment to have the horizontal source 504 and the drain 509. In addition, the source 504 and the drain 509 are formed separately at the time of impurity implantation by the shape of the gate 508 elongated in one direction. In addition, the roles of the semiconductor substrate 500, the channel insulating layers 501, 501 ′, 505, 507, the channel 506, the first gate 502, the second gate 508, and the drain 509 are illustrated in FIG. It plays the same role as the corresponding component of the fusion memory shown in 4c.

Hereinafter, the operation principle and effects of the field effect transistor and the fusion memory of the vertical nanoshell structure according to the present invention described so far will be described.

The field effect transistor of the vertical nanoshell structure according to the present invention has excellent channel control effect of the gate because two gates surround the inside and outside of the three-dimensional thin channel. The present invention can be driven by applying the same voltage to each gate as if the first and second gates are tied, and the gate material having a different work function for each independently controllable gate for use as a low power device. Threshold voltage effect according to the channel state of depletion / inversion locally different according to different voltages, or by applying different gate voltages to each gate. Variation Effect) Since the threshold voltage can be adjusted, it can be used as a low power device by reducing the supply voltage required for the integrated circuit.

In addition, a fused memory having both a nonvolatile flash memory characteristic and a capacitorless DRAM characteristic according to the present invention is structurally a floating gate or ONO (Oxide-Nitride-Oxide) between the gate insulating layers to operate as a nonvolatile memory like a flash memory. Electron is injected through Fowler-Nordheim tunneling or hot-carrier injection depending on the voltage applied to the gate and source / drain by inserting a charge storage layer such as nitride In the case of capacitorless DRAM operation, holes generated by impact ionization accumulate in the floating-body, which is the lowest potential region. In addition to the hole accumulation method through collision ionization, hole accumulation is possible due to a gate induced drain leakage (GIDL) effect due to a bias. If a negative voltage is applied to the gate, a ground voltage is applied to the source, and a positive voltage is applied to the drain, holes generated by the band-band tunneling due to the GIDL effect are collected by the floating body and accumulate. Applying a ground voltage to the source and a negative voltage to the drain depletes the hole in the floating body.

According to another embodiment of the present invention, a single memory cell having a vertical nanoshell structure can implement a capacitorless DRAM due to a natural floating body effect due to a gate front surface surrounded by a gate. It has excellent channel effect, punchthrough effect, etc., and has a steep slope in the linear region during device operation, so it can have fast switching operation characteristics and leakage current due to high gate control due to the three-dimensional device structure. The reduction has the advantage of increasing the refresh time by increasing the storage time of the charge stored in the floating body in the storage operation of the capacitorless DRAM. Based on this, electrons are injected or erased from the floating gate to have a nonvolatile memory operation characteristic, and a high integration density that achieves a fast DRAM operation characteristic without a capacitor by accumulating and evicting holes in a naturally generated floating body region surrounded by the gate. The fusion memory of can be implemented.

Next, the driving method of the above-described fusion memory device will be described. The fusion memory device according to the present invention may be operated by a floating body effect or a gate induced drain leakage effect. By this effect, holes can be accumulated or expelled.

In addition, when a high driving speed is required, the fusion memory according to the present invention may operate in a DRAM mode in which information is written or erased as holes are accumulated or removed by a bias applied to each of the gate, the source, and the drain. have.

In addition, when a nonvolatile property is required, the fusion memory according to the present invention is a nonvolatile memory mode in which information is erased or written as electrons are injected or erased by a bias applied to each of gates, sources, and drains in a floating gate. It can work as

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is apparent to those skilled in the art that various modifications are possible without departing from the scope of the technical idea of the present invention. something to do.

1 is a view showing a conventional planar field effect transistor.

2A to 2H are diagrams illustrating a field effect transistor having a vertical nanoshell structure according to a first embodiment of the present invention in order of manufacturing process.

3A and 3B illustrate a vertical nanoshell structured field effect transistor according to another embodiment of the present invention.

4A through 4C are diagrams illustrating a fusion memory device according to an embodiment of the present invention, according to a manufacturing process sequence.

5 is a diagram illustrating a fusion memory device according to another exemplary embodiment of the present invention.

FIG. 6 is a diagram illustrating a threshold voltage change in a current-voltage curve according to an operation of a fusion memory according to an embodiment of the present invention.

* Explanation of Signs of Major Parts of Drawings *

200, 300, 400, 500: semiconductor substrate

201, 201 ', 300, 301', 400, 401 ', 500, 501': interlayer insulating film

202, 302, 402, 502: first gate

204, 304, 404, 504: source

205, 305, 405, 505: first gate insulating film

206, 306, 406, 506: channel (polysilicon)

207, 307, 407, 507: second gate insulating film

208, 308, 408, 508: second gate

209, 309, 409, 509: Drain

Claims (22)

A second gate 208 having a first vertical pillar shape; A second vertical column-shaped channel 206 surrounding the side of the second gate 208; A first gate 202 surrounding the side of the channel 206; A source 204 connected to a lower end of the channel 206; And A drain 209 connected to an upper end of the channel 206 and spaced apart from the source 204, And the first gate and the second gate are formed of materials having different work functions. The method of claim 1, Further comprising a semiconductor substrate formed under the channel, The source is formed on the semiconductor substrate, And the drain is formed to surround the outer periphery of the upper portion of the channel. The method of claim 1, Further comprising a semiconductor substrate formed under the channel, The source is connected to a portion of the outer peripheral portion of the upper portion of the channel, And the drain is connected to another portion of the outer circumferential portion at the top of the channel. The method of claim 1, The channel is insulated by the first gate and the second gate and the insulating film, And the insulating film is made of any one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a metal oxide film. delete The method according to claim 2 or 3, And the semiconductor substrate is made of one of silicon, silicon germanium, strained silicon, and tensile silicon germanium. The method of claim 1, The first and second vertical pillars are column or polygonal pillars, field effect transistor. A second gate having a first vertical pillar shape; A second vertical column-shaped channel surrounding the side of the second gate; A first gate surrounding the side of the channel; A source connected to a lower end of the channel; And A drain connected to an upper end of the channel and spaced apart from the source; And A floating gate formed between the second gate and the channel to surround a side of the second gate, The first gate and the second gate are formed of a material having a different work function from each other. The method of claim 8, The floating gate includes a polysilicon layer, a nitride layer forming a silicon oxide nitride oxide (SONOS) or a metal nitride oxide silicon (MNOS) structure, an amorphous silicon layer, a metal oxide layer, a silicon nitride layer, a silicon nanocrystal layer, and a metal nano 1. A fused memory device in which one or more of a crystal layer or a metal oxide nanocrystal layer is mixed. The method of claim 8, The floating gate is insulated by the second gate, the channel and the insulating layer, The insulating film is made of a material of any one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film or a metal oxide film. (a) implanting impurities into the semiconductor substrate to form a source; (b) sequentially stacking a first interlayer insulating film, a first gate, and a second interlayer insulating film on the semiconductor substrate; (c) forming holes in the vertical direction through the first interlayer insulating film, the first gate, and the second interlayer insulating film; (d) forming a first gate insulating film in the hole and exposing the source through an etch back process; (e) forming a nanoshell-shaped channel on the exposed source and the first gate insulating film; (f) forming a second gate insulating film on the channel; (g) forming a second gate inside the hole; And (h) implanting impurities into the nanoshell channels to form a drain. The method of claim 11, The channel is annealing the deposited amorphous silicon or polysilicon at a high temperature or using a laser to increase the size of the silicon crystal to form a channel, the method of manufacturing a field effect transistor. In the method for manufacturing a fused memory device using the method for manufacturing a field effect transistor according to claim 11, Between steps (f) and (g), (i) forming a floating gate on the second gate insulating film; And (j) forming a control insulating film on the floating gate; And the second gate insulating film is a tunneling insulating film. (a) sequentially stacking a first interlayer insulating film, a first gate, and a second interlayer insulating film on a semiconductor substrate; (b) forming holes in the vertical direction through the first interlayer insulating film, the first gate, and the second interlayer insulating film; (c) forming a first gate insulating film in the hole and exposing the semiconductor substrate through an etch back process; (d) forming a nanoshell-shaped channel on the exposed semiconductor substrate and the first gate insulating film; (e) forming a second gate insulating film on the channel; (f) forming a second gate inside the hole; And (g) forming a source and a drain by implanting impurities into the nanoshell channel. The method of claim 14, The channel is annealing the deposited amorphous silicon or polysilicon at a high temperature or using a laser to increase the size of the silicon crystal to form a channel, the method of manufacturing a field effect transistor.  In the method for manufacturing a fused memory device using the method for manufacturing a field effect transistor according to claim 14, Between step (e) and step (f), (i) forming a floating gate on the second gate insulating film; And (j) forming a control insulating film on the floating gate; And the second gate insulating film is a tunneling insulating film. A method of driving the field effect transistor according to claim 1, And applying a different gate voltage to each of the first and second gates to implement a low power consumption transistor. delete delete delete delete delete

Images