KR20000045405A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR20000045405A KR20000045405A KR1019980061963A KR19980061963A KR20000045405A KR 20000045405 A KR20000045405 A KR 20000045405A KR 1019980061963 A KR1019980061963 A KR 1019980061963A KR 19980061963 A KR19980061963 A KR 19980061963A KR 20000045405 A KR20000045405 A KR 20000045405A
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- insulating film
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- interlayer insulating
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000000034 method Methods 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000010410 layer Substances 0.000 claims abstract description 55
- 239000011229 interlayer Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 125000006850 spacer group Chemical group 0.000 claims abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 37
- 229920005591 polysilicon Polymers 0.000 claims description 35
- 239000012535 impurity Substances 0.000 claims description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 239000002019 doping agent Substances 0.000 abstract 2
- 230000015556 catabolic process Effects 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000005415 magnetization Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000012421 spiking Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로서, 특히 저전압 구동 소자와 고전압 구동 소자가 함께 형성되는 반도체소자에서 고전압 및 저전압 소자를 함께 형성할 수 있어 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. In particular, a semiconductor device capable of forming a high voltage and a low voltage device together in a semiconductor device in which a low voltage driving device and a high voltage driving device are formed together can improve process yield and reliability of device operation. It relates to a method for manufacturing a device.
반도체소자가 고집적화되어 감에 따라 소자의 크기를 감소시키기 위하여 모스 전계효과 트랜지스터(Metal Oxide Semiconductor Field Effect Transistor; 이하 MOS FET라 칭함)의 게이트전극이나 소오스/드레인영역 및 이들과의 콘택등 공정 전반의 디자인 룰이 감소되고 있으나, 게이트전극의 폭과 전기저항은 비례 관계에 있어 폭이 N배 줄어들면 전기 저항이 N배 증가되어 반도체소자의 동작 속도를 떨어뜨리는 문제점이 있다. 따라서 게이트전극의 저항을 감소시키기 위하여 가장 안정적인 MOSFET 특성을 나타내는 폴리실리콘층/산화막 계면의 특성을 이용하여 폴리실리콘층과 실리사이드의 적층 구조인 폴리사이드가 저저항 게이트로서 사용하기도 한다.In order to reduce the size of the semiconductor device as the semiconductor device becomes more integrated, the gate electrode, source / drain region, and contact thereof of a metal oxide semiconductor field effect transistor (hereinafter referred to as MOS FET) Although design rules are being reduced, there is a problem in that the width of the gate electrode and the electrical resistance are proportional to each other, so that if the width is reduced by N times, the electrical resistance is increased by N times, thereby reducing the operation speed of the semiconductor device. Therefore, in order to reduce the resistance of the gate electrode, the polysilicon, which is a laminated structure of the polysilicon layer and the silicide, may be used as the low resistance gate by using the characteristics of the polysilicon layer / oxide layer showing the most stable MOSFET characteristics.
일반적으로 반도체소자는 고전압 소자와 저전압 소자를 하나의 칩에 공유하게 되는데, 상기 고전압 소자는 모터 구동등의 고전압 또는 고전류 출력이 필요한 경우나 외부 시스템에서의 고전압 입력이 있는 경우에 사용되고, 상기 저전압 소자는 내부회로에 사용된다.In general, semiconductor devices share a high voltage device and a low voltage device on a single chip, and the high voltage device is used when a high voltage or high current output such as a motor driving is required or when there is a high voltage input from an external system. Is used for internal circuits.
또한 많은 경우가 게이트전극에는 저전압만이 인가되고, 드레인 쪽에만 고전압이 인가되는데, 이러한 고전압 소자의 파괴전압을 높이기 위하여 소자의 구조를 변경하게 된다.In many cases, only a low voltage is applied to the gate electrode, and a high voltage is applied only to the drain side. The structure of the device is changed to increase the breakdown voltage of the high voltage device.
즉, 저전압 소자를 기준으로 공정을 진행하게 되고, 고전압 소자는 고전압을 수용할 수 있는 구조로 변경하게 되는데, 일반적으로 높은 파괴 전압을 유지하기 위하여 접합은 저농도의 깊은 접합을 가지게하는데, 이로 인하여 소자의 면적이 증가되고, 게이트산화막은 F-N 터널링(Fowler-Nordheim tunneling)이 발셍하지 않도록 형성하게된다.That is, the process is performed based on the low voltage device, and the high voltage device is changed to a structure capable of accommodating high voltage. In general, the junction has a low concentration deep junction in order to maintain a high breakdown voltage. The area of the gate electrode is increased and the gate oxide film is formed so that FN tunneling does not occur.
따라서 저전압을 기초로 형성하는 소자에서 웰 구조를 변경하고, 게이트산화막 두께를 두껍게 형성하며, 저전압 소자와 고전압소자간의 최적 접합 파괴전압을 얻기 위하여 많은 시뮬레이션 및 실험이 필요하게 된다.Therefore, many simulations and experiments are required to change the well structure, form a thick gate oxide film, and obtain an optimum junction breakdown voltage between the low voltage device and the high voltage device in a device formed on the basis of low voltage.
여기서 상기 고전압 소자의접합 도핑 구조를 변경시키는 것은 드레인에 인가되는 전압이 높기 때문이며, 따라서 저농도의 깊은 접합을 형성하여 전압 강하를 유도하여, 접합 양단에 가해지는 전기장의 크기를 일반적인 임계값인 약 1E5V/㎝ 보다 작게 유지하여 높은 항복전압을 갖도록하는 것이다. 또한 게이트 산화막의 경우에는 게이트전극과 드레인에 가해지는 전압차에 의한 GIDL(gate-induced drain leakage) 현상에 의한 브레이크 다운을 감소시키고, 즉면 디플리션의 확보하기 위하여 게이트산화막의 두께를 변화시키게 된다.The reason why the junction doping structure of the high voltage device is changed is that the voltage applied to the drain is high, thus forming a low concentration deep junction to induce a voltage drop, and thus the magnitude of the electric field applied to both ends of the junction is a general threshold of about 1E5V. It keeps smaller than / cm to have high breakdown voltage. In addition, in the case of the gate oxide film, the breakdown caused by the gate-induced drain leakage (GIDL) phenomenon due to the voltage difference applied to the gate electrode and the drain is reduced, that is, the thickness of the gate oxide film is changed to secure the depletion. .
상기와 같은 종래 기술에 따른 고전압 소자의 제조방법은 게이트산화막으로 두가지 이상의 두께로 형성하여야하므로 공정이 복잡해지고, 게이트산화막 자체의 신뢰성도 떨어뜨리는 등의 문제점이 있으며, 고전압 소자용 웰과 드레인 도핑 구조의 변경등과 같은 공정을 진행하여야 하므호 공정이 복잡해져 공정수율 및 소자동작의 신뢰성을 떨어뜨리는 다른 문제점이 있다.Since the method of manufacturing a high voltage device according to the related art has to be formed with a gate oxide film having two or more thicknesses, there is a problem that the process becomes complicated and the reliability of the gate oxide film itself is degraded. Since the process such as changing the need to proceed the process is complicated, there is another problem that decreases the process yield and reliability of device operation.
본 발명은 상기와 같은 문제점들을 해결하기 위한 것으로서, 본 발명의 목적은 드레인 접합의 저항을 조절하여 고전압에 대한 내압 구조를 가지는 고전압 소자를 형성하여 공정이 간단하고, 게이트산화막의 신뢰성을 향상시켜 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있는 반도체소자 및 그 제조방법을 제공함에 있다.The present invention is to solve the above problems, the object of the present invention is to adjust the resistance of the drain junction to form a high voltage device having a breakdown voltage structure against high voltage, the process is simple, improve the reliability of the gate oxide film process It is to provide a semiconductor device and a method of manufacturing the same that can improve the yield and reliability of device operation.
도 1a 내지 도 1c는 본 발명의 일실시예에 따른 반도체소자의 제조공정도.1A to 1C are manufacturing process diagrams of a semiconductor device according to an embodiment of the present invention.
도 2는 본 발명의 다른 실시예에 따른 반도체소자의 단면도.2 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
10 : 반도체 기판 12 : 소자분리 산화막10 semiconductor substrate 12 device isolation oxide film
14 : 게이트산화막 16 : 게이트전극14 gate oxide film 16 gate electrode
18 : 저농도 불순물영역 20 : 스페이서18: low concentration impurity region 20: spacer
22 : 고농도 불순영역 22S : 소오스영역22: high concentration impurity region 22S: source region
22D : 드레인영역 24 : 층간절연막22D: drain region 24: interlayer insulating film
26 : 감광막패턴 28 : 콘택홀26: photoresist pattern 28: contact hole
30 : n형 도핑된 도전층 32 : 절연막30 n-type doped conductive layer 32 insulating film
34D,39 : 드레인 콘택 플러그 34S : 소오스 콘택 플럭그34D, 39: Drain Contact Plug 34S: Source Contact Plug
36 : 금속배선36: metal wiring
37 : n형 도핑된 다결정실리콘층37: n-type doped polysilicon layer
38 : p형 도핑된 다결정실리콘층38: p-type doped polysilicon layer
상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체소자의 제조방법의 특징은,Features of the semiconductor device manufacturing method according to the present invention for achieving the above object,
제1도전형의 반도체기판에서 고전압 소자로 예정되어있는 부분상에 게이트산화막을 형성하는 공정과,Forming a gate oxide film on a portion of the first conductive semiconductor substrate which is intended to be a high voltage device;
상기 게이트산화막상에 게이트전극을 형성하는 공정과,Forming a gate electrode on the gate oxide film;
상기 게이트전극 양측의 반도체기판에 제2도전형의 저농도 불순물영역을 형성하는 공정과,Forming a low concentration impurity region of a second conductivity type on the semiconductor substrates on both sides of the gate electrode;
상기 게이트전극의 측벽에 절연 스페이서를 형성하는 공정과,Forming an insulating spacer on sidewalls of the gate electrode;
상기 스페이서 양측의 반도체기판에 제2도전형의 고농도 불순물영역을 형성하여 소오스/드레인영역을 형성하는 공정과,Forming a source / drain region by forming a high concentration impurity region of a second conductivity type on the semiconductor substrate on both sides of the spacer;
상기 드레인영역으로 예정되어있는 부분을 노출시키는 콘택홀을 구비하는 층간절연막을 상기 구조의 표면에 형성하는 공정과,Forming an interlayer insulating film on the surface of the structure, the interlayer insulating film having a contact hole exposing a portion intended for the drain region;
상기 구조의 전표면에 제2도전형의 불순물이 도핑된 다결정실리콘층과 절연막을 순차적을 형성하는 공정과,Sequentially forming a polysilicon layer doped with an impurity of the second conductivity type and an insulating film on the entire surface of the structure;
상기 층간절연막상의 절연막과 다결정실리콘층을 제거하여 콘택홀을 메우는 다결정실리콘층 패턴과 절연막 패턴으로된 오옴믹 접촉되는 콘택 플러그를 형성하는 공정을 구비함에 있다.And removing the insulating film and the polysilicon layer on the interlayer insulating film to form an ohmic contact contact plug having a polysilicon layer pattern filling the contact hole and an insulating film pattern.
본발명의 다른 특징은Other features of the present invention
제1도전형의 반도체기판에서 고전압 소자로 예정되어있는 부분상에 게이트산화막을 형성하는 공정과,Forming a gate oxide film on a portion of the first conductive semiconductor substrate which is intended to be a high voltage device;
상기 게이트산화막상에 게이트전극을 형성하는 공정과,Forming a gate electrode on the gate oxide film;
상기 게이트전극 양측의 반도체기판에 제2도전형의 저농도 불순물영역을 형성하는 공정과,Forming a low concentration impurity region of a second conductivity type on the semiconductor substrates on both sides of the gate electrode;
상기 게이트전극의 측벽에 절연 스페이서를 형성하는 공정과,Forming an insulating spacer on sidewalls of the gate electrode;
상기 스페이서 양측의 반도체기판에 제2도전형의 고농도 불순물영역을 형성하여 소오스/드레인영역을 형성하는 공정과,Forming a source / drain region by forming a high concentration impurity region of a second conductivity type on the semiconductor substrate on both sides of the spacer;
상기 드레인영역으로 예정되어있는 부분을 노출시키는 콘택홀을 구비하는 층간절연막을 상기 구조의 표면에 형성하는 공정과,Forming an interlayer insulating film on the surface of the structure, the interlayer insulating film having a contact hole exposing a portion intended for the drain region;
상기 구조의 전표면에 제2도전형의 불순물이 도핑된 다결정실리콘층과 제1도전형의 불순물이 도핑된 다결정실리콘층을 순차적을 형성하는 공정과,Sequentially forming a polysilicon layer doped with impurities of the second conductivity type and a polysilicon layer doped with impurities of the first conductivity type on the entire surface of the structure;
상기 층간절연막상의 다결정실리콘층들을 제거하여 콘택홀을 메우는 제1 및 제2도전형의 불순물이 도핑된 다결정실리콘층 패턴들로된 오옴믹 접촉되는 콘택 플러그를 형성하는 공정을 구비함에 있다.And removing the polysilicon layers on the interlayer insulating layer to form an ohmic contact contact plug made of polycrystalline silicon layer patterns doped with impurities of the first and second conductivity types filling the contact holes.
이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 제조방법에 대하여 상세히 설명을 하기로 한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1c는 본 발명의 일실시예에 따른 반도체소자의 제조공정도로서, NMOS의 고전압 소자만을 도시한 예이다.1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention, and show only a high voltage device of an NMOS.
먼저, 실리콘 웨이퍼등의 p형 반도체기판(10)상에 소자분리 산화막(12)을 형성하고, 상기 반도체기판(10)상에 게이트산화막(14)과 다결정실리콘층 패턴으로된 게이트전극(16)을 형성하고, 상기 게이트전극(16) 양측의 반도체기판(10)에 n-의 저농도 불순물영역(18)을 형성한 후, 상기 게이트전극(16)의 측벽에 산화막 스페이서(20)를 형성하고, 상기 스페이서(20) 양측의 저농도 불순물 영역(18)에 n+의 고농도 불순물영역(22)을 형성하여, 소오스/드레인영역(22S, 22D)을 완성한다. 여기서 도시되어있지는 않으나, 동일한 구조로 저전압 소자도 형성된다.First, a device isolation oxide film 12 is formed on a p-type semiconductor substrate 10 such as a silicon wafer, and the gate electrode 16 having a gate oxide film 14 and a polysilicon layer pattern on the semiconductor substrate 10 is formed. Form a low concentration impurity region 18 of n− on the semiconductor substrate 10 on both sides of the gate electrode 16, and then form an oxide spacer 20 on the sidewall of the gate electrode 16, A high concentration impurity region 22 of n + is formed in the low concentration impurity region 18 on both sides of the spacer 20 to complete the source / drain regions 22S and 22D. Although not shown here, a low voltage element is also formed with the same structure.
그다음 상기 구조의 전표면에 층간절연막(24)을 형성하고, 화학-기계적 연마(chemical mechanical polishing; CMP) 방법으로 평탄화 시킨 다음 상기 소오스/드레인영역중 드레인으로 예정되어있는 부분상의 층간절연막(24)을 노출시키는 감광막패턴(26)을 형성한 후, 상기 감광막패턴(26)에 의해 노출되어있는 층간절연막(24)을 제거하여 드레인영역(22D)을 노출시키는 콘택홀(28)을 형성한다. (도 1a 참조).An interlayer insulating film 24 is then formed on the entire surface of the structure, planarized by chemical mechanical polishing (CMP), and then interlayer insulating film 24 on the part of the source / drain regions, which is intended to be drained. After forming the photoresist pattern 26 exposing the photoresist layer, the contact hole 28 exposing the drain region 22D is formed by removing the interlayer insulating layer 24 exposed by the photoresist pattern 26. (See FIG. 1A).
그후, 상기 감광막패턴(26)을 제거하고, 상기 구조의 전표면에 n형 도핑된 도전층(30)과 산화막이나 질화막등의 절연막(32)을 도포하여 상기 콘택홀(28)을 메운다. 여기서 상기 드레인 콘택 플러그로 사용되는 도전층(30)은 불순물 도핑 농도에 따라 저항의 조절이 용이한 다결정실리콘층을 사용한다. (도 1b 참조).Thereafter, the photoresist pattern 26 is removed, and the contact hole 28 is filled by applying an n-type doped conductive layer 30 and an insulating film 32 such as an oxide film or a nitride film to the entire surface of the structure. Here, the conductive layer 30 used as the drain contact plug uses a polysilicon layer in which resistance is easily adjusted according to the impurity doping concentration. (See FIG. 1B).
그다음 상기 층간절연막(24)상의 절연막(32)과 도전층(30)을 CMP 나 전면 식각 방법 등으로 제거하여 드레인영역(22D)과 접촉되는 드레인 콘택 플러그(34D)를 형성하고, 상기 소오스영역(22S)을 노출시키는 콘택홀을 형성하고, 다시 이를 메우는 소오스 콘택 플럭그(34S)를 선택 증착되는 텅스텐이나 금속층으로 형성하며, 각각의 콘택 플러그와 접촉되는 금속배선(36)을 층간절연막(24) 상에 형성한다. (도 1c 참조).Thereafter, the insulating film 32 and the conductive layer 30 on the interlayer insulating film 24 are removed by CMP or an entire surface etching method to form a drain contact plug 34D in contact with the drain region 22D, and the source region ( 22S) is formed, and the source contact plug 34S filling the gap is formed of tungsten or a metal layer to be selectively deposited, and the metal wiring 36 in contact with each contact plug is formed in the interlayer insulating film 24. Form on the phase. (See FIG. 1C).
상기에서 도전층과 절연막으로 드레인 콘택 플러그를 형성하는 공정은 고전압 소자의 드레인 콘택이 저전압 소자의 콘택 보다 크게 형성되므로, 충분한 디자인 룰상의 여유를 가지고 공정을 진행할 수 있다.In the process of forming the drain contact plug with the conductive layer and the insulating layer, since the drain contact of the high voltage device is formed to be larger than that of the low voltage device, the process may be performed with a sufficient design rule.
또한 드레인 콘택의 크기와 다결정실리콘층의 도핑 정도 및 도전층과 절연막간의 두께를 조절하는 것으로서 드레인 콘택 저항을 용이하게 조절할 수 있으며, 플러그 이온주입이나 플러그 형성후의 이온주입 등으로 드레인영역과 다결정실리콘층간에는 오옴믹 콘택이 되도록하여야 하고, 접합 계면에서의 불순물 농도는 디제너러시(degeneracy)를 보상하여야한다.In addition, the drain contact resistance can be easily controlled by controlling the size of the drain contact, the degree of doping of the polysilicon layer, and the thickness between the conductive layer and the insulating film, and between the drain region and the polysilicon layer by plug ion implantation or ion implantation after plug formation. It should be an ohmic contact, and the impurity concentration at the junction interface should compensate for the degeneracy.
도 2는 본 발명의 다른 실시예에 따른 반도체소자의 단면도로서, NMOS 의 예이며, 도 1c 에서의 드레인 콘택 플러그(34D)를 n형 도핑된 다결정실리콘층(37)과 p형 도핑된 다결정실리콘층(38)을 순차적으로 적층하고, 이를 CMP나 전면 이방성 식각으로 제거하여 n형 및 p형 도핑된 다결정실리콘층(37),(38) 패턴으로된 콘택플러그(39)를 형성하고, 후속 공정을 진행한 것이다.FIG. 2 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention, which is an example of an NMOS, in which the drain contact plug 34D in FIG. 1C is n-type doped polysilicon layer 37 and p-type doped polysilicon. Layer 38 is sequentially stacked and removed by CMP or full anisotropic etching to form contact plugs 39 in the n- and p-type doped polysilicon layers 37, 38 pattern, and subsequent steps Will proceed.
여기서 상기 n형 도핑된 다결정실리콘층(37)과 p형 도핑된 다결정실리콘층(38) 모두가 금속배선(36)과 접촉되어 있으며, 상기에서 드레인 접합과는 n형 도핑된 다결정실리콘층(37)이 맞닿아 있고, p형 도핑된 다결정실리콘층(38)은 동일 전압 상태가 된다. 따라서 n-p 접합간의 빌트인 포텐셜 만큼의 전위장벽차가 있어 전류의 흐름에는 p형 도핑된 다결정실리콘층(38)은 기여하지 못하는 준 절연(quasi- insulating) 상태가 되므로, n형 도핑된 다결정실리콘층(37)이 차지하는 면적이 유효 단면적이 되어 저항을 조절하는 수단이 된다. 상기 p형 도핑된 다결정실리콘층(38)은 도핑되지 않은 다결정실리콘층으로 형성할 수도 있다.Herein, both the n-type doped polysilicon layer 37 and the p-type doped polysilicon layer 38 are in contact with the metal wiring 36, and the n-type doped polysilicon layer 37 is connected to the drain junction. ) Are in contact with each other, and the p-type doped polysilicon layer 38 is in the same voltage state. Therefore, since there is a potential barrier difference as much as the built-in potential between the np junctions, the p-doped polysilicon layer 38 becomes a quasi-insulating state in which the p-type doped polysilicon layer 38 does not contribute to the flow of current, and thus the n-type doped polysilicon layer 37 The area occupied by) becomes an effective cross-sectional area, which serves as a means for adjusting resistance. The p-type doped polysilicon layer 38 may be formed of an undoped polysilicon layer.
상기한 바와같이 본 발명에 따른 반도체소자의 제조방법은, 하나의 칩에 저전압 소자와 고전압 소자가 함께 형성되는 경우 저전압 소자를 기준으로 공정을 진행하여 소자를 형성하고, 고전압 소자의 드레인 영역에만 고전압이 인가되며, 고전압 소자의 콘택이 저전압 소자에 비해 디자룰이 크게 형성되는 점을 이용하여, 고전압소자의 드레인 영역과 접촉되어 금속배선과 연결시키는 드레인 콘택 플러그를 저항의 조절이 용이한 물질른 접합과 동일 도전형으로 도핑된 다결정실리콘층과 절연막의 적층 구조로 형성하거나, 동일 도전형 및 반대 도전형으로 도핑된 다결정실리콘층으로 형성하여 고전압 소자의 드레인에 인가되는 고전압을 용이하게 강하시켰으므로, 고전압 드레인 콘택에서의 전자축퇴나 접합 스파이킹에 의한 불량 발생이나, 고전압 소자형성에 따른 수율 및 신뢰성 저하를 방지할 수 있으며, 콘택의 크기를 감소시켜 소자의 고집적화를 유리하게하는 효과가 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, when a low voltage device and a high voltage device are formed together on one chip, a process is performed based on a low voltage device to form a device, and a high voltage is applied only to the drain region of the high voltage device. Is applied, and the contact of the high voltage device is formed larger than that of the low voltage device, so that the drain contact plug which contacts the drain region of the high voltage device and connects with the metal wiring is easily bonded. The high voltage applied to the drain of the high-voltage device is easily dropped by forming a stacked structure of a polysilicon layer and an insulating film doped with the same conductivity type as or a polysilicon layer doped with the same conductivity type and an opposite conductivity type. Failure due to electron degeneracy or junction spiking at high voltage drain contact or high voltage The yield and reliability deterioration due to magnetization can be prevented, and the size of the contact can be reduced, thereby facilitating high integration of the device.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030001642A (en) * | 2001-06-25 | 2003-01-08 | 주식회사 하이닉스반도체 | Method for forming the contact plug of semiconductor device |
| KR100720518B1 (en) * | 2005-12-28 | 2007-05-22 | 동부일렉트로닉스 주식회사 | Semiconductor device and method for fabricating semiconductor device |
| KR100741271B1 (en) * | 2006-06-28 | 2007-07-19 | 주식회사 하이닉스반도체 | Method for forming a contact plug in semiconductor device |
| KR100866690B1 (en) * | 2007-05-18 | 2008-11-04 | 주식회사 동부하이텍 | Method for contact hole of semiconductor device |
| US11114152B1 (en) | 2020-04-22 | 2021-09-07 | SK Hynix Inc. | Semiconductor memory device including page buffers |
-
1998
- 1998-12-30 KR KR1019980061963A patent/KR100307828B1/en not_active IP Right Cessation
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030001642A (en) * | 2001-06-25 | 2003-01-08 | 주식회사 하이닉스반도체 | Method for forming the contact plug of semiconductor device |
| KR100720518B1 (en) * | 2005-12-28 | 2007-05-22 | 동부일렉트로닉스 주식회사 | Semiconductor device and method for fabricating semiconductor device |
| KR100741271B1 (en) * | 2006-06-28 | 2007-07-19 | 주식회사 하이닉스반도체 | Method for forming a contact plug in semiconductor device |
| KR100866690B1 (en) * | 2007-05-18 | 2008-11-04 | 주식회사 동부하이텍 | Method for contact hole of semiconductor device |
| US11114152B1 (en) | 2020-04-22 | 2021-09-07 | SK Hynix Inc. | Semiconductor memory device including page buffers |
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