JP2004103637A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To restrain or prevent carriers from being reduced in mobility when the gate insulating film of a field-effect transistor is made of a high-k material higher in permittivity than silicon oxide. <P>SOLUTION: In NMISQN and PMISQP each equipped with the gate insulating film 7 made of high-k material, channels are made at a position deeper than a contacting interface between the gate insulating film 7 and a p-type semiconductor layer 2a or an n-type semiconductor layer 2b. In NMISQN, an n-type semiconductor layer 5 is formed on the surface layer of the p-type semiconductor layer 2a under a gate electrode 8B, and in PMISQP, a p-type semiconductor layer 6 is formed on the n-type semiconductor layer 2b under a gate electrode 8C to form a buried channel. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a technology for manufacturing the same, and more particularly to a semiconductor device using a material having a higher dielectric constant than silicon oxide for a gate insulating film and a technology effective when applied to a technology for manufacturing the same.
[0002]
[Prior art]
For example, as described in Japanese Patent Application Laid-Open No. 2000-150668, for the purpose of mainly reducing the resistance of a fine gate electrode and improving the gate depletion rate, metal is used instead of polysilicon in which an impurity is introduced into the gate electrode. There is an example using. In order to prevent a rise in threshold voltage when a metal is used for the gate electrode, a buried channel structure is formed to realize a low threshold voltage.
[0003]
Further, in a current semiconductor device manufacturing technique, a silicon oxide film (SiO 2) is used as a gate insulating film of a metal oxide semiconductor (MOS) element. ₂ ) Is used. In recent years, miniaturization of MOS devices has been promoted in order to achieve high integration of semiconductor devices. However, as the miniaturization of MOS devices progresses, it is necessary to make the gate insulating film thinner.
[0004]
However, when the silicon oxide film as the gate insulating film is thinned, a tunnel current is generated between the gate electrode and the channel formation region due to a tunnel effect, and a leak current is increased. When the leakage current increases, there is a problem that power consumption increases.
[0005]
Therefore, by using a material having a higher dielectric constant than the oxide film (hereinafter, referred to as a high-k material), the thickness of the gate insulating film is increased while maintaining the same capacitance. When the thickness of the gate insulating film is increased, no tunnel current is generated between the gate electrode and the channel formation region, and the above problem can be solved.
[0006]
As an example of a MOS type device using a high-k material for a gate insulating film, for example, L.K. Kang et al. , IEDM Tech. Dig. , 35 (2000).
[0007]
[Problems to be solved by the invention]
However, when the above-described high-k material is used for the gate insulating film, there is a problem that the mobility of electrons flowing in a channel formation region formed immediately below the gate insulating film is deteriorated. That is, when a high-k material is used for the gate insulating film, the flatness of the surface of the gate insulating film is significantly reduced, and electrons flowing in a channel formation region adjacent to the gate insulating film are scattered. For this reason, there is a problem that the mobility of electrons decreases and the current flowing through the channel formation region decreases.
[0008]
An object of the present invention is to provide a technique capable of suppressing or preventing a decrease in the mobility of electrons flowing in a channel formation region even when a high-k material is used for a gate insulating film.
[0009]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0010]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0011]
According to the present invention, in a field effect transistor having a gate insulating film containing a high-k material, a channel is formed at a position deeper than an interface between the gate insulating film and a semiconductor during operation.
[0012]
Further, the present invention provides (a) a first semiconductor layer into which impurities of a first conductivity type are introduced, and (b) a gate insulating film formed on the first semiconductor layer and containing a material having a higher dielectric constant than silicon oxide. (C) a gate electrode formed on the gate insulating film, and (d) a layer formed in a channel formation region in the first semiconductor layer immediately below the gate electrode, the first conductivity type being included. And a second semiconductor layer into which impurities of a different conductivity type are introduced.
[0013]
Further, the present invention provides (a) a step of forming a first semiconductor layer into which an impurity of a first conductivity type is introduced, and (b) a step of forming a channel formation region of the first semiconductor layer having a conductivity type different from the first conductivity type. Forming a second semiconductor layer by introducing impurities, (c) forming a gate insulating film containing a material having a higher dielectric constant than silicon oxide on the second semiconductor layer, and (d) forming the gate. Forming a gate electrode on the insulating film.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted. In the present embodiment, a MIS • FET (Metal Insulator Field Effect Transistor) representing a field effect transistor is abbreviated as MIS, a P-channel MIS • FET is abbreviated as PMIS, and an N-channel MIS • FET is represented as PMIS. Is abbreviated as NMIS.
[0015]
(Embodiment 1)
The semiconductor device according to the first embodiment will be described with reference to the drawings. FIG. 1 is a main part sectional view showing the configuration of the semiconductor device according to the first embodiment. In FIG. 1, the element portion of the semiconductor device according to the first embodiment has NMISQN in which an N-type channel is formed and PMISQP in which a P-type channel is formed.
[0016]
The semiconductor substrate 1A is made of, for example, single crystal silicon (Si), and the insulating layer 1 is formed on the semiconductor substrate 1A. The insulating layer 1 is made of, for example, silicon oxide. On the insulating layer 1, a semiconductor layer (first semiconductor) including a P-type semiconductor layer 2a as a component of NMISQN and an N-type semiconductor layer 2b as a component of PMISQP is provided. One example of a layer) 2 is formed. The thickness of the semiconductor layer 2 is, for example, 100 nm or more. A P-type impurity such as boron (B) is introduced into the P-type semiconductor layer 2a. An N-type impurity such as phosphorus or arsenic (As) is introduced into the N-type semiconductor layer 2b. NMISQN and PMISQP are formed on the main surfaces of the P-type semiconductor layer 2a and the N-type semiconductor layer 2b, respectively. The NMISQN and the PMISQP are separated from each other by the element isolation layer 4. The element isolation layer 4 is formed by embedding an insulating film made of, for example, silicon oxide or the like in a trench dug in the semiconductor layer 2 (a trench isolation structure). The lower portion of the element isolation layer 4 is formed so as to reach the insulating layer 1, and has a structure in which NMISQN and PMISQP are completely separated. With such an SOI (Silicon On Insulator) structure, complete isolation between elements can be achieved, so that the integration density of elements can be improved. In addition, since complete isolation between elements can be achieved, malfunction due to crosstalk, latch-up phenomenon, and the like via the semiconductor substrate 1A can be prevented. Further, since the junction capacitance is reduced, it is possible to form an element with high speed operation and low power consumption.
[0017]
Next, a structural example of the NMISQN will be described as follows. The NMISQN includes a P-type semiconductor layer 2a, an N-type semiconductor layer 5 (an example of a second semiconductor layer), a gate insulating film 7, a gate electrode 8B, a low-concentration N-type impurity diffusion layer (second region) 9, 10, It has concentration N-type impurity diffusion layers (second regions) 13 and 14 and sidewalls 17. This NMISQN is formed on the insulating layer 1 and has an SOI (Silicon On Insulator) structure. In the P-type semiconductor layer 2a immediately below the gate electrode 8B between the low-concentration N-type impurity diffusion layers (second regions) 9 and 10 for source and drain in the semiconductor layer 2, the surface thereof is transferred to the insulating layer 1. The reaching region is the first region, and an NMISQN channel is formed in a part of the first region.
[0018]
The gate electrode 8B of the NMISQN is made of, for example, N-type polysilicon, and sidewalls 17 are formed on both side surfaces thereof. In the semiconductor layer 2 (P-type semiconductor layer 2a), low-concentration N-type impurity diffusion layers 9 and 10 and high-concentration N-type impurities forming source and drain semiconductor regions of NMISQN are located at positions corresponding to both sides of the gate electrode 8B. Diffusion layers 13 and 14 are formed. That is, a source region including the low concentration N-type impurity diffusion layer 9 and the high concentration N-type impurity diffusion layer 13 and a drain region including the low concentration N-type impurity diffusion layer 10 and the high concentration N-type impurity diffusion layer 14 are formed. ing. N-type impurities such as phosphorus (P) or arsenic (As) are introduced into the low-concentration N-type impurity diffusion layers 9 and 10 and the high-concentration N-type impurity diffusion layers 13 and 14. The low-concentration N-type impurity diffusion layers 9 and 10 near the channel formation region (the operation region of the P-type semiconductor layer 2a immediately below the gate electrode 8B) have a lower impurity concentration than the high-concentration N-type impurity diffusion layers 13 and 14. It has a function of reducing generation of hot carriers due to relaxation of electric field concentration.
[0019]
In the P-type semiconductor layer 2a, in the channel formation region immediately below the gate electrode 8B, the N-type semiconductor layer 5 is formed so as to be sandwiched between the low-concentration N-type impurity diffusion layers 9 and 10. An N-type impurity such as phosphorus (P) or arsenic (As) is introduced into the N-type semiconductor layer 5, for example. When the NMIS QN is not operating (when no operating voltage is applied to the gate electrode 8B), a depletion layer is formed in the P-type semiconductor layer 2a immediately below the gate electrode 8B. However, the depletion layer does not reach the insulating layer 1, and has a configuration in which a neutral region (P-type semiconductor layer 2a) with many carriers exists between the depletion layer and the insulating layer 1 (partial depletion). Type). In such a partially depleted SOI, for example, the following effects can be obtained as compared with a case where a bulk is used as a substrate. First, the junction capacitance can be reduced. For this reason, since the load capacity can be reduced, a device that operates at high speed and consumes low power can be developed. Further, signal transmission loss during high frequency operation can be reduced. Second, the substrate bias effect can be improved. Third, the same process as that for the bulk can be applied to setting of the threshold value and formation of the silicide layer at the source and drain. On the other hand, when the NMISQN operates (when a predetermined operation voltage is applied to the gate electrode 8B), a channel is formed near the boundary between the N-type semiconductor layer 5 and the P-type semiconductor layer 2a. That is, in the present embodiment, by providing the N-type semiconductor layer 5, the channel through which electrons pass is formed not at the contact interface between the gate insulating film 7 and the semiconductor layer 2, but at a position deeper than the contact interface. (Embedded channel). The effect of this will be described later.
[0020]
A gate insulating film 7 is formed between the gate electrode 8B and the semiconductor layer 2 (the N-type semiconductor layer 5 of the P-type semiconductor layer 2a). The gate insulating film 7 is made of, for example, aluminum oxide (Al ₂ O ₃ ), Zirconium oxide (ZrO) ₂ ), Hafnium oxide (HfO ₂ ), Titanium oxide (TiO) ₂ ), Silicon nitride (Si ₃ N ₄ ) Or tantalum oxide (Ta) ₂ O ₅ ), Etc. are formed from a high-k material. By forming the gate insulating film 7 from a high-k material in this manner, it is possible to increase the capacity required for improving the characteristics of the MIS without making the gate insulating film 7 thin. Therefore, since the thickness of the gate insulating film 7 can be secured to some extent, a leak current generated between the gate electrode 8B and the channel can be reduced. However, when a high-k material is used as the material of the gate insulating film 7, the flatness of the surface of the semiconductor layer 2 in contact with the gate insulating film 7 is reduced as compared with the case where silicon oxide is used as the material of the gate insulating film 7. I do. Therefore, if the channel of the NMISQN is formed at the interface between the gate insulating film 7 and the semiconductor layer 2, that is, a so-called surface channel is formed, electrons flowing through the channel will not pass through the gate insulating film 7 and the semiconductor. As a result of scattering due to unevenness at the interface with the layer 2, the mobility of electrons decreases, and the driving current amount of the NMISQN decreases. On the other hand, in the present embodiment, the N-type semiconductor layer 5 is provided in the channel formation region of the P-type semiconductor layer 2a, and the channel of the NMISQN is not at the interface between the gate insulating film 7 and the semiconductor layer 2, but at the interface thereof. By being formed at a deeper position, the electrons serving as carriers can be buried without being disturbed by the unevenness of the interface between the gate insulating film 7 and the semiconductor layer 2 and without being scattered. Can move channels. That is, since scattering of electrons flowing through the channel of the NMISQN can be suppressed or prevented, a decrease in the mobility of the electrons can be suppressed or prevented.
[0021]
FIG. 2 schematically illustrates a state in which electrons flow through the surface channel in a surface channel type NMIS in which the gate insulating film 7 is formed of a high-k material. The contact interface between the gate insulating film 7 using a high-k material and the semiconductor layer 2 has low flatness and unevenness. In this NMIS, since a channel is formed on the surface of the P-type semiconductor layer 2a, when electrons move through the channel, the electrons are scattered by the unevenness existing on the gate insulating film 7 and the surface of the P-type semiconductor layer 2a. . Therefore, the mobility of electrons is reduced and the current is reduced.
[0022]
On the other hand, FIG. 3 schematically shows how electrons flow through the buried channel in the NMISQN according to the first embodiment. In the NMISQN according to the first embodiment, the N-type semiconductor layer 5 is provided in the channel formation region immediately below the gate insulating film 7, so that when a voltage is applied to the gate electrode 8B, the N-type semiconductor layer 5 and the P-type semiconductor A buried channel is formed near the boundary with the layer 2a (interface region). That is, the electrons do not move directly below the gate insulating film 7 as shown in FIG. 2, but flow into a region deeper than immediately below the gate insulating film 7 as shown in FIG. That is, since the electrons flow in a place not in contact with the gate insulating film 7, the electrons can flow in the channel without being scattered by the unevenness existing on the surface of the gate insulating film 7. For this reason, according to NMISQN in the first embodiment, it is possible to suppress or prevent a decrease in electron mobility.
[0023]
FIG. 4 is an enlarged cross-sectional view of a main part of the NMISQN according to the first embodiment. FIG. 5 is a graph showing an impurity concentration profile at a predetermined position in the depth direction from the silicon surface A in FIG. It is shown. That is, FIG. 5 shows the impurity concentration distribution of the N-type semiconductor layer 5 forming the buried channel. As can be seen from FIG. 5, a maximum of 1.0 × 10 ¹⁸ (1 / cm ³ ) With an impurity concentration of 1.0) and a maximum of 1.0 × 10 ¹⁷ (1 / cm ³ It can be seen that boron (B) having an impurity concentration of (a) is introduced. By introducing impurities as described above, the N-type semiconductor layer 5 can be formed.
[0024]
Next, the configuration of the PMISQP will be described. The PMISQP shown in FIG. 1 includes an N-type semiconductor layer 2b, a P-type semiconductor layer 6 (an example of a second semiconductor layer), a gate insulating film 7, a gate electrode 8C, a low-concentration P-type impurity diffusion layer (second region) 11 , 12, high-concentration P-type impurity diffusion layers (second regions) 15, 16, and sidewalls 18. In the N-type semiconductor layer 2b immediately below the gate electrode 8C between the low-concentration P-type impurity diffusion layers (second regions) 11 and 12 for source and drain in the semiconductor layer 2, the surface thereof is transferred to the insulating layer 1. The reaching region is the first region, and a PMISQP channel is formed in a part of the first region.
[0025]
The gate electrode 8C of the PMISQP is made of, for example, P-type polysilicon, and sidewalls 18 are formed on both side surfaces thereof. In the semiconductor layer 2 (N-type semiconductor layer 2b), the low-concentration P-type impurity diffusion layers 11 and 12 and the high-concentration P-type impurity which constitute the source and drain semiconductor regions of the PMISQP are located at positions corresponding to both sides of the gate electrode 8C. Diffusion layers 15 and 16 are formed. That is, a source region including the low-concentration P-type impurity diffusion layer 11 and the high-concentration P-type impurity diffusion layer 15 and a drain region including the low-concentration P-type impurity diffusion layer 12 and the high-concentration P-type impurity diffusion layer 16 are formed. ing. P-type impurities such as boron (B) are introduced into the low-concentration P-type impurity diffusion layers 11 and 12 and the high-concentration P-type impurity diffusion layers 15 and 16. The low-concentration P-type impurity diffusion layers 11 and 12 (close to the operating region of the N-type semiconductor layer 2b immediately below the electrode 8C) have a lower impurity concentration than the high-concentration P-type impurity diffusion layers 15 and 16; It has a function of reducing generation of hot carriers due to relaxation of concentration.
[0026]
In the N-type semiconductor layer 2b, the P-type semiconductor layer 6 is formed in the channel formation region immediately below the gate electrode 8B so as to be sandwiched between the low-concentration P-type impurity diffusion layers 11 and 12. A P-type impurity such as boron (B) is introduced into the P-type semiconductor layer 6. When the PMISQP is not operating (when the operating voltage is not applied to the gate electrode 8C), a depletion layer is formed in the channel formation region (N-type semiconductor layer 2b) immediately below the gate electrode 8C. However, the depletion layer does not reach the insulating layer 1 and has a configuration in which a neutral region (N-type semiconductor layer 2b) with many carriers exists between the depletion layer and the insulating layer 1 (partial depletion). Type). In such a partially depleted SOI, the above-described effects can be obtained as compared with a case where a bulk is used as a substrate. On the other hand, when the PMISQP operates (when a predetermined operation voltage is applied to the gate electrode 8C), a channel is formed near the boundary between the P-type semiconductor layer 6 and the N-type semiconductor layer 2b. That is, in the present embodiment, by providing the P-type semiconductor layer 6, the channel, which is a path for electrons, is formed not at the contact interface between the gate insulating film 7 and the semiconductor layer 2 but at a position deeper than the contact interface. (Embedded channel). Therefore, in the case of PMISQP as well, like NMISQN, scattering of carriers due to unevenness at the contact interface between the gate insulating film 7 and the semiconductor layer 2 can be suppressed or prevented, and a decrease in carrier mobility can be suppressed or prevented.
[0027]
A gate insulating film 7 is formed between the gate electrode 8C and the semiconductor layer 2 (P-type semiconductor layer 6 of N-type semiconductor layer 2b). The material of the gate insulating film 7 is the same as the above-described high-k material, and its effect is the same as that described for NMISQN, and thus the description is omitted. Further, in the present embodiment, the P-type semiconductor layer 6 is provided in the channel formation region of the N-type semiconductor layer 2b, and the channel during the operation of the PMISQP is not at the interface between the gate insulating film 7 and the semiconductor layer 2, but at the interface thereof. By forming the holes at a deeper position, the holes serving as carriers are buried without being disturbed by the unevenness of the interface between the gate insulating film 7 and the semiconductor layer 2 and without being scattered. You can move the inbound channel. That is, since scattering of holes flowing through the PMISQP channel can be suppressed or prevented, a decrease in the mobility of the holes can be suppressed or prevented.
[0028]
Next, a wiring portion of the semiconductor device according to the first embodiment will be described. Note that the description of the wiring section shows up to the first wiring layer, and the description of the further layers is omitted.
[0029]
In FIG. 1, an interlayer insulating layer 30 made of, for example, silicon oxide is formed on NMISQN and PMISQP. In this interlayer insulating layer 30, holes reaching the high concentration N-type impurity diffusion layers 13 and 14 of NMISQN and the high concentration P-type impurity diffusion layers 15 and 16 of PMISQP are formed. In the hole reaching the source layer of NMISQN, a titanium nitride film 31a and a tungsten film 31b are buried to form a plug 31, and in the hole reaching the drain layer of NMISQN, a titanium nitride film 32a and a tungsten film 32b are buried. Thus, a plug 32 is formed. In a hole reaching the source layer of the PMISQP, a titanium nitride film 33a and a tungsten film 33b are embedded to form a plug 33. In a hole reaching the drain layer of the PMISQP, a titanium nitride film 34a and a tungsten film 34b are formed. Is embedded to form a plug 34. The plug 31 is connected to a first layer wiring 35 composed of a titanium nitride film 35a, a tungsten film 35b, and a titanium nitride film 35c. Further, the plug 32 and the plug 33 are connected to a first layer wiring 36 composed of a titanium nitride film 36a, a tungsten film 36b, and a titanium nitride film 36c. Therefore, the drain layer of NMISQN and the source layer of PMISQP are connected by the first layer wiring 36, and a CMIS (Complementary MIS) type element is formed. The plug 34 is connected to a first layer wiring 37 made of a titanium nitride film 37a, a tungsten film 37b, and a titanium nitride film 37c. On the first layer wiring 35, the first layer wiring 36, and the first layer wiring 37, an interlayer insulating layer 38 made of, for example, silicon oxide is formed.
[0030]
Next, a method of manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS. 6 to 12 are fragmentary cross-sectional views of the semiconductor device of First Embodiment during manufacturing steps.
[0031]
First, as shown in FIG. 6, an insulating layer 1 made of silicon oxide is formed on a semiconductor substrate 1A made of silicon by using a thermal oxidation method. Next, a semiconductor substrate containing, for example, boron (B), which is a P-type impurity, is bonded to the surface of the semiconductor substrate 1A on which the insulating layer 1 is formed and subjected to heat treatment, and then, for example, is subjected to a predetermined method by a CMP (Chemical Mechanical Polishing) technique. (For example, 100 nm or more) to form the semiconductor layer 2 (an example of a first semiconductor layer).
[0032]
Subsequently, after a silicon nitride film is formed on the semiconductor layer 2 using a CVD method, the silicon nitride film is patterned using a photolithography technique and an etching technique. Thereafter, the semiconductor layer 2 is etched using the patterned silicon nitride film as a mask to form element isolation trenches. Then, a silicon oxide film is deposited on the semiconductor layer 2 in which the element isolation trench is formed by using the CVD method.
[0033]
Next, the silicon oxide film deposited on portions other than the isolation trenches is removed by using the CMP technique, and an isolation layer 4 for isolating the region of the semiconductor layer 2 is formed. Subsequently, a resist film is applied on the semiconductor layer 2 and the element isolation layer 4, and is patterned by exposing and developing. In this patterning, a resist pattern is formed so that the PMIS formation region is exposed and other regions are covered. Then, for example, phosphorus (P) or arsenic (As), which is an N-type impurity, is implanted into the semiconductor layer 2 by using an ion implantation method in a region exposed from the resist pattern, so that the N-type semiconductor layer 2b (first An example of a semiconductor layer) is formed. Thus, a so-called SOI (Silicon On Insulator) structure can be formed.
[0034]
Next, as shown in FIG. 7, arsenic, which is an N-type impurity, is implanted into the P-type semiconductor layer 2a using a photolithography technique and an ion implantation method, and then heat treatment is applied to the N-type semiconductor layer 5 (the 2 example). Similarly, after boron, which is a P-type impurity, is implanted into the N-type semiconductor layer 2b using a photolithography technique and an ion implantation method, the P-type semiconductor layer 6 (an example of the second semiconductor layer) is subjected to heat treatment. Form.
[0035]
Subsequently, as shown in FIG. 8, a gate insulating film 7 made of a high-k material having a dielectric constant higher than that of silicon oxide is formed by a CVD method by a CVD method or the like. A silicon film 8A is deposited. As a high-k material having a higher dielectric constant than silicon oxide, for example, Al ₂ O ₃ , ZrO ₂ , HfO ₂ , TiO ₂ , Si ₃ N ₄ Or Ta ₂ O ₅ And the like. Although an example in which a high-k material is used as the gate insulating film 7 is described, the gate insulating film 7 may be a stacked film of a high-k film and a silicon oxide film. Thereafter, phosphorus or arsenic, which is an N-type impurity, is implanted into the polysilicon film 8A in the NMISQN formation region using a photolithography technique and an ion implantation method. Similarly, boron, which is a P-type impurity, is implanted into the polysilicon film 8A in the PMIS QP formation region using a photolithography technique and an ion implantation method. The impurity of the polysilicon film 8A may be introduced when depositing it. Subsequently, the polysilicon film 8A is patterned by using a photolithography technique and an etching technique to form a gate electrode 8B containing an N-type impurity and a gate electrode 8C containing a P-type impurity as shown in FIG.
[0036]
Next, as shown in FIG. 10, by using a photolithography technique and an ion implantation method, an N-type impurity is implanted to form low-concentration N-type impurity diffusion layers 9 and 10. Then, low-concentration P-type impurity diffusion layers 11 and 12 in which P-type impurities are implanted are formed by using an ion implantation method.
[0037]
Subsequently, after depositing a silicon nitride film or a silicon oxide film on the gate insulating film 7 and the gate electrodes 8B and 8C using the CVD method, the silicon nitride film or the silicon oxide film is etched back by anisotropic etching. The walls 17 and 18 are formed. Then, by using a photolithography technique and an ion implantation method, N-type impurities are implanted to form high-concentration N-type impurity diffusion layers 13 and 14. Similarly, P-type impurities are implanted by using a photolithography technique and an ion implantation method to form high-concentration P-type impurity diffusion layers 15 and 16.
[0038]
Next, as shown in FIG. 12, an interlayer insulating layer 30 made of silicon oxide is formed on the gate insulating film 7 and the gate electrodes 8B and 8C by using the CVD method, and reaches the source layer and the drain layer of NMISQN. A through hole is formed and a through hole reaching the source and drain layers of the PMISQP is formed.
[0039]
Subsequently, after forming the titanium nitride films 31a, 32a, 33a, and 34a in the formed through holes by using the sputtering method, the tungsten films 31b, 32b, 33b, and 34b are formed by using the CVD method. Thereafter, the plugs 31, 32, 33, and 34 are formed by performing CMP polishing.
[0040]
Next, as shown in FIG. 1, a titanium nitride film is formed on the interlayer insulating layer 30 and the plugs 31, 32, 33, and 34 using a sputtering method, and then a tungsten film is formed using a CVD method. Thereafter, a titanium nitride film is formed again by using the sputtering method. Subsequently, using a photolithography technique and an etching technique, a first layer wiring 35 composed of a titanium nitride film 35a, a tungsten film 35b, and a titanium nitride film 35c, a titanium nitride film 36a, a tungsten film 36b, and a titanium nitride film 36c are formed. A first layer wiring 37 including a first layer wiring 36, a titanium nitride film 37a, a tungsten film 37b, and a titanium nitride film 37c is formed. Thereafter, an interlayer insulating layer 38 made of silicon oxide is formed on the first layer wiring 35, the first layer wiring 36, and the first layer wiring 37 by using the CVD method. Thus, the semiconductor device according to the first embodiment can be manufactured.
[0041]
(Embodiment 2)
In the second embodiment, a case where the semiconductor device in the first embodiment is manufactured by a method different from the manufacturing method described in the first embodiment will be described. 13 to 24 are fragmentary cross-sectional views of the semiconductor device of Second Embodiment during manufacturing steps.
[0042]
First, in the same manner as described in the first embodiment, an insulating layer 1 is formed on a semiconductor substrate 1A as shown in FIG. The semiconductor layer 2a and the N-type semiconductor layer 2b are formed.
[0043]
Next, as shown in FIG. 14, a dummy gate insulating film 21 made of a silicon oxide film is formed on the P-type semiconductor layer 2a, the N-type semiconductor layer 2b and the element isolation layer 4 by using a thermal oxidation method. Then, a polysilicon film 22A is deposited on the dummy gate insulating film 21 by using the CVD method. Thereafter, the dummy gate electrode 22 is formed by patterning the polysilicon film 22A using a photolithography technique and an etching technique, as shown in FIG. Here, a silicon nitride film may be deposited instead of the polysilicon film 22A.
[0044]
Subsequently, as shown in FIG. 16, for example, phosphorus or arsenic, which is an N-type impurity, is implanted into the P-type semiconductor layer 2 a using a photolithography technique and an ion implantation method, and then heat treatment is performed so that the low-concentration N-type The impurity diffusion layers 9 and 10 are formed. Similarly, after boron, which is a P-type impurity, is implanted into the N-type semiconductor layer 2b using a photolithography technique and an ion implantation method, heat treatment is performed to form the low-concentration P-type impurity diffusion layers 11, 12.
[0045]
Thereafter, a silicon nitride film is formed on the dummy gate insulating film 21 and the dummy gate electrode 22 by using the CVD method, and anisotropic etching is performed to form sidewalls 17 and 18 shown in FIG.
[0046]
Next, high-concentration N-type impurity diffusion layers 13 and 14 are formed by using a photolithography technique and an ion implantation method, and then performing heat treatment after implanting phosphorus or arsenic, which are N-type impurities. Similarly, by using a photolithography technique and an ion implantation method, high-concentration P-type impurity diffusion layers 15 and 16 are formed by performing heat treatment after implanting boron as a P-type impurity.
[0047]
Subsequently, as shown in FIG. 18, after a silicon oxide film 23 is deposited on the element formation surface of the semiconductor layer 2 by using the CVD method, the surface of the dummy gate electrode 22 is exposed by using the CMP technique. Polish the silicon oxide film 23 to a certain extent. Then, as shown in FIG. 19, the dummy gate electrode 22 is removed using a photolithography technique and an etching technique. Thereafter, as shown in FIG. 20, after a resist film is applied on the dummy gate insulating film 21 and the silicon oxide film 23, the resist film is patterned by exposing and developing. In this patterning, no resist film is left in the NMISQN formation region. Next, phosphorus or arsenic, which is an N-type impurity, is implanted into the NMISQN formation region by using an ion implantation method. The implanted phosphorus or arsenic is injected into the channel formation region of the P-type semiconductor layer 2a, and the N-type semiconductor layer 5 for forming the buried channel is formed by the subsequent heat treatment.
[0048]
Next, after removing the patterned resist film, a resist film is applied on the dummy gate insulating film 21 and the silicon oxide film 23, and the resist film is patterned by exposing and developing. This patterning prevents the resist film from remaining in the PMISQP formation region. Next, boron, which is a P-type impurity, is implanted into the PMISQP formation region by using an ion implantation method. The implanted boron is injected into a channel formation region of the N-type semiconductor layer 2b, and a heat treatment thereafter forms a P-type semiconductor layer 6 for forming a buried channel.
[0049]
Then, after removing the resist film, as shown in FIG. 21, the exposed dummy gate insulating film 21 is removed by etching. Then, as shown in FIG. 22, a high-k film 7A made of a high-k material having a higher dielectric constant than silicon oxide is deposited by a CVD method or the like using a CVD method. As a high-k material having a higher dielectric constant than silicon oxide, for example, Al ₂ O ₃ , ZrO ₂ , HfO ₂ , TiO ₂ , Si ₃ N ₄ Or Ta ₂ O ₅ And the like.
[0050]
Next, as shown in FIG. 23, a polysilicon film 8A is deposited on the high-k film 7A using the CVD method, and then the polysilicon in the NMISQN formation region is formed using the photolithography technique and the ion implantation method. An N-type impurity such as phosphorus or arsenic is implanted into the film 8A. Similarly, boron, which is a P-type impurity, is implanted into the polysilicon film 8A in the PMIS QP formation region using a photolithography technique and an ion implantation method.
[0051]
Subsequently, as shown in FIG. 24, the high-k film 7A and the polysilicon film 8A are polished by using the CMP technique, so that the gate insulating film 7, the gate electrode 8B in which the N-type impurity is implanted, and the P-type A gate electrode 8C into which impurities are implanted is formed. Although an example in which polysilicon is used as the gate electrodes 8B and 8C has been described, since a gate electrode is formed after forming a diffusion layer accompanied by high heat treatment, for example, tungsten (W), molybdenum (Mo), cobalt (Co), or the like is used. Metals may be used. At this time, since the formation of the diffusion layer requiring high-temperature heat treatment has been completed, even if a metal film having a relatively low melting point is used for the gate electrode 8C, it is formed without causing defects such as melting of the metal. can do.
[0052]
Subsequent steps are the same as those described in the first embodiment, and a description thereof will be omitted. Thus, the semiconductor device according to the first embodiment can also be manufactured by the method for manufacturing a semiconductor device according to the second embodiment.
[0053]
(Embodiment 3)
FIG. 25 is a cross-sectional view of a main part of the semiconductor device according to the third embodiment.
[0054]
In the third embodiment, when NMISQN and PMISQP are not operating, the semiconductor layer 2 (N-type semiconductor layer 5 and P-type semiconductor layer 6) immediately below the gate electrodes 8B and 8C is completely depleted. . That is, the semiconductor layer 2 immediately below the gate electrodes 8B and 8C is completely depleted from the main surface of the semiconductor layer 2 to the insulating layer 1 (fully depleted type). For this reason, the semiconductor layer 2 is formed thinner than in the first embodiment, and has a thickness of, for example, 50 nm or thinner. In such a fully depleted SOI, for example, the following effects can be obtained as compared with a case where a bulk is used as a substrate or a partially depleted SOI. First, the junction capacitance can be reduced as compared with the case where a bulk is used. For this reason, since the load capacity can be reduced, a device with high speed operation and low power consumption can be developed, and signal transmission loss during high frequency operation can be reduced. Second, the substrate bias effect can be improved as compared with the case where a bulk is used. Third, the subthreshold coefficient can be reduced as compared with the partially depleted type. Therefore, assuming the same off-state current, the threshold voltage of the fully depleted type can be reduced by about 0.1 V as compared with the partially depleted type or the bulk, and the speed performance of a semiconductor device operating at a low voltage can be reduced. Can be improved. Fourth, the floating effect of the substrate can be reduced as compared with the partially depleted type. For this reason, the operation stability of the MIS can be improved, so that the circuit and layout design can be facilitated.
[0055]
Also, low-concentration N-type impurity diffusion layers 9 and 10 and high-concentration N-type impurity diffusion layers (second regions) 13 and 14 for source and drain of NMISQN, and low-concentration P-type impurity for source and drain of PMISQP The diffusion layers 11 and 12 and the high-concentration P-type impurity diffusion layers (second regions) 15 and 16 are formed to extend from the surface of the semiconductor layer 2 to the insulating layer 1.
[0056]
Other configurations are the same as those of the first and second embodiments. For example, also in the third embodiment, the gate insulating film 7 is configured to include a high-k material as in the first and second embodiments. Also in the third embodiment, during the operation of the NMISQN and the PMISQP, the channel through which carriers (electrons or holes) pass is not at the contact interface between the gate insulating film 7 and the semiconductor layer 2 but at the contact interface. Deeper, here near the interface between the insulating layer 1 and the semiconductor layer 2 (buried channel). Therefore, even in a semiconductor device having a fully depleted SOI structure as in the third embodiment, carriers (electrons or holes) of NMISQN and PMISQP interfere with unevenness at the interface between gate insulating film 7 and semiconductor layer 2. The buried channel can be moved without being scattered and scattered. That is, scattering of carriers flowing through the NMISQN and PMISQP channels can be suppressed or prevented, so that a decrease in the mobility of the carriers can be suppressed or prevented.
[0057]
Next, a method for manufacturing a semiconductor device according to the third embodiment will be described.
[0058]
First, an insulating layer 1 is formed on a semiconductor substrate 1A as shown in FIG. 26 in the same manner as in the method described in the first embodiment. Forms a semiconductor layer 2 of about 50 nm or thinner. Thus, a so-called SOI structure can be formed.
[0059]
Next, as shown in FIG. 27, after covering the PMIS formation region with a resist film 24, phosphorus or arsenic, which is an N-type impurity, is implanted into the P-type semiconductor layer 2 using an ion implantation method. Then, an N-type semiconductor layer 5 in which a buried channel is formed by heat treatment is formed. In the present embodiment, N-type semiconductor layer 5 is formed from the main surface of semiconductor layer 2 to insulating layer 1. Here, in the ion implantation method, the length in the lateral direction is controlled according to the thickness in the depth direction. That is, if the thickness in the depth direction for implanting ions is small, the length in the horizontal direction for implanting ions can be correspondingly reduced. Therefore, in the present embodiment, since the thickness of the N-type semiconductor layer 5 is formed as thin as, for example, 50 nm or less, the lateral length of the N-type semiconductor layer 5 formed by the ion implantation method is also reduced. can do. For this reason, miniaturization of the NMIS becomes possible.
[0060]
Subsequently, after removing the resist film 24, as shown in FIG. 28, the NMIS formation region is covered with a resist film 25, and then boron as a P-type impurity is implanted into the semiconductor layer 2 by using an ion implantation method. . Then, a P-type semiconductor layer 6 in which a buried channel is formed by heat treatment is formed. In the present embodiment, P-type semiconductor layer 6 is formed from the main surface of semiconductor layer 2 to insulation layer 1. Like the above NMIS, miniaturization is possible on the PMIS side.
[0061]
Next, after removing the resist film 25, as shown in FIG. 29, the silicon oxide is formed on the semiconductor layer 2 including the N-type semiconductor layer 5 and the P-type semiconductor layer 6 and the element isolation layer 4 by using the CVD method. A gate insulating film 7 made of a high-k material having a higher dielectric constant is deposited. Then, a polysilicon film 8A is formed on the gate insulating film 7 by using the CVD method, and then the polysilicon film 8A formed on the NMISQN formation region is formed by using the photolithography technique and the ion implantation method. Phosphorus and arsenic, which are mold impurities, are implanted. Similarly, using a photolithography technique and an ion implantation method, boron, which is a P-type impurity, is implanted into the polysilicon film 8A formed on the PMISQP formation region.
[0062]
Thereafter, the polysilicon film 8A is patterned by using a photolithography technique and an etching technique to form gate electrodes 8B and 8C shown in FIG. Subsequently, low-concentration N-type impurity diffusion layers 9 and 10 and low-concentration P-type impurity diffusion layers 11 and 12 are formed using a photolithography technique and an ion implantation method.
[0063]
Next, after a silicon nitride film is formed on the gate insulating film 7 and the gate electrodes 8B and 8C by using the CVD method, the sidewalls 17 and 18 shown in FIG. Form. Then, by using a photolithography technique and an ion implantation method, N-type impurities are implanted to form high-concentration N-type impurity diffusion layers 13 and 14. Similarly, P-type impurities are implanted by using a photolithography technique and an ion implantation method to form high-concentration P-type impurity diffusion layers 15 and 16. FIG. 31 is a plan view of a main part of the semiconductor device according to the third embodiment having undergone the above steps, as viewed from above. In FIG. 31, NMISQN has a gate electrode 8B with a sidewall 17 between the high-concentration N-type impurity diffusion layers 13 and 14, and PMISQP has a side electrode between the high-concentration P-type impurity diffusion layers 15 and 16. It can be seen that there is a gate electrode 8C with a wall 18. Further, it can be seen that the entire periphery of NMISQN and PMISQP is separated by the element separation layer 4. Subsequent steps are the same as in the first embodiment, and a description thereof will be omitted. Thus, the semiconductor device according to the third embodiment can be formed.
[0064]
Next, a modified example of the semiconductor device according to the third embodiment will be described. FIG. 32 is a main part perspective view showing the configuration of a semiconductor device according to a modification. FIG. 33 is a sectional view taken along line Y1-Y1 in FIG. 32, and FIG. 34 is a sectional view taken along line X1-X1 in FIG. An insulating layer 1 is formed on a semiconductor substrate 1A, and a semiconductor layer 2 is provided on the insulating layer 1 in an island shape. In this semiconductor layer 2, NMISQN and PMISQP are formed adjacent to each other. An element isolation layer 4 is formed between the NMIS QN and the PMIS QP. The element isolation layer 4 is formed so as to reach the insulating layer 1 from the main surface of the semiconductor layer 2. Therefore, NMISQN and PMISQP are completely separated by the insulating layer 1 and the element isolation layer 4.
[0065]
The thickness d of the semiconductor layer 2 is formed, for example, to be 50 nm or thinner as described above, and has a fully depleted SOI structure. Of course, similarly to the first embodiment, a partially depleted SOI structure may be used. Here, the difference from the above is that the gate insulating film 7 and the gate electrodes 8B and 8C of NMISQN and PMISQP are formed so as to cover the upper surface and side surfaces of the semiconductor layer 2. Therefore, the effective gate width of each of NMISQN and PMISQP (the length in the longitudinal direction of gate electrodes 8B and 8C) can be represented by the sum of width W and thickness d × 2 (= W + 2d). That is, it can be made longer by the thickness d × 2 than the gate width of NMISQN and PMISQP having the structure shown in FIG. Therefore, the current flowing during the operation of NMISQN and PMISQP can be made larger than that of NMISQN and PMISQP having the structure shown in FIG. Therefore, the operation speed of NMISQN and PMISQP can be improved. Here, the case where width W> thickness d is illustrated, but assuming that width W <thickness d or width W = thickness d, the same effective gate width (W + 2d) as NMISQN and PMISQp in FIG. 32 is obtained. You may do it. That is, although the effective gate width of the MIS is the same, the gate width may be obtained by the planar width W, or may be obtained by the thickness of the semiconductor layer 2. You may get it equally.
[0066]
Even in such a structure, the channels of the NMISQN and the PMISQP are located deeper than the interface between the gate insulating film 7 and the semiconductor layer 2 and the semiconductor layer 2 in the same manner as in the first and second embodiments and the example described with reference to FIG. On the side surface, it is formed at a position away from the interface between the gate insulating film 7 and the semiconductor layer 2. Therefore, also in this case, scattering of carriers of NMISQN and PMISQP can be suppressed or prevented, and a decrease in carrier mobility can be suppressed or prevented. The illustration of the side walls on the side surfaces of the gate electrodes 8B and 8C is omitted.
[0067]
(Embodiment 4)
35 is a perspective view of a main part of the semiconductor device according to the fourth embodiment, FIG. 36 is a sectional view taken along line Z1-Z1 in FIG. 35, FIG. 37 is a sectional view taken along line Z2-Z2 in FIG. 35, and FIG. 35 is a sectional view taken along line Z3-Z3, and FIG. 39 is a sectional view taken along line Y2-Y2 in FIG.
[0068]
In the fourth embodiment, a columnar semiconductor layer 27 is provided on the insulating layer 1 via the semiconductor layer 2 (N-type semiconductor layer 2b). An example of a semiconductor device including a structure in which an NMISQN channel is formed is described. Here, NMIS is exemplified, but PMIS may be formed. Further, the semiconductor layer 27 is not limited to a columnar shape, but may be a cubic shape.
[0069]
The semiconductor layer 27 is made of, for example, silicon ⁺ Semiconductor layer (second region) 27a, N-type semiconductor layer (second semiconductor layer, first region) 5 and N ⁺ The type semiconductor layer (second region) 27b is formed so as to sequentially overlap from the lower layer. The semiconductor layers 27a and 27b are regions where semiconductor regions for the source and drain of the MIS are formed. An N-type impurity such as, for example, phosphorus or arsenic is introduced into the semiconductor layers 27a and 27b. Of these, the lowest N ⁺ The type semiconductor layer 27a is electrically connected to the semiconductor layer 2. The semiconductor layer 2 is electrically connected to the terminal T1 through a wiring. On the other hand, the uppermost N ⁺ The type semiconductor layer 27b is electrically connected to the terminal T2 through a wiring.
[0070]
The base of the semiconductor layer 27 (N from the bottom of the semiconductor layer 27) ⁺ An insulating layer 26 is formed in a cylindrical shape so as to cover the outer periphery of the semiconductor layer 27a (the portion up to the height position in the middle of the semiconductor layer 27a). The insulating layer 26 is made of, for example, silicon oxide and has a function of separating the gate electrode 8D from the semiconductor layer 2. A gate insulating film 7 is formed in a cylindrical shape above the base of the semiconductor layer 27 so as to cover the outer periphery thereof (particularly, the outer periphery of the N-type semiconductor layer 5). The gate insulating film 7 is formed of the same high-k material as in the first to third embodiments. Further, on the outer periphery of the semiconductor layer 27, a gate electrode 8D is formed in a cylindrical shape via the gate insulating film 7 so as to cover the outer periphery (in particular, the outer periphery of the N-type semiconductor layer 5). The gate electrode 8D is made of, for example, N-type polysilicon. The gate electrode 8D is electrically connected to the terminal T3 through a wiring.
[0071]
Also in the fourth embodiment, when NMISQN is not operating, the entire N-type semiconductor layer 5 in the middle of the semiconductor layer 27 is depleted (fully depleted type). On the other hand, during the operation of the NMIS (when a predetermined operating voltage is applied to the gate electrode 8D), the channel of the NMISQN is not at the interface between the gate insulating film 7 and the semiconductor layer 27, but at a position deeper than the interface, that is, the circle. The columnar semiconductor layer 27 is formed such that it is formed from the central axis toward the outer periphery thereof (buried channel). In this case, electrons that are carriers of NMISQN flow along the central axis of the columnar semiconductor layer 27 (along the vertical direction in FIG. 29). Therefore, electrons as carriers can move through the buried channel without being disturbed by the unevenness of the interface between the gate insulating film 7 and the semiconductor layer 27 and without being scattered. That is, since scattering of electrons flowing through the channel of the NMISQN can be suppressed or prevented, a decrease in the mobility of the electrons can be suppressed or prevented.
[0072]
Next, a method for manufacturing the semiconductor device of the fourth embodiment will be described with reference to FIGS. 40 to 43 are main-portion cross-sectional views of the semiconductor device during the manufacturing process thereof.
[0073]
First, as shown in FIG. 40, an insulating layer 1 made of silicon oxide is formed on a semiconductor substrate 1A made of silicon by using a thermal oxidation method. Next, a semiconductor substrate into which, for example, phosphorus or arsenic, which is an N-type impurity, has been introduced, is bonded to the surface of the semiconductor substrate 1A on which the insulating layer 1 is formed, and heat-treated, and then polished to a predetermined thickness by a CMP technique. Then, a semiconductor layer 2 (N-type semiconductor layer 2b) is formed.
[0074]
Subsequently, as shown in FIG. 41, a first amorphous silicon film doped with an N-type impurity such as phosphorus or arsenic is formed on the N-type semiconductor layer 2b. A second amorphous silicon film doped with an N-type impurity and a third amorphous silicon film doped with an N-type impurity such as phosphorus or arsenic, which are substantially the same as the first amorphous silicon, are sequentially deposited from below by a CVD method or the like. Then, heat treatment is performed to crystallize these amorphous silicon films. The crystallization of the amorphous silicon film may be performed by a heat treatment in a step of forming a gate insulating film described later. Alternatively, the first amorphous silicon film may be formed by doping an N-type impurity by an ion implantation method or the like after depositing by a CVD method, and then applying a heat treatment. The same applies to the second and third amorphous silicon films.
[0075]
Subsequently, the semiconductor layer 27 is patterned into a column by photolithography and etching. This gives N ⁺ Semiconductor layer 27a, N-type semiconductor layer 5 and N ⁺ A columnar semiconductor layer 27 having a type semiconductor layer 27b is formed.
[0076]
Next, an insulating layer 26 made of silicon oxide is deposited on the SOI substrate by the CVD method, and is etched back to form the insulating layer 26 on the base of the semiconductor layer 27 as shown in FIG. Thereafter, a gate insulating film 7 made of a high-k material having a higher dielectric constant than silicon oxide is formed by a CVD method or the like. Subsequently, as shown in FIG. 43, an N-type polysilicon film 28 is deposited by a CVD method or the like so as to cover the gate insulating film 7, and is patterned by using a photolithography technique and an etching technique. The gate electrode 8D is formed as shown in FIG. Subsequently, the insulating layer 26 and the N-type semiconductor layer 2b are formed into a shape shown in FIG. 39 by using a photolithography technique and an etching technique. Thus, the semiconductor device according to the fourth embodiment can be formed.
[0077]
As a modification of the fourth embodiment, another element (for example, MIS) may be formed on the main surface of the semiconductor substrate 1A. For example, a driver MIS of an SRAM memory cell is formed on the main surface of the semiconductor substrate 1. The load MIS or the transfer MIS of the memory cell of the SRAM is formed by the vertical NMISQN. The source or drain of the driver MIS is electrically connected to one of the source and drain (that is, the terminal T1) of the vertical NMIS QN through a wiring. If the vertical MISQN is a transfer MIS, the other of the source and the drain (that is, the terminal T2) is electrically connected to the data line. The gate electrode 8D of the vertical NMISQN (that is, the terminal T3) is electrically connected to a word line. In this case, the insulating layer 1 corresponds to an interlayer insulating film between wiring layers.
[0078]
As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and can be variously modified without departing from the gist thereof. Needless to say.
[0079]
The effects obtained by the typical embodiments of the embodiments disclosed in the present application will be briefly described below.
[0080]
With the SOI structure, complete isolation between elements can be achieved, so that the integration density of elements can be improved. Further, since complete isolation between elements can be achieved, malfunction due to crosstalk, latch-up phenomenon, and the like via the semiconductor substrate can be prevented. Further, since the junction capacitance is reduced, it is possible to form an element with high speed operation and low power consumption.
[0081]
In addition, by forming the gate insulating film from a high-k material having a higher dielectric constant than the silicon oxide film, a capacity required for improving the characteristics of the MIS can be obtained without reducing the thickness of the gate insulating film. Therefore, since the thickness of the gate insulating film can be secured to some extent, a leak current generated between the gate electrode and the channel can be reduced.
[0082]
In the field effect transistor having a gate insulating film containing a high-k material, according to the NMISQn of the present embodiment, the N-type semiconductor layer 5 is formed so that the interface between the gate insulating film and the semiconductor can be formed during the operation. By forming a channel at a deeper position, scattering of electrons flowing through the channel of the field-effect transistor can be prevented.
[0083]
Further, by completely depleting the semiconductor layer below the gate in the SOI structure, the junction capacitance can be reduced as compared with a case where a bulk is used as a substrate or a partially depleted SOI. Further, signal transmission loss during high frequency operation can be reduced. Further, the substrate bias effect can be improved as compared with the case where a bulk is used. Further, the subthreshold coefficient can be reduced as compared with the partially depleted type.
[0084]
【The invention's effect】
The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
[0085]
A decrease in mobility of electrons flowing through the channel formation region can be suppressed or prevented.
[Brief description of the drawings]
FIG. 1 is a fragmentary cross-sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view of a main part schematically showing a state where electrons flow and are scattered in a channel formed immediately below a gate insulating film.
FIG. 3 is a fragmentary cross-sectional view schematically showing how electrons flow in a buried channel in the first embodiment of the present invention.
FIG. 4 is an essential part cross sectional view showing a part of the semiconductor device in the first embodiment of the present invention;
FIG. 5 is a graph showing a profile of an impurity concentration at a predetermined position proceeding in a depth direction from a silicon surface.
FIG. 6 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step according to Embodiment 1 of the present invention;
FIG. 7 is an essential part cross sectional view of the semiconductor device of First Embodiment of the present invention during a manufacturing step;
FIG. 8 is an essential part cross sectional view of the semiconductor device of First Embodiment of the present invention during a manufacturing step;
FIG. 9 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step according to Embodiment 1 of the present invention;
FIG. 10 is an essential part cross sectional view of the semiconductor device of First Embodiment of the present invention during a manufacturing step;
FIG. 11 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step according to Embodiment 1 of the present invention;
FIG. 12 is an essential part cross sectional view of the semiconductor device of First Embodiment of the present invention during a manufacturing step;
FIG. 13 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step according to Embodiment 2 of the present invention;
FIG. 14 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step according to Embodiment 2 of the present invention;
FIG. 15 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step according to Embodiment 2 of the present invention;
FIG. 16 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step according to Embodiment 2 of the present invention;
FIG. 17 is an essential part cross sectional view of the semiconductor device of Second Embodiment of the present invention during a manufacturing step;
FIG. 18 is an essential part cross sectional view of the semiconductor device of Second Embodiment of the present invention during a manufacturing step;
FIG. 19 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step according to Embodiment 2 of the present invention;
FIG. 20 is an essential part cross sectional view of the semiconductor device of Second Embodiment of the present invention during a manufacturing step;
FIG. 21 is an essential part cross sectional view of the semiconductor device of Second Embodiment of the present invention during a manufacturing step;
FIG. 22 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step according to Embodiment 2 of the present invention;
FIG. 23 is an essential part cross sectional view of the semiconductor device of Second Embodiment of the present invention during a manufacturing step;
FIG. 24 is an essential part cross sectional view of the semiconductor device of Second Embodiment of the present invention during a manufacturing step;
FIG. 25 is an essential part cross sectional view showing the configuration of a semiconductor device in Embodiment 3 of the present invention.
FIG. 26 is an essential part cross sectional view of the semiconductor device of Third Embodiment during a manufacturing step thereof;
FIG. 27 is an essential part cross sectional view of the semiconductor device of Third Embodiment during a manufacturing step thereof;
FIG. 28 is an essential part cross sectional view of the semiconductor device of Third Embodiment of the present invention during a manufacturing step;
FIG. 29 is an essential part cross sectional view of the semiconductor device of Third Embodiment during a manufacturing step thereof;
FIG. 30 is an essential part cross sectional view of the semiconductor device of Third Embodiment during a manufacturing step thereof;
FIG. 31 is a main part plan view of the semiconductor device according to the third embodiment of the present invention, as viewed from above;
FIG. 32 is an essential part perspective view showing the configuration of a semiconductor device in a modification of Embodiment 3 of the present invention;
FIG. 33 is a sectional view taken along line Y1-Y1 of FIG. 32;
FIG. 34 is a sectional view taken along line X1-X1 of FIG. 32;
FIG. 35 is a perspective view showing a configuration of a semiconductor device according to a fourth embodiment of the present invention.
36 is a sectional view taken along line Z1-Z1 in FIG.
FIG. 37 is a sectional view taken along line Z2-Z2 in FIG.
38 is a sectional view taken along line Z3-Z3 in FIG.
39 is a sectional view taken along line Y2-Y2 of FIG.
FIG. 40 is an essential part cross sectional view of the semiconductor device of Fourth Embodiment during a manufacturing step thereof;
FIG. 41 is an essential part cross sectional view showing the manufacturing process of the semiconductor device, following FIG. 40;
FIG. 42 is an essential part cross sectional view showing the manufacturing process of the semiconductor device, following FIG. 41;
FIG. 43 is an essential part cross sectional view showing the manufacturing process of the semiconductor device following FIG. 42;
[Explanation of symbols]
1A Semiconductor substrate
1 insulating layer
2 Semiconductor layer (first semiconductor layer)
2a P-type semiconductor layer (first semiconductor layer)
2b N-type semiconductor layer (first semiconductor layer)
4 Device isolation layer
5 N-type semiconductor layer (second semiconductor layer, first region)
6 P-type semiconductor layer (second semiconductor layer, first region)
7 Gate insulating film
7A high-k membrane
8 Gate electrode
8A polysilicon film
8B Gate electrode
8C gate electrode
8D gate electrode
9 Low concentration N-type impurity diffusion layer (second region)
10 Low concentration N-type impurity diffusion layer (second region)
11 Low concentration P-type impurity diffusion layer (second region)
12 Low-concentration P-type impurity diffusion layer (second region)
13 High-concentration N-type impurity diffusion layer (second region)
14 High-concentration N-type impurity diffusion layer (second region)
15 High-concentration P-type impurity diffusion layer (second region)
16 High-concentration P-type impurity diffusion layer (second region)
17 Sidewall
18 Sidewall
21 Dummy gate insulating film
22 Dummy gate electrode
22A polysilicon film
23 Silicon oxide film
24 Resist film
25 Resist film
26 Insulation layer
27 Semiconductor layer
28 N-type polysilicon film
30 interlayer insulation layer
31 plug
31a Titanium nitride film
31b Tungsten film
32 plug
32a Titanium nitride film
32b tungsten film
33 plug
33a Titanium nitride film
33b Tungsten film
34 plug
34a Titanium nitride film
34b tungsten film
35 First layer wiring
35a Titanium nitride film
35b Tungsten film
35c titanium nitride film
36 First layer wiring
36a Titanium nitride film
36b Tungsten film
36c titanium nitride film
37 First layer wiring
37a Titanium nitride film
37b Tungsten film
37c titanium nitride film
38 Interlayer insulation film
QNN N-channel type MIS • FET
QP P-channel type MIS • FET

Claims (27)

(A) a first semiconductor layer of a first conductivity type;
(B) a gate insulating film formed on the first semiconductor layer and containing a material having a higher dielectric constant than silicon oxide;
(C) a gate electrode formed on the gate insulating film;
(D) a second semiconductor layer formed in the first semiconductor layer immediately below the gate electrode and having a second conductivity type different from the first conductivity type. (A) an insulating layer;
(B) a first semiconductor layer of a first conductivity type formed on the insulating layer;
(C) a gate insulating film formed on the first semiconductor layer and containing a material having a higher dielectric constant than silicon oxide;
(D) a gate electrode formed on the gate insulating film;
(E) a second semiconductor layer formed in the first semiconductor layer immediately below the gate electrode and having a second conductivity type different from the first conductivity type. (A) an insulating layer;
(B) a first semiconductor layer of a first conductivity type formed on the insulating layer;
(C) a gate insulating film formed on the first semiconductor layer and containing a material having a higher dielectric constant than silicon oxide;
(D) a gate electrode formed on the gate insulating film;
(E) a first region formed immediately below the gate electrode in the first semiconductor layer;
(F) a field effect transistor having a second region formed on both sides of the first region of the first semiconductor layer;
A semiconductor device, wherein a channel of the field effect transistor is formed in the first region at a position apart from an interface between the gate insulating film and the first semiconductor layer. (A) an insulating layer;
(B) a first semiconductor layer of a first conductivity type formed on the insulating layer;
(C) a gate insulating film formed on the first semiconductor layer and containing a material having a higher dielectric constant than silicon oxide;
(D) a gate electrode formed on the gate insulating film;
(E) a first region formed immediately below the gate electrode in the first semiconductor layer;
(F) a field effect transistor having source and drain second regions formed on both sides of the first region of the first semiconductor layer,
A semiconductor device, wherein a buried channel is formed in the first region when the field effect transistor operates. (A) an insulating layer;
(B) a first semiconductor layer of a first conductivity type formed on the insulating layer;
(C) a gate insulating film formed on the first semiconductor layer and containing a material having a higher dielectric constant than silicon oxide;
(D) a gate electrode formed on the gate insulating film;
(E) a first region formed immediately below the gate electrode in the first semiconductor layer;
(F) a field effect transistor having a second region formed on both sides of the first region of the first semiconductor layer;
A semiconductor device, wherein a part of the first region is depleted when the field effect transistor is not operating. (A) an insulating layer;
(B) a first semiconductor layer of a first conductivity type formed on the insulating layer;
(C) a gate insulating film formed on the first semiconductor layer and containing a material having a higher dielectric constant than silicon oxide;
(D) a gate electrode formed on the gate insulating film;
(E) a first region formed immediately below the gate electrode in the first semiconductor layer;
(F) a field effect transistor having a second region formed on both sides of the first region of the first semiconductor layer;
A semiconductor device, wherein the entire first region is depleted when the field effect transistor is not operating. (A) a columnar semiconductor layer;
(B) a first region formed in the columnar semiconductor layer;
(C) second regions formed on both sides of the first region of the columnar semiconductor layer;
(D) an insulating film formed so as to cover the outer periphery of the columnar semiconductor layer, wherein the gate insulating film includes a material having a higher dielectric constant than silicon oxide;
(E) a field effect transistor having a gate electrode formed so as to cover at least a part of the outer periphery of the first region of the columnar semiconductor layer via the gate insulating film;
A semiconductor device, wherein a channel of the field effect transistor is formed in the first region at a position away from an interface between the gate insulating film and the columnar semiconductor layer. (A) a columnar semiconductor layer;
(B) a first region formed in the columnar semiconductor layer;
(C) second regions for source and drain formed on both sides of the first region of the columnar semiconductor layer;
(D) an insulating film formed so as to cover the outer periphery of the columnar semiconductor layer, wherein the gate insulating film includes a material having a higher dielectric constant than silicon oxide;
(E) a field effect transistor having a gate electrode formed so as to cover at least a part of the outer periphery of the first region of the columnar semiconductor layer via the gate insulating film;
A semiconductor device, wherein a channel of the field effect transistor is formed on a center axis side of the columnar semiconductor layer. The semiconductor device according to claim 7, wherein
A semiconductor device, wherein the entire first region is depleted when the field effect transistor is not operating. 10. The semiconductor device according to claim 1, wherein the gate insulating film contains any one of aluminum oxide, zirconium oxide, hafnium oxide, titanium oxide, silicon nitride, and tantalum oxide. 11. Semiconductor device. The semiconductor device according to claim 1, wherein the gate electrode includes one of N-type polysilicon, P-type polysilicon, and a metal. (A) forming a first semiconductor layer of a first conductivity type;
(B) forming a second semiconductor layer of a second conductivity type different from the first conductivity type in a first region of the first semiconductor layer;
(C) forming a gate insulating film including a material having a higher dielectric constant than silicon oxide on the second semiconductor layer;
(D) forming a gate electrode on the gate insulating film. (A) preparing a substrate having a first conductive type first semiconductor layer formed on an insulating layer;
(B) forming a second semiconductor layer of a second conductivity type different from the first conductivity type in a first region of the first semiconductor layer;
(C) forming a gate insulating film including a material having a higher dielectric constant than silicon oxide on the second semiconductor layer;
(D) forming a gate electrode on the gate insulating film. (A) preparing a substrate having a first conductive type first semiconductor layer formed on an insulating layer;
(B) forming a field-effect transistor in the first semiconductor layer;
The step of forming the field-effect transistor,
(B1) forming a gate insulating film containing a material having a higher dielectric constant than silicon oxide on the first semiconductor layer;
(B2) forming a gate electrode on the gate insulating film;
(B3) forming a second region of a second conductivity type different from the first conductivity type by introducing predetermined impurities into both sides of the first region of the first semiconductor layer directly below the gate electrode; The process of
(B4) Injecting impurities into the first region so that a channel of the field effect transistor is formed in the first region at a position away from an interface between the gate insulating film and the first semiconductor layer. And a method of manufacturing a semiconductor device. (A) preparing a substrate having a first conductive type first semiconductor layer formed on an insulating layer;
(B) forming a field-effect transistor in the first semiconductor layer;
The step of forming the field-effect transistor,
(B1) forming a gate insulating film containing a material having a higher dielectric constant than silicon oxide on the first semiconductor layer;
(B2) forming a gate electrode on the gate insulating film;
(B3) forming a second region of a second conductivity type different from the first conductivity type by introducing predetermined impurities into both sides of the first region of the first semiconductor layer directly below the gate electrode; The process of
(B4) Impurities are introduced into the first region so that a channel of the field effect transistor is formed in the first region at a position away from an interface between the gate insulating film and the first semiconductor layer. And a step of
The method of manufacturing a semiconductor device according to claim 1, wherein the first semiconductor layer is formed to have a thickness such that a part of the first region is depleted when the field effect transistor is not operating. (A) preparing a substrate having a first conductive type first semiconductor layer formed on an insulating layer;
(B) forming a field-effect transistor in the first semiconductor layer;
The step of forming the field-effect transistor,
(B1) forming a gate insulating film containing a material having a higher dielectric constant than silicon oxide on the first semiconductor layer;
(B2) forming a gate electrode on the gate insulating film;
(B3) forming a second region of a second conductivity type different from the first conductivity type by introducing predetermined impurities into both sides of the first region of the first semiconductor layer directly below the gate electrode; The process of
(B4) Impurities are introduced into the first region so that a channel of the field effect transistor is formed in the first region at a position away from an interface between the gate insulating film and the first semiconductor layer. And a step of
The method of manufacturing a semiconductor device according to claim 1, wherein the first semiconductor layer is formed so as to completely deplete the first region when the field effect transistor is not operating. Forming a field-effect transistor in a columnar semiconductor layer formed on the insulating layer,
The step of forming the field-effect transistor,
(A) forming the columnar semiconductor layer having a second region on both sides of a first region;
(B) forming a gate insulating film containing a material having a higher dielectric constant than silicon oxide on the surface of the columnar semiconductor layer;
(C) forming a gate electrode via the gate insulating film so as to cover at least a part of the outer periphery of the first region;
(D) introducing an impurity into the first region such that a channel of the field-effect transistor is formed in the first region at a position away from an interface between the gate insulating film and the semiconductor layer. And a method for manufacturing a semiconductor device. (A) a source region and a drain region formed in a first semiconductor layer of a first conductivity type and having a second conductivity type different from the first conductor type;
(B) a second semiconductor layer formed in the first semiconductor layer, sandwiched between the source region and the drain region, and having the second conductivity type;
(C) a gate insulating film formed on the first semiconductor layer and having a higher dielectric constant than silicon oxide;
(D) a gate electrode formed on the second semiconductor layer via the gate insulating film;
When a voltage is applied to the gate electrode, the source region and the drain region are provided at an interface region between the first semiconductor layer and the second semiconductor layer before an interface region between the first semiconductor layer and the gate insulating film. A semiconductor device, wherein a channel that conducts between the semiconductor device and the semiconductor device is formed. (A) an insulating layer;
(B) a first semiconductor layer formed on the insulating layer;
(C) a MISFET formed in the first semiconductor layer;
Has,
The MISFET includes:
(C1) a source region and a drain region formed in the first semiconductor layer from the surface of the first semiconductor layer to the insulating layer;
(C2) a semiconductor layer between the source region and the drain region of the semiconductor layer, which has a lower concentration than the source region and the drain region and has the same conductivity type as the source region and the drain region; A second semiconductor layer formed from the surface of the first semiconductor layer to the insulating layer;
(C3) a gate insulating film formed on the first semiconductor layer and having a higher dielectric constant than silicon oxide;
(C4) a gate electrode formed on the second semiconductor layer via the gate insulating film;
At the time of applying a voltage to the gate electrode, the source region and the drain region are formed at an interface region between the second semiconductor layer and the insulating layer before an interface region between the second semiconductor layer and the gate insulating film. A semiconductor device, wherein a channel for conduction is formed. The semiconductor device according to claim 19,
The semiconductor device according to claim 1, wherein the thickness of the first semiconductor layer is smaller than 50 nm. A MISFET having at least three semiconductor layers formed in a columnar shape,
The MISFET includes:
(A) a source region which is one of the semiconductor layers and includes a bottom surface of the semiconductor layer;
(B) another one layer of the semiconductor layer, including the other bottom surface of the semiconductor layer, and a drain region having the same conductivity type as the source region;
(C) another layer of the semiconductor layer, which is sandwiched between the source region and the drain region, has a lower concentration than the source region and the drain region, and has the same conductivity as the source region and the drain region. A second semiconductor layer of the type;
(D) a gate insulating film formed on the side surface of the semiconductor layer so as to surround the second semiconductor layer and having a higher dielectric constant than silicon oxide;
(E) a gate electrode formed via the gate insulating film;
At the time of applying a voltage to the gate electrode, a channel is formed at the center of the second semiconductor layer prior to the interface region between the second semiconductor layer and the gate insulating film, for conducting the source region and the drain region. A semiconductor device characterized by being performed. 22. The semiconductor device according to claim 19, 20, or 21,
The semiconductor device, wherein the first semiconductor layer is completely depleted when the MISFET is in an OFF state. The semiconductor device according to any one of claims 18 to 22,
The source region and the drain region have a low concentration impurity region and a high concentration impurity region, respectively.
The semiconductor device, wherein the low-concentration impurity region is formed at a position closer to the gate electrode than the high-concentration impurity region. 24. The semiconductor device according to claim 18, wherein said gate electrode is formed of N-type polysilicon or P-type polysilicon. The semiconductor device according to any one of claims 18 to 23,
The semiconductor device according to claim 1, wherein the gate electrode is formed of a film containing any of molybdenum, tungsten, and cobalt. 10. The semiconductor device according to claim 1, wherein the gate insulating film contains any one of aluminum oxide, zirconium oxide, hafnium oxide, titanium oxide, silicon nitride, and tantalum oxide. 11. Semiconductor device. (A) an insulating layer;
(B) a semiconductor layer formed on the insulating layer;
(C) an element isolation region separating the semiconductor layer into a first semiconductor layer of a first conductivity type and a third semiconductor layer of a second conductivity type of the opposite conductivity type;
(D) a first MISFET formed in the first semiconductor layer;
(E) a second MISFET formed in the third semiconductor layer;
Has,
The first MISFET includes:
(D1) a first source region and a first drain region of the second conductivity type formed in the first semiconductor layer;
(D2) a fourth semiconductor layer of the second conductivity type sandwiched between the first source region and the first drain region in the first semiconductor layer;
(D3) a gate insulating film formed on the first semiconductor layer and having a higher dielectric constant than silicon oxide;
(D4) a first gate electrode formed on the fourth semiconductor layer via the gate insulating film;
The second MISFET includes:
(E1) a second source region and a second drain region of the first conductivity type formed in the third semiconductor layer;
(E2) in the second semiconductor layer, a fifth semiconductor layer of the first conductivity type, which is sandwiched between the second source region and the second drain region;
(E3) the gate insulating film formed on the third semiconductor layer;
(E4) a second gate electrode formed on the fifth semiconductor layer via the gate insulating film;
When a voltage is applied to the first gate electrode, the first source region is provided at an interface region between the fourth semiconductor layer and the first semiconductor layer before an interface region between the fourth semiconductor layer and the gate insulating film. A first channel for conducting between the first drain region and the first drain region;
When a voltage is applied to the second gate electrode, the second source region is provided at an interface region between the fifth semiconductor layer and the third semiconductor layer before an interface region between the fifth semiconductor layer and the gate insulating film. A second channel for conducting between the second drain region and the second drain region.

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