KR100305880B1 - Manufacturing method of transistor - Google Patents
Manufacturing method of transistor Download PDFInfo
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- KR100305880B1 KR100305880B1 KR1019980039591A KR19980039591A KR100305880B1 KR 100305880 B1 KR100305880 B1 KR 100305880B1 KR 1019980039591 A KR1019980039591 A KR 1019980039591A KR 19980039591 A KR19980039591 A KR 19980039591A KR 100305880 B1 KR100305880 B1 KR 100305880B1
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- Prior art keywords
- forming
- conductive
- side wall
- layer
- insulating film
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000012535 impurity Substances 0.000 claims abstract description 31
- 239000004065 semiconductor Substances 0.000 claims abstract description 31
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 31
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 22
- 229920005591 polysilicon Polymers 0.000 claims abstract description 17
- 239000004020 conductor Substances 0.000 claims abstract description 15
- 238000000059 patterning Methods 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 10
- 238000009413 insulation Methods 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 239000002019 doping agent Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 39
- 238000010586 diagram Methods 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Abstract
본 발명은 트랜지스터의 제조 방법에 관한 것으로서, 제 1 도전형 반도체기판 상에 게이트산화막, 불순물이 도핑된 다결정실리콘 및 실리사이드층을 순차적으로 형성하고 상기 실리사이드층을 원하는 게이트의 폭보다 작게 패터닝하는 공정과, 상기 실리사이드층의 측면에 도전물질을 이용한 도전측벽을 형성하는 공정과, 상기 다결정실리콘층 상에 상기 실리사이드층 및 도전측벽을 덮는 캡절연막을 형성하고 상기 캡절연막, 다결정실리콘 및 게이트산화막을 패터닝하여 게이트를 형성하는 공정과, 상기 반도체기판에 상기 캡절연막을 마스크로 사용하여 제 2 도전형의 불순물을 저농도로 도핑하여 제 1 불순물영역을 형성하는 공정과, 상기 캡절연막, 게이트 및 게이트산화막의 측면에 절연측벽을 형성하고 상기 반도체기판에 상기 캡절연막 및 절연측벽을 마스크로 사용하여 제 2 도전형의 불순물을 고농도로 도핑하여 제 2 불순물영역을 형성하는 공정을 구비한다. 따라서, 본 발명에 따른 트랜지스터의 게이트는 상부의 폭을 좁게 형성하여 절연측벽이 접촉홀의 형성시에 소정 부분 식각되더라도 상기 접촉홀을 채우는 도전물질과 단락되는 것을 방지할 수 있는 이점이 있다.The present invention relates to a method of manufacturing a transistor, comprising: sequentially forming a gate oxide film, a doped polycrystalline silicon and a silicide layer on a first conductive semiconductor substrate, and patterning the silicide layer to be smaller than a desired gate width; Forming a conductive side wall using a conductive material on a side surface of the silicide layer, and forming a cap insulating layer covering the silicide layer and the conductive side wall on the polysilicon layer, and patterning the cap insulating layer, the polysilicon, and the gate oxide layer. Forming a first impurity region by doping a second conductive dopant at a low concentration using a cap insulating film as a mask on the semiconductor substrate, and forming a first impurity region on the semiconductor substrate; Forming an insulating side wall on the semiconductor substrate; By using the wall as a mask, doping the impurity of the second conductivity type at a high concentration and a step of forming a second impurity region. Therefore, the gate of the transistor according to the present invention has an advantage of forming a narrow width of the upper part to prevent the insulating side wall from being short-circuited with the conductive material filling the contact hole even when a predetermined portion is etched at the time of forming the contact hole.
Description
본 발명의 반도체 장치의 제조 방법에 관한 것으로, 특히, 게이트의 형성시에 실리사이드층의 측벽에 다결정측벽을 형성하여 게이트의 형상을 제어하여 캐패시터 또는 비트 라인과 연결하기 위해 형성하는 플러그와의 단락을 방지할 수 있는 트랜지스터의 제조 방법에 관한 것이다.In particular, the present invention relates to a method for manufacturing a semiconductor device, and more particularly, to form a polycrystalline sidewall at a sidewall of a silicide layer to control a shape of a gate to form a short circuit with a plug formed to be connected to a capacitor or a bit line. A method of manufacturing a transistor that can be prevented.
일반적으로 게이트 전극 재료는 게이트 전극과 동시에 메모리의 워드선과 같은 배선으로도 사용되므로 저항률이 낮은 것이 바람직하다. 특히 미세화, 고집적화에 따라 배선저항, 용량의 증대에 따라 저저항 배선 재료의 개발이 요구되었다.In general, since the gate electrode material is also used as a wiring such as a word line of a memory at the same time as the gate electrode, a low resistivity is preferable. In particular, development of low-resistance wiring materials has been required in accordance with the increase in wiring resistance and capacity due to miniaturization and high integration.
따라서 게이트산화막과 가장 안정한 MOS 특성을 나타내는 다결정실리콘층 상에 실리사이드층을 적층하여 저저항 게이트전극을 형성하여 트랜지스터를 제조하게 되었다.Accordingly, a transistor is manufactured by forming a low resistance gate electrode by laminating a silicide layer on a gate oxide film and a polysilicon layer having the most stable MOS characteristics.
도 1a 내지 도 1b는 종래의 기술에 따른 트랜지스터의 제조 방법을 도시하는 단면 공정도이고 도 2는 종래 기술에 따른 트랜지스터의 문제점을 도시하는 단면도이다.1A to 1B are cross sectional process diagrams illustrating a method of manufacturing a transistor according to the prior art, and FIG. 2 is a cross sectional view showing a problem of the transistor according to the prior art.
종래에는 도 1a에 나타낸 바와 같이 도전형의 갖는, 예를 들어 p형의 반도체기판(11) 상에 게이트산화막(13), 불순물이 도핑된 다결정실리콘(15), 실리사이드(17) 및 캡절연막(19)을 순차적으로 형성하고, 상기 캡절연막(19), 실리사이드(17), 다결정실리콘(15) 및 게이트산화막(13)을 패터닝하여 상기 반도체기판(11)의 소정 부분에 다수 개의 캡절연막(19) 및 게이트산화막(13)을 개재시킨 게이트(15,17)를 형성한다. 그리고, 상기 반도체기판(11)에 상기 캡절연막(19)을 마스크로 사용하여 상기 반도체기판(11)과 도전형이 다른 n형의 불순물을 저농도로 이온주입하여 LDD(Lightly Doped Drain)구조를 형성하는 제 1 불순물영역(21)을 형성한다.1A, a gate oxide film 13, a polycrystalline silicon 15 doped with impurities, a silicide 17, and a cap insulating film are formed on a p-type semiconductor substrate 11 having a conductivity type, as shown in FIG. 19 are sequentially formed, and the cap insulation layer 19, the silicide 17, the polysilicon 15, and the gate oxide layer 13 are patterned to form a plurality of cap insulation layers 19 at predetermined portions of the semiconductor substrate 11. And gates 15 and 17 interposed between the gate oxide film 13 and the gate oxide film 13 are formed. In addition, by using the cap insulating film 19 as a mask on the semiconductor substrate 11, an n-type impurity having a different conductivity type from the semiconductor substrate 11 is ion-implanted at low concentration to form a lightly doped drain (LDD) structure. The first impurity region 21 is formed.
그런 다음, 도 1b와 같이 상기 반도체기판(11) 상에 상기 캡절연막(19)을 덮도록 절연막을 형성하고 상기 절연막을 에치백하여 상기 캡절연막(19), 게이트(17,15) 및 게이트산화막(13)의 측면에 절연측벽(23)을 형성한다. 그리고, 상기 반도체기판(11)에 상기 캡절연막(19) 및 절연측벽(23)을 마스크로 사용하여 상기 반도체기판(11)과 도전형이 다른 n형의 불순물을 고농도로 이온주입하여 소오스/드레인영역으로 사용되는 제 2 불순물영역(25)을 형성하여 게이트(15,17)와 소오스/드레인영역을 포함하는 트랜지스터를 형성한다.Next, as shown in FIG. 1B, an insulating film is formed on the semiconductor substrate 11 to cover the cap insulating film 19, and the insulating film is etched back to form the cap insulating film 19, the gates 17 and 15, and the gate oxide film. The insulating side wall 23 is formed in the side surface of (13). Then, by using the cap insulating film 19 and the insulating side wall 23 as a mask on the semiconductor substrate 11, ion-implanted n-type impurities having a different conductivity type from the semiconductor substrate 11 are ion-infused at a high concentration so as to provide source / drain. A second impurity region 25 used as a region is formed to form a transistor including gates 15 and 17 and a source / drain region.
그리고, 도 2는 상기와 같은 종래의 방법으로 형성한 트랜지스터의 문제점을 나타내기 위한 도면으로서 도 2에 나타낸 바와 같이 상기 반도체기판(11) 상에 상기 캡절연막(19)를 덮도록 층간절연막(27)을 형성한 후, 상기 층간절연막(27)을 패터닝하여 상기 제 2 불순물영역(25)을 노출시키는 접촉홀을 형성하고 상기 접촉홀에 도전물질을 채워 플러그(29)를 형성한 것으로서, 상기의 접촉홀을 형성하기 위한 식각시에 상기 절연측벽(23)도 소정량 식각되어 상기 캡절연막(19) 하부에 실리사이드층(17)의 측면이 노출되고(도 2의 "A"부분) 상기 노출된 실리사이드층(17)의 측면과 상부 비트 라인이나 캐패시터의 연결을 위한 플러그(29)가 단락이 발생하는 문제가 있다.FIG. 2 is a diagram illustrating a problem of a transistor formed by the conventional method as described above. As shown in FIG. 2, the interlayer insulating film 27 covers the cap insulating film 19 on the semiconductor substrate 11. ), The interlayer insulating layer 27 is patterned to form a contact hole exposing the second impurity region 25, and a plug 29 is formed by filling a conductive material in the contact hole. In the etching process for forming the contact hole, the insulating side wall 23 is also etched by a predetermined amount to expose the side surface of the silicide layer 17 under the cap insulating film 19 (the portion “A” in FIG. 2). The plug 29 for connecting the side of the silicide layer 17 and the upper bit line or the capacitor may have a short circuit.
따라서, 본 발명의 목적은 게이트의 형상을 제어하여 불순물영역을 노출시키는 접촉홀의 형성시에 게이트와 접촉홀을 채우는 플러그와의 단락을 방지할 수 있는 트랜지스터의 제조 방법을 제공함에 있다.Accordingly, it is an object of the present invention to provide a method for manufacturing a transistor that can prevent a short circuit between the gate and the plug filling the contact hole when forming the contact hole exposing the impurity region by controlling the shape of the gate.
상기 목적을 달성하기 위한 본 발명의 트랜지스터의 제조 방법은 제 1 도전형 반도체기판 상에 게이트산화막, 불순물이 도핑된 다결정실리콘 및 실리사이드층을 순차적으로 형성하고 상기 실리사이드층을 원하는 게이트의 폭보다 작게 패터닝하는 공정과, 상기 실리사이드층의 측면에 도전물질을 이용한 도전측벽을 형성하는 공정과, 상기 다결정실리콘층 상에 상기 실리사이드층 및 도전측벽을 덮는 캡절연막을 형성하고 상기 캡절연막, 다결정실리콘 및 게이트산화막을 패터닝하여 게이트를 형성하는 공정과, 상기 반도체기판에 상기 캡절연막을 마스크로 사용하여 제 2 도전형의 불순물을 저농도로 도핑하여 제 1 불순물영역을 형성하는 공정과, 상기 캡절연막, 게이트 및 게이트산화막의 측면에 절연측벽을 형성하고 상기 반도체기판에 상기 캡절연막 및 절연측벽을 마스크로 사용하여 제 2 도전형의 불순물을 고농도로 도핑하여 제 2 불순물영역을 형성하는 공정을 구비한다.In order to achieve the above object, a transistor manufacturing method of the present invention sequentially forms a gate oxide film, a doped polycrystalline silicon and a silicide layer on a first conductive semiconductor substrate, and pattern the silicide layer to be smaller than a desired gate width. And forming a conductive side wall using a conductive material on the side of the silicide layer, and forming a cap insulating film covering the silicide layer and the conductive side wall on the polysilicon layer and forming the cap insulating film, the polysilicon, and the gate oxide film. Forming a gate by patterning the semiconductor substrate; forming a first impurity region by doping a second conductive type impurity at low concentration using the cap insulating film as a mask; and forming the cap insulating film, the gate, and the gate. An insulating side wall is formed on the side of the oxide film and the cap is cut on the semiconductor substrate. Using the side wall insulating film and the mask comprises a step of forming a second impurity region by doping impurities of the second conductivity type at a high concentration.
도 1a 내지 도 1b는 종래의 기술에 따른 트랜지스터의 제조 방법을 도시하는 단면 공정도.1A to 1B are cross-sectional process diagrams illustrating a method of manufacturing a transistor according to the prior art.
도 2는 종래의 기술에 따른 트랜지스터에서의 문제점을 도시하는 단면도.2 is a cross-sectional view showing a problem in a transistor according to the prior art.
도 3a 내지 도 3d는 본 발명의 실시 예에 따른 트랜지스터의 제조 방법을 도시하는 단면 공정도.3A to 3D are cross-sectional process diagrams illustrating a method of manufacturing a transistor according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 간단한 설명><Brief description of symbols for the main parts of the drawings>
31 : 반도체기판 33 : 게이트절연막31 semiconductor substrate 33 gate insulating film
35 : 다결정실리콘 37 : 제 1 실리사이드35 polysilicon 37 first silicide
39 : 도전측벽 41 : 캡절연막39: conductive side wall 41: cap insulation film
45 : 절연측벽 47 : 고농도 불순물영역45: insulating side wall 47: high concentration impurity region
이하, 도면을 참고하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the drawings.
도 3a 내지 도 3d는 본 발명의 실시 예에 따른 트랜지스터의 제조 방법을 도시하는 단면 공정도이다.3A to 3D are cross-sectional process diagrams illustrating a method of manufacturing a transistor according to an embodiment of the present invention.
본 방법은 도 3a에 나타낸 바와 같이 도전형의 갖는, 예를 들어 p형의 반도체기판(31) 상에 게이트산화막(33), 불순물이 도핑된 다결정실리콘층(35) 및 실리사이드층(37)을 순차적으로 형성하고 상기 실리사이드층(37)을 원하는 게이트의 폭보다 작게 패터닝한다.3A, the gate oxide film 33, the doped polycrystalline silicon layer 35 and the silicide layer 37 are formed on the p-type semiconductor substrate 31 having a conductivity type, as shown in FIG. It is formed sequentially and the silicide layer 37 is patterned smaller than the width of the desired gate.
다음에, 도 3b와 같이 상기 다결정실리콘층(35) 상에 상기 실리사이드층(37)을 덮도록 실리사이드와 같은 도전물질층을 형성하고 상기 도전물질층을 에치백하여 상기 패터닝된 실리사이드층(37)의 측면에 도전측벽(39)을 형성한다.Next, as shown in FIG. 3B, a conductive material layer such as silicide is formed on the polysilicon layer 35 to cover the silicide layer 37, and the conductive material layer is etched back to form the patterned silicide layer 37. The conductive side wall 39 is formed on the side of the.
그리고, 도 3c에 나타낸 바와 같이 상기 다결정실리콘층(35) 상에 상기 실리사이드층(37) 및 도전측벽(39)을 덮도록 질화막과 같은 절연물질을 증착하고 상기 절연물질의 표면을 CMP하여 캡절연막(41)을 형성한다. 상기 CMP한 캡절연막(41) 상에 상기 실리사이드층(37) 및 도전측벽(39)과 대응하는 부분에 마스크층(도시하지 않음)을 형성하고 상기 마스크층을 마스크로 사용하여 상기 캡절연막(41), 다결정실리콘층(35) 및 게이트산화막(33)을 이방성 식각한 후 상기 마스크층을 제거하여 캡절연막(41) 및 게이트산화막(33)을 갖는 게이트(35,37,39)를 형성한다. 그런 다음, 상기 반도체기판(31)에 상기 캡절연막(41)을 마스크로 사용하여 상기 반도체기판(31)과 도전형이 다른 n형의 불순물을 저농도로 이온주입하여 LDD를 형성하는 제 1 불순물영역(43)을 형성한다.3C, an insulating material such as a nitride film is deposited on the polysilicon layer 35 to cover the silicide layer 37 and the conductive side wall 39, and the surface of the insulating material is CMP to form a cap insulating film. To form 41. A mask layer (not shown) is formed on a portion of the CMP cap insulating film 41 corresponding to the silicide layer 37 and the conductive side wall 39, and the cap insulating film 41 is formed using the mask layer as a mask. ), The polysilicon layer 35 and the gate oxide layer 33 are anisotropically etched, and then the mask layer is removed to form gates 35, 37, and 39 having a cap insulating layer 41 and a gate oxide layer 33. Then, the first impurity region is formed by using the cap insulating film 41 as a mask on the semiconductor substrate 31 to form LDD by ion implantation of n-type impurities having a different conductivity type from the semiconductor substrate 31 at low concentration. To form 43.
다음에는, 도 3d에 나타낸 바와 같이 상기 반도체기판(31) 상에 상기 캡절연막(41)을 덮도록 절연막을 형성하고 상기 절연막을 에치백하여 상기 캡절연막(41), 게이트(35,37,39) 및 게이트산화막(33)의 측면에 절연측벽(45)을 형성한다. 그리고, 상기 반도체기판(31)에 상기 캡절연막(41) 및 절연측벽(45)을 마스크로 사용하여 상기 반도체기판(31)과 도전형이 다른 n형의 불순물을 고농도로 이온주입하여 소오스/드레인영역으로 사용되는 제 2 불순물영역(47)을 형성한다.Next, as shown in FIG. 3D, an insulating film is formed on the semiconductor substrate 31 to cover the cap insulating film 41, and the insulating film is etched back to form the cap insulating film 41 and the gates 35, 37, and 39. And an insulating side wall 45 on the side of the gate oxide film 33. Then, using the cap insulating film 41 and the insulating side wall 45 as a mask on the semiconductor substrate 31, ion-implanted impurities of a different conductivity type from that of the semiconductor substrate 31 are ion-infused at a high concentration, so that the source / drain The second impurity region 47 used as the region is formed.
상술한 바와 같이 본 방법에서는 게이트의 형성시에 실리사이드층의 측면에 도전물질을 이용한 도전측벽을 형성하여 게이트의 형상을 상부로 갈수록 폭이 좁아지게 형성한다.As described above, in the method, a conductive side wall using a conductive material is formed on the side of the silicide layer in forming the gate, so that the shape of the gate becomes narrower toward the top.
따라서, 상기 트랜지스터를 덮는 층간절연막을 형성하고 상기 층간절연막을 패터닝하여 상기 불순물영역을 노출시키는 접촉홀을 형성할 때, 상기 절연측벽이 소정 량 식각되더라도 상부의 게이트 폭이 좁아지도록 형성하여 단락되는 문제를 방지할 수 있게 된다.Therefore, when forming an interlayer insulating film covering the transistor and patterning the interlayer insulating film to form a contact hole for exposing the impurity region, the gate width of the upper portion is narrowed even if the insulating side wall is etched by a predetermined amount, resulting in a short circuit. Can be prevented.
또한, 도시하지 않았지만 상기 게이트를 다결정실리콘 및 실리사이드층을 원하는 게이트 폭보다 작게 패터닝한 후에 상기 다결정실리콘층 및 실리사이드층의 측면에 도전측벽을 형성하는 방법도 같은 효과가 있고, 게이트로 불순물이 도핑된 다결정실리콘층만 사용한다면 상기 다결정실리콘층을 원하는 게이트 폭보다 작게 패터닝한 후에 다결정실리콘층의 측면에 도전측벽을 형성하여도 같은 효과가 있다.Although not shown, a method of forming a conductive sidewall on the sides of the polysilicon layer and the silicide layer after patterning the gate with the polysilicon and silicide layers smaller than the desired gate width has the same effect. If only the polysilicon layer is used, the same effect can be obtained by forming the conductive sidewall on the side of the polysilicon layer after patterning the polysilicon layer smaller than the desired gate width.
따라서, 본 발명에 따른 트랜지스터의 게이트는 상부의 폭을 좁게 형성하여 절연측벽이 접촉홀의 형성시에 소정 부분 식각되더라도 상기 접촉홀을 채우는 도전물질과 단락되는 것을 방지할 수 있는 이점이 있다.Therefore, the gate of the transistor according to the present invention has an advantage of forming a narrow width of the upper part to prevent the insulating side wall from being short-circuited with the conductive material filling the contact hole even when a predetermined portion is etched at the time of forming the contact hole.
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