KR100388222B1 - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

Info

Publication number
KR100388222B1
KR100388222B1 KR10-2000-0063207A KR20000063207A KR100388222B1 KR 100388222 B1 KR100388222 B1 KR 100388222B1 KR 20000063207 A KR20000063207 A KR 20000063207A KR 100388222 B1 KR100388222 B1 KR 100388222B1
Authority
KR
South Korea
Prior art keywords
cap layer
gate
forming
plug
semiconductor substrate
Prior art date
Application number
KR10-2000-0063207A
Other languages
Korean (ko)
Other versions
KR20020032190A (en
Inventor
강전진
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR10-2000-0063207A priority Critical patent/KR100388222B1/en
Publication of KR20020032190A publication Critical patent/KR20020032190A/en
Application granted granted Critical
Publication of KR100388222B1 publication Critical patent/KR100388222B1/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 반도체장치의 제조방법에 관한 것으로 제 1 도전형의 반도체기판 상에 게이트산화막을 개재시켜 게이트와 제 1 캡층을 형성하는 공정과, 상기 게이트 및 제 1 캡층의 측면에 측벽을 형성하는 공정과, 상기 제 1 캡층 상에 제 2 캡층을 형성하는 공정과, 상기 게이트 및 제 1 캡층 사이 뿐만 아니라 상기 측벽이 노출되지 않도록 표면이 상기 제 2 캡층 사이에 위치하는 플러그를 형성하는 공정을 구비한다.The present invention relates to a method for manufacturing a semiconductor device, comprising: forming a gate and a first cap layer through a gate oxide film on a first conductive semiconductor substrate; and forming sidewalls on side surfaces of the gate and the first cap layer. And a step of forming a second cap layer on the first cap layer, and a step of forming a plug having a surface located between the second cap layer so that not only the gate and the first cap layer but also the side wall are not exposed. .

따라서, 플러그 표면적의 증가에 의해 이후에 형성될 다른 플러그 및 비트라인와의 접촉 면적이 증가되어 접촉 저항이 감소되므로 전기적 신호가 지연되는 것을 방지할 수 있다.Accordingly, the increase in the plug surface area increases the contact area with other plugs and bit lines to be formed later, thereby reducing the contact resistance, thereby preventing the electrical signal from being delayed.

Description

반도체장치의 제조방법{Method for fabricating semiconductor device}Method for fabricating semiconductor device

본 발명은 반도체장치의 제조방법에 관한 것으로서, 특히, 셀영역 내의 메모리 소자를 이루는 불순물영역에 플러그를 자기 정렬 접촉되게 형성하는 반도체장치의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which a plug is self-aligned to an impurity region forming a memory element in a cell region.

반도체장치의 집적도가 증가되면서 단위 트랜지스터의 크기가 감소되므로 소오스 및 드레인영역을 이루는 불순물영역의 크기가 감소된다. 그러므로, 불순물영역과 커패시터의 스토리지 전극 및 비트라인을 접촉하기 위한 접촉홀의 크기도 감소되어 종횡비가 증가된다. 이에, 접촉홀의 형성과, 이 접촉홀 내에 커패시터의 스토리지 전극 및 비트라인의 형성하기 어렵다. 특히, 이러한 종횡비의 증가에 의한 문제점은 소자의 크기가 큰 주변회로영역에 형성되는 구동회로소자 보다 소자의 크기가 작은 셀영역 내에 형성되는 메모리소자에서 더 심각하다.As the degree of integration of the semiconductor device increases, the size of the unit transistor decreases, thereby reducing the size of the impurity regions constituting the source and drain regions. Therefore, the size of the contact hole for contacting the impurity region, the storage electrode of the capacitor, and the bit line is also reduced to increase the aspect ratio. As a result, it is difficult to form contact holes and to form storage electrodes and bit lines of capacitors in the contact holes. In particular, the problem caused by the increase in the aspect ratio is more serious in a memory device formed in a cell area having a smaller device size than a driving circuit device formed in a peripheral circuit area having a large device size.

따라서, 셀영역 내에 형성되는 메모리소자의 커패시터의 스토리지 전극 및 비트라인을 형성하기 위해 2개 이상의 접촉홀을 형성하는, 즉, 불순물영역을 노출시키는 하부의 접촉홀에 플러그를 형성하고 상부의 접촉홀에 이 플러그와 연결되게 커패시터의 스토리지 전극 또는 비트라인을 형성하는 기술이 개발되었다. 상기에서 하부 및 상부의 접촉홀을 포함하는 2개 이상의 접촉홀은 통상 1번의 공정에 의해 형성되는 접촉홀 보다 깊이가 감소된다. 그러므로, 접촉홀의 종횡비가 감소되어 형성이 용이할 뿐만 아니라 커패시터의 스토리지 전극 및 비트라인의 형성이 용이해진다.Therefore, two or more contact holes are formed to form the storage electrode and the bit line of the capacitor of the memory device formed in the cell region, that is, a plug is formed in the lower contact hole exposing the impurity region and the upper contact hole is formed. A technology has been developed to form the storage electrodes or bit lines of capacitors in connection with these plugs. In the above, two or more contact holes including lower and upper contact holes are usually reduced in depth than the contact holes formed by one process. Therefore, the aspect ratio of the contact hole is reduced to facilitate the formation, as well as the formation of the storage electrode and the bit line of the capacitor.

도 1a 내지 도 1c는 종래 기술에 따른 반도체장치의 제조방법을 도시하는 공정도이다.1A to 1C are process diagrams illustrating a method for manufacturing a semiconductor device according to the prior art.

도 1a를 참조하면, P형의 반도체기판(11) 상에 STI(Shallow Trench Isolation) 방법에 의해 소자의 활성영역과 필드영역을 한정하는 필드산화막(13)을 형성한다. 상기에서 필드산화막(13)은 LOCOS(Local Oxidation of Silicon) 방법에 의해 형성될 수도 있다.Referring to FIG. 1A, a field oxide film 13 defining an active region and a field region of a device is formed on a P-type semiconductor substrate 11 by a shallow trench isolation (STI) method. The field oxide layer 13 may be formed by a local oxidation of silicon (LOCOS) method.

반도체기판(11)의 활성영역 상에 게이트산화막(15)을 개재시켜 게이트(17)와 캡층(19)을 형성한다. 상기에서 게이트산화막(15)을 반도체기판(11)의 활성영역을 열산화하여 형성한다. 그리고, 게이트산화막(15) 상에 다결정실리콘과 질화실리콘을 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 증착한 후 RIE(Reactive Ion Etch) 등의 이방성 식각을 포함하는 포토리쏘그래피 방법으로 패터닝하여 게이트(17)와 캡층(19)을 형성한다. 상기에서 게이트(17)를 다결정실리콘과 금속의 2중 구조로 형성할 수도 있으며, 캡층(19)을 산화실리콘으로 형성할 수도 있다.The gate 17 and the cap layer 19 are formed through the gate oxide film 15 on the active region of the semiconductor substrate 11. The gate oxide film 15 is formed by thermally oxidizing an active region of the semiconductor substrate 11. Then, photolithography including anisotropic etching of RIE (Reactive Ion Etch) after depositing polycrystalline silicon and silicon nitride on the gate oxide film 15 by chemical vapor deposition (hereinafter referred to as CVD) method. Patterning is done in a manner to form the gate 17 and the cap layer 19. The gate 17 may be formed in a double structure of polycrystalline silicon and a metal, and the cap layer 19 may be formed of silicon oxide.

도 1b를 참조하면, 반도체기판(11) 상에 게이트(17)를 덮도록 CVD 방법으로 질화실리콘을 증착한다. 그리고, 질화실리콘을 반도체기판(11)이 노출되도록 에치백하여 게이트(17) 및 캡층(19)의 측면에 측벽(21)을 형성한다.Referring to FIG. 1B, silicon nitride is deposited by a CVD method to cover the gate 17 on the semiconductor substrate 11. The silicon nitride is etched back to expose the semiconductor substrate 11 to form sidewalls 21 on the side surfaces of the gate 17 and the cap layer 19.

그리고, 반도체기판(11)의 노출된 부분에 N형의 불순물을 이온 주입하여 트랜지스터의 소오스 및 드레인영역이 되는 불순물영역(23)을 형성한다.Then, an N-type impurity is ion-implanted into the exposed portion of the semiconductor substrate 11 to form an impurity region 23 serving as a source and a drain region of the transistor.

도 1c를 참조하면, 상술한 구조 상에 불순물이 도핑된 다결정실리콘을 불순물영역(27)과 접촉되도록 CVD 방법으로 증착한다. 그리고, 다결정실리콘을 캡층(19)이 노출되도록 RIE 방법으로 에치백하거나 또는 CMP(Chemical Mechanical Polishing) 방법으로 연마하여 게이트(17) 및 캡층(19) 사이에만 잔류하도록 한다. 이 때, 잔류하는 다결정실리콘은 플러그(25)가 된다.Referring to FIG. 1C, polycrystalline silicon doped with impurities on the above-described structure is deposited by a CVD method to contact the impurity region 27. Then, the polysilicon is etched back by RIE method or polished by CMP (Chemical Mechanical Polishing) method so that the cap layer 19 is exposed so as to remain only between the gate 17 and the cap layer 19. At this time, the remaining polysilicon becomes the plug 25.

상술한 바와 같이 형성된 플러그는 이 후 공정에서 비트라인과 접촉되거나, 또는, 이후에 형성될 다른 플러그를 통해 커패시터의 스토리지전극과 접촉되어 전기적으로 연결된다.The plug formed as described above is in electrical contact with the bit line in a subsequent process or with the storage electrode of the capacitor via another plug to be formed later.

그러나, 상술한 반도체장치의 제조방법은 플러그를 형성할 때 다결정실리콘이 과도하게 식각 또는 연마되면 측벽에 의해 플러그의 표면적이 감소되어 이후에 형성될 다른 플러그 및 비트라인과의 접촉 저항이 증가되므로 전기적 신호가 지연되는 문제점이 있었다.However, in the above-described method of manufacturing a semiconductor device, when polysilicon is excessively etched or polished when forming a plug, the surface area of the plug is reduced by sidewalls, thereby increasing the contact resistance with other plugs and bitlines to be formed later. There was a problem that the signal is delayed.

따라서, 본 발명의 목적은 플러그의 표면적을 증가시켜 이후에 형성될 다른 플러그 및 비트라인와의 접촉 저항을 감소시키는 반도체장치의 제조방법을 제공함에 있다.Accordingly, it is an object of the present invention to provide a method for manufacturing a semiconductor device which increases the surface area of a plug and reduces the contact resistance with other plugs and bit lines to be formed later.

상기 목적을 달성하기 위한 본 발명에 따른 반도체장치의 제조방법은 제 1 도전형의 반도체기판 상에 게이트산화막을 개재시켜 게이트와 제 1 캡층을 형성하는 공정과, 상기 게이트 및 제 1 캡층의 측면에 측벽을 형성하는 공정과, 상기 제 1 캡층 상에 제 2 캡층을 형성하는 공정과, 상기 게이트 및 제 1 캡층 사이 뿐만 아니라 상기 측벽이 노출되지 않도록 표면이 상기 제 2 캡층 사이에 위치하는 플러그를 형성하는 공정을 구비한다.A semiconductor device manufacturing method according to the present invention for achieving the above object is a step of forming a gate and a first cap layer via a gate oxide film on a first conductive semiconductor substrate, and the side surface of the gate and the first cap layer Forming a side wall, forming a second cap layer on the first cap layer, and forming a plug having a surface located between the second cap layer so that the side wall is exposed as well as between the gate and the first cap layer. It is equipped with the process of doing.

도 1a 내지 도 1c는 종래 기술에 따른 반도체장치의 제조방법을 도시하는 공정도1A to 1C are process diagrams showing a method for manufacturing a semiconductor device according to the prior art.

도 2a 내지 도 2d는 본 발명에 따른 반도체장치의 제조방법을 도시하는 공정도2A to 2D are process drawings showing a method of manufacturing a semiconductor device according to the present invention.

이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2d는 본 발명에 따른 반도체장치의 제조방법을 도시하는 공정도이다.2A to 2D are process diagrams illustrating a method for manufacturing a semiconductor device according to the present invention.

도 2a를 참조하면, P형의 반도체기판(31) 상에 STI(Shallow Trench Isolation) 방법에 의해 소자의 활성영역과 필드영역을 한정하는 필드산화막(33)을 형성한다. 상기에서 필드산화막(33)은 반도체기판(31) 상의 소정 부분을 노출시키는 패드산화막(도시되지 않음) 및 마스크층(도시되지 않음)을 형성하고, 반도체기판(31)의 노출된 부분을 RIE 등의 이방성 식각방법으로 소정 각을 갖는 트렌치(32)를 형성한 후 이 트렌치(32) 내에 산화실리콘을 채우고 마스크층 및 패드산화막을 제거하므로써 형성된다. 상기에서 필드산화막(33)을 STI 방법으로 형성하였으나 LOCOS(Local Oxidation of Silicon) 방법으로 형성할 수도 있다.Referring to FIG. 2A, a field oxide film 33 defining an active region and a field region of an element is formed on a P-type semiconductor substrate 31 by a shallow trench isolation (STI) method. The field oxide film 33 forms a pad oxide film (not shown) and a mask layer (not shown) exposing a predetermined portion on the semiconductor substrate 31, and the exposed portion of the semiconductor substrate 31 is formed by RIE or the like. After forming the trench 32 having a predetermined angle by the anisotropic etching method, the silicon oxide is filled in the trench 32 and the mask layer and the pad oxide film are removed. Although the field oxide layer 33 is formed by the STI method, the field oxide layer 33 may be formed by a local oxide of silicon (LOCOS) method.

반도체기판(31)의 활성영역 상에 게이트산화막(35)을 개재시켜 게이트(37)와 제 1 캡층(39)을 형성한다. 상기에서 게이트산화막(35)을 반도체기판(31)의 활성영역을 열산화하여 형성한다. 그리고, 게이트산화막(35) 상에 다결정실리콘과 질화실리콘을 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 증착한 후 RIE(Reactive Ion Etch) 등의 이방성 식각을 포함하는 포토리쏘그래피 방법으로 패터닝하여 게이트(37)와 제 1 캡층(39)을 형성한다. 상기에서 게이트(37)를 다결정실리콘과 금속의 2중 구조로 형성할 수도 있으며, 제 1 캡층(39)을 산화실리콘으로 형성할 수도 있다.The gate 37 and the first cap layer 39 are formed through the gate oxide film 35 on the active region of the semiconductor substrate 31. The gate oxide film 35 is formed by thermally oxidizing an active region of the semiconductor substrate 31. And, after depositing polysilicon and silicon nitride on the gate oxide film 35 by a chemical vapor deposition (CVD) method, photolithography including anisotropic etching such as reactive ion etching (RIE), etc. Patterning is performed to form the gate 37 and the first cap layer 39. The gate 37 may be formed in a double structure of polycrystalline silicon and a metal, and the first cap layer 39 may be formed of silicon oxide.

도 2b를 참조하면, 반도체기판(31) 상에 질화실리콘 또는 산화실리콘 등의 제 1 캡층(39)과 동일한 절연물질을 게이트(37)을 덮도록 CVD 방법으로 증착한 후 반도체기판(31)이 노출되도록 에치백하여 게이트(37) 및 제 1 캡층(39)의 측면에 측벽(41)을 형성한다.Referring to FIG. 2B, after the same insulating material as the first cap layer 39, such as silicon nitride or silicon oxide, is deposited on the semiconductor substrate 31 by CVD to cover the gate 37, the semiconductor substrate 31 is removed. The back side is etched to form sidewalls 41 on the sides of gate 37 and first cap layer 39.

그리고, 반도체기판(31)의 노출된 부분에 인(P) 또는 아세닉(As) 등의 N형의 불순물을 이온 주입하여 트랜지스터의 소오스 및 드레인영역이 되는 불순물영역(43)을 형성한다.An impurity region 43 serving as a source and a drain region of the transistor is formed by ion-implanting an N-type impurity such as phosphorus (P) or asic (As) in the exposed portion of the semiconductor substrate 31.

도 2c를 참조하면, 상기 제 1 캡층(39) 및 측벽(41)과 식각 선택비가 다른 산화실리콘 또는 질화실리콘으로 이루어진 제 2 캡층(45)을 상기 제 1 캡층(39) 상에 형성한다.Referring to FIG. 2C, a second cap layer 45 formed of silicon oxide or silicon nitride having an etch selectivity different from that of the first cap layer 39 and the sidewall 41 is formed on the first cap layer 39.

상기에서 제 2 캡층(45)을 형성하는 방법은 상술한 구조 상에 제 1 캡층(39) 및 측벽(41)을 덮도록 산화실리콘 또는 질화실리콘 등의 절연 물질을 CVD 방법으로 두껍게 증착한다. 그리고, 절연 물질을 CMP하여 표면을 평탄화시킨 후 게이트(37)와 제 1 캡층(39)을 형성할 때 사용된 동일한 마스크를 사용하는 포토리쏘그래피 방법으로 불순물영역(43)이 노출되도록 패터닝하여 제 1 캡층(39) 상에 제 2 캡층(45)을형성한다.In the method of forming the second cap layer 45, an insulating material such as silicon oxide or silicon nitride is thickly deposited by the CVD method so as to cover the first cap layer 39 and the sidewall 41 on the above-described structure. After the CMP of the insulating material is used to planarize the surface, the impurity region 43 is exposed by photolithography using the same mask used to form the gate 37 and the first cap layer 39. The second cap layer 45 is formed on the first cap layer 39.

도 2d를 참조하면, 상술한 구조 상에 불순물영역(43)과 접촉되고 제 2 캡층(45)을 덮도록 불순물이 도핑된 다결정실리콘을 CVD 방법으로 증착한다. 그리고, 다결정실리콘을 제 2 캡층(45)이 노출되도록 RIE 방법으로 에치백하거나 또는 CMP 방법으로 연마하여 플러그(47)를 형성한다. 상기에서 플러그(47)는 게이트(37) 및 제 1 캡층(39) 사이 뿐만 아니라 제 2 캡층(45) 사이에도 형성된다. 그러므로, 다결정실리콘이 과도하게 식각 또는 연마되더라도 플러그(47)는 표면이 제 2 캡층(45) 사이에 위치되어 측벽(41)이 노출되지 않으므로 표면적이 증가된다.Referring to FIG. 2D, polycrystalline silicon in contact with the impurity region 43 and doped with impurities to cover the second cap layer 45 is deposited by the CVD method. Then, the polysilicon is etched back by the RIE method or polished by the CMP method so as to expose the second cap layer 45 to form the plug 47. In the above, the plug 47 is formed between the second cap layer 45 as well as between the gate 37 and the first cap layer 39. Therefore, even if polysilicon is excessively etched or polished, the plug 47 has an increased surface area since the surface is located between the second cap layers 45 so that the side walls 41 are not exposed.

상술한 플러그(47)는, 도시되지는 않았지만, 이 후 공정에서, 비트라인과 접촉되거나, 또는, 이후에 형성될 다른 플러그를 통해 커패시터의 스토리지전극과 접촉되어 전기적으로 연결된다. 이 때, 플러그(47)의 표면적이 증가되어 있으므로 이후에 형성될 다른 플러그 및 비트라인과 접촉 면적이 증가된다.Although not shown, the plug 47 described above is electrically connected in contact with the bit line or in contact with the storage electrode of the capacitor through another plug to be formed later. At this time, since the surface area of the plug 47 is increased, the contact area with other plugs and bit lines to be formed later is increased.

따라서, 본 발명은 플러그 표면적의 증가에 의해 이후에 형성될 다른 플러그 및 비트라인와의 접촉 면적이 증가되어 접촉 저항이 감소되므로 전기적 신호가 지연되는 것을 방지할 수 있는 잇점이 있다.Therefore, the present invention has the advantage that the electrical resistance can be prevented from being delayed because the contact area with other plugs and bit lines to be formed later is increased by the increase of the plug surface area, thereby reducing the contact resistance.

Claims (4)

제 1 도전형의 반도체기판 상에 게이트산화막을 개재시켜 게이트와 제 1 캡층을 형성하는 공정과,Forming a gate and a first cap layer through a gate oxide film on the first conductive semiconductor substrate; 상기 게이트 및 제 1 캡층의 측면에 측벽을 형성하는 공정과,Forming sidewalls on side surfaces of the gate and the first cap layer; 상기 제 1 캡층 상에 제 2 캡층을 형성하는 공정과,Forming a second cap layer on the first cap layer; 상기 측벽과 상기 제 2 캡층의 측면이 노출되지 않도록, 상기 제 2 캡층 사이에 상부표면이 위치하는 플러그를 형성하는 공정을 포함하여 구성되는 것을 특징으로 하는 반도체장치의 제조방법.And forming a plug having an upper surface located between the second cap layer so that the side wall and the side surface of the second cap layer are not exposed. 삭제delete 제 1 항에 있어서, 상기 제 2 캡층은, 상기 반도체기판 상에 상기 제 1 캡층을 덮도록 절연 물질을 증착하고 평탄화한 후 상기 게이트 및 제 1 캡층을 형성할 때 사용된 동일한 마스크를 사용하는 포토리쏘그래피 방법으로 패터닝하여 형성되는 것을 특징으로 하는 반도체장치의 제조방법.The photovoltaic device of claim 1, wherein the second cap layer is formed by depositing and planarizing an insulating material to cover the first cap layer on the semiconductor substrate, and then using the same mask used to form the gate and the first cap layer. A method for manufacturing a semiconductor device, characterized in that it is formed by patterning by lithography. 제 3 항에 있어서, 상기 절연물질은 RIE(Reactive Ion Etch) 방법으로 에치백하거나 또는 CMP(Chemical Mechanical Polishing) 방법으로 연마하여 평탄화되는 것을 특징으로 하는 반도체장치의 제조방법.The method of claim 3, wherein the insulating material is etched back using a reactive ion etching (RIE) method or planarized by grinding by a chemical mechanical polishing (CMP) method.
KR10-2000-0063207A 2000-10-26 2000-10-26 Method for fabricating semiconductor device KR100388222B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR10-2000-0063207A KR100388222B1 (en) 2000-10-26 2000-10-26 Method for fabricating semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR10-2000-0063207A KR100388222B1 (en) 2000-10-26 2000-10-26 Method for fabricating semiconductor device

Publications (2)

Publication Number Publication Date
KR20020032190A KR20020032190A (en) 2002-05-03
KR100388222B1 true KR100388222B1 (en) 2003-06-19

Family

ID=19695583

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2000-0063207A KR100388222B1 (en) 2000-10-26 2000-10-26 Method for fabricating semiconductor device

Country Status (1)

Country Link
KR (1) KR100388222B1 (en)

Also Published As

Publication number Publication date
KR20020032190A (en) 2002-05-03

Similar Documents

Publication Publication Date Title
KR100299342B1 (en) A process for forming a high density semiconductor device
US8053307B2 (en) Method of fabricating semiconductor device with cell epitaxial layers partially overlap buried cell gate electrode
US6255160B1 (en) Cell design and process for making dynamic random access memory (DRAM) having one or more Gigabits of memory cells
US6333274B2 (en) Method of manufacturing a semiconductor device including a seamless shallow trench isolation step
US5858829A (en) Method for fabricating dynamic random access memory (DRAM) cells with minimum active cell areas using sidewall-spacer bit lines
KR100268427B1 (en) Method for forming of contact of semiconductor device
US5837577A (en) Method for making self-aligned node contacts to bit lines for capacitor-over-bit-line structures on dynamic random access memory (DRAM) devices
US6037211A (en) Method of fabricating contact holes in high density integrated circuits using polysilicon landing plug and self-aligned etching processes
US6010933A (en) Method for making a planarized capacitor-over-bit-line structure for dynamic random access memory (DRAM) devices
US6403416B1 (en) Method for making a double-cylinder-capacitor structure for dynamic random access memory (DRAM)
US6159808A (en) Method of forming self-aligned DRAM cell
KR100335121B1 (en) Semiconductor memory device and method for fabricating the same
US6228736B1 (en) Modified method for forming cylinder-shaped capacitors for dynamic random access memory (DRAM)
KR100318320B1 (en) Method for fabricating semiconductor device
KR20030001827A (en) Fabrication method of semiconductor device having dual gate oxide layer
US6107155A (en) Method for making a more reliable storage capacitor for dynamic random access memory (DRAM)
KR100388222B1 (en) Method for fabricating semiconductor device
KR100376868B1 (en) Method for fabricating semiconductor device
KR100348315B1 (en) Method for Fabricating of Semiconductor Device
KR100430556B1 (en) Method for forming bit line semiconductor device
KR100372637B1 (en) Method for fabricating semiconductor device
KR20010008589A (en) Method of forming bit-line of semiconductor device utilized damascene process
KR100589498B1 (en) Method of manufacturing semiconductor device
KR100910221B1 (en) Method for manufacturing storage node contact in semiconductor device
KR100269629B1 (en) Method for fabricating semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20110526

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee