KR20060014672A - Semiconductor devices employing mos transistors having recessed channel regions and methods of fabricating the same - Google Patents

Abstract

Provided are semiconductor devices employing MOS transistors having recessed channel regions, and methods of fabricating the same. The semiconductor devices include a semiconductor substrate and an isolation layer formed in a predetermined region of the semiconductor substrate to define an active region. A channel trench region recessed in the active region is provided. A first gate electrode is provided across the top of the active region while filling the recessed channel trench region. The lower region of the first gate electrode is self-aligned with the channel trench region to have the same width as the channel trench region, and the upper region of the first gate electrode has a larger width than the lower region thereof. A second gate electrode is provided adjacent to the first gate electrode and across the device isolation layer. The lower region of the second gate electrode has a narrower width than the upper region of the second gate electrode. Surfaces of the first and second gate electrodes are covered by passivation patterns. An interlayer insulating film is provided on the semiconductor substrate having the protective layer patterns, and the active region between the first and second gate electrodes is exposed by a self-aligning contact hole penetrating the interlayer insulating film. The lower region of the self-aligned contact hole has a width larger than that of the upper region. The self-aligned contact hole is filled with a contact pad. Methods of forming the semiconductor devices are also provided.

Description

Semiconductor devices employing MOS transistors having recessed channel regions and methods of fabricating the same

1A and 1B are cross-sectional views illustrating methods of manufacturing conventional DRAM cell transistors having recessed channel regions.

2A to 2L are cross-sectional views illustrating MOS transistors and a method of manufacturing the same according to embodiments of the present invention.

3A to 3E are cross-sectional views illustrating semiconductor devices employing MOS transistors and fabrication methods thereof according to embodiments of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices and methods of manufacturing the same, and more particularly to semiconductor devices and methods of manufacturing the same employing MOS transistors having recessed channel regions.

As the degree of integration of semiconductor memory devices such as DRAM devices increases, the area occupied by MOS transistors decreases. As a result, the gate length (channel length) is drastically reduced to generate a short channel effect. In order to suppress the short channel effect, the channel ion implantation amount may be increased. However, an increase in channel ion implantation results in an increase in junction leakage current. In DRAM, an increase in the junction leakage current (particularly, an increase in the cell junction leakage current) results in a decrease in the data retention time. As a result, the refresh cycle must be reduced, and the reduction of the refresh cycle leads to an increase in power consumption. In order to solve the above problems, a MOS transistor having a recessed channel region has been proposed.

1A and 1B are cross-sectional views illustrating methods of manufacturing conventional DRAM cells employing a MOS transistor having the recessed channel regions as a cell transistor.

Referring to FIG. 1A, a field oxide film 12 is formed in a predetermined region of a semiconductor substrate 10 to define an active region. The field oxide layer 12 serves to isolate individual elements such as MOS transistors from each other. The channel trenches 14 may be formed by selectively etching predetermined regions of the active region. A gate oxide layer 16 is formed on the active region having the channel trenches 14, and a polysilicon layer 18 is formed on the entire surface of the semiconductor substrate having the gate oxide layer 16.

The metal silicide layer 20 and the gate capping layer 22 are sequentially formed on the polysilicon layer 18. The metal silicide film 20 is formed to reduce the electrical resistance of the polysilicon film 18. In general, the metal silicide layer 20 is formed of a tungsten silicide layer, and the gate capping layer 22 is formed of a silicon nitride layer.

Referring to FIG. 1B, the gate capping layer 22 is patterned to form gate capping layer patterns 52 covering predetermined regions of the metal silicide layer 20. The metal silicide layer 20, the polysilicon layer 18, and the gate oxide layer 16 are sequentially etched using the gate capping layer patterns 52 as an etch mask, and the upper portions of the channel trench regions 14 may be etched. Gate electrodes 60 are formed across the gaps. As a result, each of the gate electrodes 60 may include a polysilicon pattern 48 and a metal silicide pattern 50 sequentially stacked. Gate spacers 70 are formed on sidewalls of the gate electrodes 60 and the gate capping layer patterns 52. Next, an etch stop layer 80 and an interlayer insulating layer 90 are sequentially formed on the entire surface of the semiconductor substrate including the gate spacers 70 and the gate capping layer patterns 52.

The interlayer insulating layer 90 and the etch stop layer 80 are patterned to form self-aligning contact holes 91 exposing the semiconductor substrate 10 between the gate electrodes 60. The self-aligned contact holes 91 are formed using the gate spacers 70 as an etch stop layer. After stacking a conductive film on the substrate having the self-aligned contact holes 91, the conductive film is planarized to form contact pads 92 separated from each other in the self-aligned contact holes 91. The contact surface between the contact pads 92 and the active region is as wide as "S". The width S is directly related to the contact resistance of the contact pads 92.                         

If misalignment occurs during the photolithography process for patterning the gate electrodes (ie, the gate capping layer patterns), the width of any one of the contact surfaces between the contact pads 92 and the active region ( S) may decrease. In this case, the contact pads 92 exhibit non-uniform contact resistance, and such non-uniform contact resistance deteriorates the characteristics of DRAM cells.

Self-aligned contacts are introduced in US Pat. Nos. 4,453,306 and 4,691,219.

SUMMARY OF THE INVENTION The present invention aims to prevent the contact area of a self-aligned contact pad adjacent to the gate electrode from changing even if misalignment occurs during the photolithography process for patterning the gate electrode on the recessed channel region. To provide a semiconductor device suitable for.

In addition, another technical object of the present invention is to uniformize the contact area of the self-aligned contact pad adjacent to the gate electrode even if misalignment occurs during the photolithography process for patterning the gate electrode on the recessed channel region. To provide a method for manufacturing a semiconductor device that can be controlled easily.

According to one aspect of the present invention, there are provided semiconductor devices employing a MOS transistor having a recessed channel. The semiconductor devices include a semiconductor substrate and an isolation layer formed in a predetermined region of the semiconductor substrate to define an active region. A recessed channel region is provided in the active region. The recessed channel region crosses the active region. A first gate electrode is disposed to cross the top of the active region while filling the recessed channel trench region. The lower region of the first gate electrode is self-aligned with the channel trench region to have the same width as the channel trench region, and the upper region of the first gate electrode has a larger width than the lower region. A second gate electrode is disposed to be adjacent to the first gate electrode and to cross the upper portion of the device isolation layer. The bottom width of the second gate electrode is narrower than its top width. Surfaces of the first and second gate electrodes are covered by passivation patterns. An interlayer insulating film is provided on the semiconductor substrate having the protective film patterns. The active region between the first and second gate electrodes is exposed by a self-aligned contact hole penetrating the interlayer insulating layer. The width of the lower region of the self-aligned contact hole is larger than the width of the upper region of the self-aligned contact hole. The self-aligned contact hole is filled with a contact pad.

In some embodiments, the interlayer insulating layer may be a material layer having an etching selectivity with respect to the passivation layer pattern.

In example embodiments, the passivation layer patterns may include trench spacers covering sidewalls of lower regions of the gate electrodes, gate capping layer patterns stacked on the upper regions of the gate electrodes, and sidewalls of the upper regions of the gate electrodes. And gate spacers covering sidewalls of the gate capping layer patterns. The gate spacers are connected to upper regions of the trench spacers.                     

In still other embodiments, the upper regions of the gate electrodes may include a polysilicon layer and a metal silicide layer that are sequentially stacked. In this case, the lower regions of the gate electrodes may extend from the polysilicon film.

In other embodiments, the self-aligned contact hole may expose the passivation pattern.

According to another aspect of the present invention, methods of manufacturing a semiconductor device employing a MOS transistor having a recessed channel are provided. These methods include forming an isolation layer in a predetermined region of a semiconductor substrate to define an active region. A molding film is formed on the semiconductor substrate having the active region. The molding layer is formed to have first and second openings crossing the active region and the upper portion of the device isolation layer, respectively. Trench spacers are formed on sidewalls of the openings. The active region is etched using the trench spacers and the molding layer as an etch mask to form a channel trench region in the active region below the first opening. A gate conductive layer and a gate capping layer that fill the openings and the channel trench region are sequentially formed on the molding layer. The gate capping layer and the gate conductive layer are patterned to form first and second gate patterns respectively covering the first and second openings. The molding layer is selectively isotropically etched to expose the upper regions of the trench spacers. Gate spacers may be formed to cover sidewalls of the gate patterns and may be connected to the exposed trench spacers. An interlayer insulating film is formed on the semiconductor substrate having the gate spacers. The interlayer insulating layer and the molding layer are patterned to form a self-aligning contact hole exposing an active region between the first and second gate patterns. A contact pad is formed to fill the self-aligned contact hole.

In some embodiments, the trench spacers may be formed of an insulating layer having an etch selectivity with respect to the molding layer.

In other embodiments, the gate capping layer may be formed of an insulating layer having an etch selectivity with respect to the molding layer.

In still other embodiments of the present invention, the gate spacers may be formed of an insulating layer having an etch selectivity with respect to the molding layer.

In another embodiment of the present invention, forming the self-aligned contact hole may be performed by etching the interlayer insulating layer and the molding layer using the patterned gate capping layer and the gate spacers as etching masks. The method may include forming a preliminary self-aligned contact hole passing between the two gate patterns, and cleaning the surface of the substrate having the preliminary self-aligned contact hole to expose the trench spacers.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiments introduced below are provided to sufficiently convey the spirit of the present invention to those skilled in the art. Accordingly, the present invention may be embodied in other forms without being limited to the embodiments described below. In the drawings, lengths, thicknesses, and the like of layers and regions may be exaggerated for convenience of description. Like numbers refer to like elements throughout the specification.                     

2A to 2L are cross-sectional views illustrating MOS transistors and methods of fabricating the same according to embodiments of the present invention.

Referring to FIG. 2A, an isolation layer 110 is formed in a predetermined region of the semiconductor substrate 100 to define an active region A and an isolation region I. The device isolation layer 110 may be formed using trench device isolation technology. The impurity regions 112 are formed by implanting impurity ions into the active region. The impurity region 112 may be formed to have a different conductivity type from that of the semiconductor substrate 100. For example, when the semiconductor substrate 100 is a P-type semiconductor substrate, the impurity region 112 may be doped with N-type impurities. The molding film 115 is formed on the substrate having the impurity region 112. The molding layer 115 may be formed of a silicon oxide layer.

Referring to FIG. 2B, the molding layer 115 is patterned to be positioned at both sides of the pair of first openings 120 and the active region A crossing the upper portion of the active region A. A pair of second openings 120 ′ that cross the upper portion of the device isolation layer 110 is formed. The first openings 120 and the second openings 120 ′ may be formed to be parallel to each other. An insulating film is formed on the substrate having the openings 120 and 120 ', and the trench spacers 130 are formed on the sidewalls of the openings 120 and 120' by etching back the insulating film. Form. The insulating layer for forming the trench spacers 130 may be formed of a material layer having an etch selectivity with respect to the molding layer 115. For example, the trench spacers 130 may be formed of silicon nitride (SiN).                     

Referring to FIG. 2C, a pair of cross-sections of the active region A may be selectively etched using the molding layer 115 and the trench spacers 130 as etching masks. Channel trench regions 140 are formed. The channel trench regions 140 are formed deeper than the impurity region 112. As a result, the impurity region 112 may include the first drain and the remaining portions at both ends of the active region A, as well as the common drain region 112d remaining between the pair of channel trench regions 140. And divided into two source regions 112s' and 112s ". The channel trench regions 140 define recessed channel regions. The surfaces of the channel trench regions 140 may be wet or dry cleaned. The wet cleaning process may be performed using a mixed solution of ammonium hydroxide (NH ₄ OH), hydrogen peroxide (H ₂ O ₂ ) and deionized water (H ₂ O). Lower corner portions of the channel trench regions 140 may be modified to have a rounded profile by the cleaning process.

Referring to FIG. 2D, a gate insulating layer 145 is formed on inner walls of the channel trench regions 140. The gate insulating layer 145 may be formed by thermally oxidizing a substrate having the channel trench regions 140.

Referring to FIG. 2E, a gate conductive layer may be formed on the substrate having the gate insulating layer 145 to fill the channel trench regions 140 and the openings 120 and 120 ′. The gate conductive layer may be formed by sequentially stacking the polysilicon layer 150 and the metal silicide layer 160. In this case, the polysilicon layer 150 may be formed to fill the channel trench regions 140 and the openings 120 and 120 ′. The metal silicide layer 160 may be formed of a tungsten silicide layer. A gate capping layer 170 is formed on the metal silicide layer 160. The gate capping layer 170 may be formed of a material layer having an etch selectivity with respect to the molding layer 115. For example, the gate capping layer 170 may be formed of silicon nitride (SiN).

Referring to FIG. 2F, the gate capping layer 170 is patterned, and the pair of gate capping layer patterns 171 crossing the upper portion of the active region A and the sides of the active region A, respectively. Another pair of gate capping layer patterns 171 may be formed. The metal silicide layer 160 and the polysilicon layer 150 are sequentially etched using the gate capping layer patterns 171 as etching masks to cross the upper portion of the active region A. A pair of second gate electrodes 250 ′ crossing the first gate electrodes 250 and the device isolation layer 110 is formed. That is, the pair of first parallel gate patterns 260 and the second openings 120 ′ covering the first openings 120 by patterning the gate capping layer 170 and the gate conductive layer may be formed. A pair of covering second parallel gate patterns 260 'is formed. As a result, each of the gate electrodes 250 and 250 ′ may include a polysilicon pattern 151 and a metal silicide pattern 161 sequentially stacked.

The gate electrodes 250 and 250 ′ are formed to have lower regions filling the openings 120 and 120 ′ and upper regions protruding from an upper surface of the molding layer 115. As a result, each of the upper regions may include a polysilicon pattern 151 and a metal silicide pattern 161 that are sequentially stacked, and each of the lower regions extends from the polysilicon pattern 151 and is formed in the trench spacer. It may have a form surrounded by (130). As shown in FIG. 2F, the lower regions may be self-aligned with the channel trench regions 140 to have the same width as the channel trench regions 140. In addition, the upper regions may have a larger width than the lower regions.

2G and 2H, the molding layer 115 is isotropically etched to expose the upper regions of the trench spacers 130. An insulating film is laminated on the entire surface of the substrate having the isotropically etched molding film 115. Subsequently, upper regions of the trench spacers 130 may be etched back to cover sidewalls of the gate capping layer patterns 171 and sidewalls of upper regions of the gate electrodes 250 and 250 ′. The gate spacers 180 are connected to the gate spacers 180. In other words, the gate spacers 180 are formed on sidewalls of the polysilicon pattern 151, the metal silicide pattern 161, and the gate capping layer pattern 171. The gate spacers 180 may be formed of a material layer having an etch selectivity with respect to the molding layer 115. For example, the gate spacers 180 may be formed of silicon nitride (SiN).

Meanwhile, when the impurity region 112 illustrated in FIG. 2A is a low concentration impurity region, the semiconductor substrate may be formed using the gate spacers 180 and the gate capping layer patterns 171 as ion implantation masks. High concentration source / drain regions (not shown) may be formed by further implanting impurity ions into the active region A of 100.

2I and 2J, an interlayer insulating layer 190 is formed on a substrate having the gate spacers 180. The interlayer insulating layer 190 may be formed of a material layer having an etch selectivity with respect to the gate capping layer patterns 171 and the gate spacers 180. For example, the interlayer insulating layer 190 may be formed of an oxide film such as BPSG, BSG, TEOS, or USG. The interlayer insulating layer 190 and the molding layer 115 are etched using the gate capping layer patterns 171 and the gate spacers 180 as etching masks to form the gate patterns 260 and 260 ′. Preliminary self-aligning contact holes are formed to penetrate the regions therebetween and expose the common drain region 112d, the first source region 112s ′, and the second source region 112s ″.

The surface of the substrate having the preliminary self-aligned contact holes is cleaned using a wet process or a dry process to form final self-aligned contact holes 200. The cleaning process may be performed using the trench spacers 130 and the gate spacers 180 as an etch stop layer. As a result, the self-aligned contact holes 200 may be extended to completely expose the trench spacers 130. That is, the lower regions of the self-aligned contact holes 200 extend to be wider than their upper regions. In other words, the self-aligned contact holes 200 are formed to have lower regions 201 extending thereunder, such that the common drain region 112d, the first source region 112s ′, and the second source are formed. The exposed areas of region 112s "can be maximized. The wet process uses a mixture of ammonium hydroxide (NH ₄ OH), hydrogen peroxide (H ₂ O ₂ ) and deionized water (H ₂ O ₂ ). It can be carried out by.

Referring to FIG. 2K, a conductive film may be formed on the entire surface of the semiconductor substrate including the contact holes 200 to fill the contact holes 200. The conductive film may be formed of a dope polysilicon film. The doped polysilicon film may be formed using an in-situ process. That is, the doped polysilicon film may be formed by implanting dopants such as phosphorous (P) during the deposition of the polysilicon film. Subsequently, the conductive layer is planarized until the upper surface of the interlayer insulating layer 190 is exposed to form contact pads 210 isolated from each other in the contact holes 200. In this case, the extended portions 201 of FIG. 2J of the contact holes 200 may also be filled with the conductive layer to form horizontal extensions 211 of the contact pads 210. As a result, the width S of the contact surfaces between the horizontal extensions 211 and the source / drain regions 112s ', 112s ", and 112d is the gate electrodes 250 and 250' as shown in FIG. ) Can always be constant regardless of misalignment.

3A to 3E are cross-sectional views illustrating semiconductor devices and methods of fabricating the same according to still other embodiments of the inventive concept.

Referring to FIG. 3A, the device isolation layer 110 is formed in a predetermined region of the semiconductor substrate 100 having the cell region C and the peripheral region P, respectively, in the cell region C and the peripheral region P, respectively. Define the cell active area and the peripheral active area. The molding layer 115 is formed on the entire surface of the substrate having the device isolation layer 110. The molding layer 115 is patterned to form first openings 120 and second openings 120 ′ in the cell region C. Trench spacers 130 are formed on sidewalls of the openings 120 and 120 ′. The molding layer 115, the openings 120 and 120 ′ and the trench spacers 130 may be formed using the same methods as the embodiments described with reference to FIGS. 2A and 2B.

The cell active region is etched using the molding layer 115 and the trench spacers 130 as etching masks to form channel trench regions 140 crossing the cell active region.

Referring to FIG. 3B, a photoresist pattern (not shown) covering the cell region C is formed on a substrate having the channel trench regions 140, and the photoresist pattern is used as an etching mask. The molding layer 115 is selectively etched to expose the device isolation layer 110 and the peripheral active region in the peripheral region P. FIG. Subsequently, the photoresist pattern is removed.

Referring to FIG. 3C, after removing the photoresist pattern, a gate insulating layer 145 is formed on inner walls of the channel trench regions 140 and surfaces of the peripheral active region. The gate insulating layer 145 may also be formed using the same method as the embodiments described with reference to FIG. 2D. A gate conductive layer and a gate capping layer 170 that fill the openings 120 and 120 ′ and the channel trench regions 140 are sequentially formed on the substrate having the gate insulating layer 145. The gate conductive layer may be formed by sequentially stacking the polysilicon layer 150 and the metal silicide layer 160 as described with reference to FIG. 2E, and the gate capping layer 170 is also described with reference to FIG. 2E. It can be formed using the same methods as the embodiments.

Referring to FIG. 3D, the gate capping layer 170, the metal silicide layer 160, and the polysilicon layer 150 are successively patterned to form gates having the same shapes as those shown in FIG. 2F in the cell region C. Electrodes and gate capping layer patterns 171 are formed. That is, each of the gate electrodes may be formed to have the polysilicon pattern 151 and the metal silicide pattern 161 stacked in sequence. While the polysilicon patterns 151, the metal silicide patterns 161, and the gate capping layer patterns 171 are formed in the cell region C, a peripheral gate pattern crossing the upper portion of the peripheral active region is simultaneously formed. Can be formed. As a result, the peripheral gate pattern may be formed to have the peripheral polysilicon pattern 152, the peripheral metal silicide pattern 162, and the peripheral gate capping layer pattern 172 sequentially stacked.

After forming the cell gate patterns and the peripheral gate pattern, the molding layer 115 is isotropically etched to expose the upper regions of the trench spacers 130. After isotropic etching of the molding layer 115, cell gate spacers 180 and peripheral gate spacers 181 are formed on sidewalls of the cell gate patterns and sidewalls of the peripheral gate pattern, respectively. The gate spacers 180 and 181 may be formed using the same methods as the embodiments described with reference to FIG. 2H.

After the gate spacers 180 and 181 are formed, they are elevated using a selective epitaxial growth (SEG) technique on the peripheral active region on either side of the peripheral gate pattern. Source / drain regions 220 may be formed. Subsequently, a source / drain metal silicide layer 230 may be further formed on the raised source / drain regions 220 using a salicide (self-aligned silicide) technique.

Referring to FIG. 3E, an interlayer insulating layer 190 is formed on a substrate having the source / drain metal silicide layer 230. The interlayer insulating layer 190 may be formed using the same methods as the embodiments described with reference to FIG. 2I. That is, the interlayer insulating layer 190 is formed of a material layer having an etch selectivity with respect to the gate capping layer patterns 171 and 172 and the gate spacers 180 and 181. Subsequently, the interlayer insulating layer 190 and the molding layer 115 are patterned to form self-aligned contact holes 200 exposing the cell active regions between the cell gate patterns, and the self-aligned contact holes. Form contact pads 210 that fill 200. The self-aligned contact holes 200 and the contact pads 210 may be formed using the same methods as the embodiments described with reference to FIGS. 2J and 2K.

As described above, according to the exemplary embodiments of the present invention, a gate electrode having a self-aligned lower region is formed in the recessed channel trench region using the molding layer. Therefore, even if misalignment occurs in the photolithography process for forming the upper region of the gate electrode, the width of the interface between the contact pads between the gate electrodes and the impurity regions contacting them is equal to the upper region of the gate electrode. It can always be constant regardless of misalignment of.

Claims (10)

Semiconductor substrates; An isolation layer formed in a predetermined region of the semiconductor substrate to define an active region; A recessed channel trench region formed in the active region and crossing the active region; Fills the recessed channel trench region while crossing the top of the active region, its lower region self-aligned with the channel trench region to have the same width as the channel trench region and its upper region being the lower region A first gate electrode having a greater width; A second gate electrode adjacent to the first gate electrode and crossing the upper portion of the device isolation layer, wherein the lower width thereof is narrower than the upper width thereof; Passivation patterns covering surfaces of the first and second gate electrodes; An interlayer insulating film stacked on the semiconductor substrate having the protective film patterns; A self-aligning contact hole penetrating the interlayer insulating film to expose the active region between the first and second gate electrodes, wherein a width of the lower region is larger than a width of the upper region; And And a contact pad filling the self-aligned contact hole. The method of claim 1, And the interlayer dielectric layer is a material layer having an etch selectivity with respect to the passivation layer pattern. The method of claim 1, wherein the protective layer patterns Trench spacers covering sidewalls of the lower regions of the gate electrodes; Gate capping layer patterns stacked on the upper regions of the gate electrodes; And And gate spacers covering sidewalls of the upper regions of the gate electrodes and sidewalls of the gate capping layer patterns and connected to upper regions of the trench spacers. The method of claim 1, And the upper regions of the gate electrodes include a polysilicon layer and a metal silicide layer that are sequentially stacked, and the lower regions of the gate electrodes extend from the polysilicon layer of the upper regions. The method of claim 1, The self-aligning contact hole exposes the protective layer pattern. Forming an isolation layer in a predetermined region of the semiconductor substrate to define an active region; A molding film is formed on the semiconductor substrate having the active area, wherein the molding film is formed to have first and second openings crossing the top of the active area and the device isolation layer, respectively. Forming trench spacers on sidewalls of the openings, Etching the active region using the trench spacers and the molding layer as an etch mask to form a channel trench region in the active region below the first opening; A gate conductive layer and a gate capping layer that sequentially fill the openings and the channel trench region are formed on the molding layer, Patterning the gate capping layer and the gate conductive layer to form first and second gate patterns respectively covering the first and second openings, Selectively isotropically etching the molding layer to expose the upper regions of the trench spacers, Forming gate spacers covering sidewalls of the gate patterns and connected to the exposed trench spacers, An interlayer insulating film is formed on the semiconductor substrate having the gate spacers; Patterning the interlayer insulating layer and the molding layer to form a self-aligning contact hole exposing an active region between the first and second gate patterns; Forming a contact pad filling the self-aligned contact hole. The method of claim 6, And the trench spacers are formed of an insulating layer having an etch selectivity with respect to the molding layer. The method of claim 6, And the gate capping layer is formed of an insulating layer having an etch selectivity with respect to the molding layer. The method of claim 6, And the gate spacers are formed of an insulating layer having an etch selectivity with respect to the molding layer. 7. The method of claim 6, wherein forming the self-aligned contact hole Etching the interlayer insulating layer and the molding layer using the patterned gate capping layer and the gate spacers as etch masks to form a preliminary self-aligning contact hole passing between the first and second gate patterns, Cleaning the surface of the substrate having the preliminary self-aligned contact hole to expose the trench spacers.

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