KR20020010793A - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor device Download PDFInfo
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- KR20020010793A KR20020010793A KR1020000044273A KR20000044273A KR20020010793A KR 20020010793 A KR20020010793 A KR 20020010793A KR 1020000044273 A KR1020000044273 A KR 1020000044273A KR 20000044273 A KR20000044273 A KR 20000044273A KR 20020010793 A KR20020010793 A KR 20020010793A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000010410 layer Substances 0.000 claims abstract description 76
- 125000006850 spacer group Chemical group 0.000 claims abstract description 46
- 230000002093 peripheral effect Effects 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 25
- 239000011229 interlayer Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 18
- 239000000126 substance Substances 0.000 claims abstract description 9
- 229920005591 polysilicon Polymers 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims description 9
- 238000007517 polishing process Methods 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 4
- 238000003860 storage Methods 0.000 claims description 3
- 238000005498 polishing Methods 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract 10
- 238000002955 isolation Methods 0.000 description 5
- 150000002500 ions Chemical group 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 접합영역에 직접 접촉되는 콘택패드를 소오스/드레인영역에 형성하되, 게이트전극의 측벽에도 상기 콘택패드를 형성함으로써 후속 콘택공정에서 오버랩 마진(overlap margin)을 확보하고, 식각공정에서의 손상(damage)을 최소화하는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and in particular, a contact pad in direct contact with a junction region is formed in a source / drain region, and the contact pad is formed on a sidewall of a gate electrode, thereby providing an overlap margin in a subsequent contact process. And a method for manufacturing a semiconductor device for minimizing damage in an etching process.
일반적으로, P형 또는 N형 반도체기판에 N 또는 P형 불순물로 형성되는 PN접합은 불순물을 반도체기판에 이온 주입한 후, 열처리로 활성화시켜 확산영역을 형성한다.In general, a PN junction formed of an N or P-type impurity on a P-type or N-type semiconductor substrate is ion implanted into the semiconductor substrate and then activated by heat treatment to form a diffusion region.
따라서, 채널의 폭이 감소된 반도체소자에서는 확산영역으로 부터 측면확산에 의한 쇼트 채널 이펙트(short channel effect)를 방지하기 위하여 접합 깊이를 얕게 형성해야 한다.Therefore, in the semiconductor device having a reduced channel width, the junction depth must be shallow in order to prevent short channel effects due to side diffusion from the diffusion region.
종래 기술에 따른 모스 전계효과 트랜지스터의 제조방법은 다음과 같다.A method of manufacturing a MOS field effect transistor according to the prior art is as follows.
먼저, 반도체기판의 셀영역 및 주변회로영역에서 소자분리를 위한 소자분리절연막을 형성한 다음, 전체표면 상부에 게이트 절연막 및 다결정실리콘층을 형성한다.First, a device isolation insulating film for device isolation is formed in a cell region and a peripheral circuit region of a semiconductor substrate, and then a gate insulating film and a polysilicon layer are formed over the entire surface.
다음, 게이트 전극 마스크를 식각마스크로 사용하여 상기 다결정실리콘층 및 게이트 절연막을 식각하여 게이트 전극을 형성한다.Next, the polysilicon layer and the gate insulating layer are etched using a gate electrode mask as an etching mask to form a gate electrode.
그 다음, 상기 반도체기판의 셀영역에 형성되어 있는 게이트 전극의 양측 반도체기판에 저농도의 불순물을 이온 주입시켜 엘.디.디.(lightly doped drain, LDD)영역을 형성한다.Next, a low concentration of impurities are ion-implanted into both semiconductor substrates of the gate electrode formed in the cell region of the semiconductor substrate to form a lightly doped drain (LDD) region.
그리고, 전체표면 상부에 절연막을 형성한 다음, 전면식각하여 상기 게이트 전극의 측벽에 절연막 스페이서를 형성한다.Then, an insulating film is formed over the entire surface and then etched to form an insulating film spacer on the sidewall of the gate electrode.
그 후, 상기 반도체기판의 주변회로영역에 형성되는 상기 절연막 스페이서의 양쪽 반도체기판에 고농도의 불순물 이온주입하여 고농도의 소오스/드레인영역을 형성하여 모스 전계효과 트랜지스터를 형성한다.Thereafter, a high concentration of source / drain regions are formed by implanting a high concentration of impurity ions into both semiconductor substrates of the insulating film spacer formed in the peripheral circuit region of the semiconductor substrate to form a MOS field effect transistor.
다음, 전체표면 상부에 상기 반도체기판에서 콘택으로 예정되는 부분을 노출시키는 콘택홀이 구비된 층간절연막을 형성한다.Next, an interlayer insulating film having a contact hole for exposing a portion of the semiconductor substrate, which is to be a contact, is formed on the entire surface.
그 다음, 전체표면 상부에 도전층을 형성한 후 화학적 기계적 연마(chemical mechanical polishing, 이하 CMP라 함)공정 또는 플라즈마를 이용한 건식식각방법으로 상기 콘택홀을 매립하는 콘택플러그를 형성한다.Next, after forming a conductive layer on the entire surface, a contact plug for filling the contact hole is formed by a chemical mechanical polishing (CMP) process or a dry etching method using plasma.
그러나, 상기와 같이 종래기술에 따른 반도체소자의 제조방법은, 소오스/드레인영역에 콘택을 형성하는 경우 콘택과 게이트전극 간에 어느 정도의 오버랩 마진을 확보해야 하고, 콘택홀 식각공정 시 과도 식각공정에 의하여 소오스/드레인영역이 식각되어 접합누설전류가 증가하고 그로 인하여 소자의 동작 특성 및 수율을 저하시키는 문제점이 있다.However, in the method of manufacturing a semiconductor device according to the related art as described above, when forming a contact in a source / drain region, some overlap margin must be secured between the contact and the gate electrode. As a result, the source / drain regions are etched to increase the junction leakage current, thereby lowering the operation characteristics and yield of the device.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 반도체기판의 주변회로영역에 형성되는 게이트전극의 측벽 및 소오스/드레인영역에 다결정실리콘층을 이용하여 콘택패드를 형성함으로써 콘택 형성 시 오버랩 마진을 확보하고, 콘택홀을 형성하기 위한 식각공정 시 소오스/드레인영역의 손상을 방지할 수 있는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, the contact margin is formed on the sidewalls of the gate electrode formed in the peripheral circuit region of the semiconductor substrate and the source / drain regions using a polysilicon layer to form an overlap margin during contact formation. It is an object of the present invention to provide a method of manufacturing a semiconductor device that can secure the semiconductor device and prevent damage to the source / drain regions during an etching process for forming a contact hole.
도 1 내지 도 6 은 본 발명의 제1실시예에 따른 반도체소자의 제조방법을 도시한 단면도.1 to 6 are cross-sectional views showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention.
도 7 은 본 발명의 제2실시예에 따른 반도체소자의 제조방법을 도시한 단면도.7 is a cross-sectional view illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
10 : 반도체기판 12 : 소자분리절연막10 semiconductor substrate 12 device isolation insulating film
14 : 게이트절연막패턴 16 : 게이트전극14 gate insulating film pattern 16 gate electrode
18 : 실리사이드막패턴 20 : 마스크절연막패턴18: silicide film pattern 20: mask insulating film pattern
22 : 제1절연막 스페이서 24a : 제2절연막22: first insulating film spacer 24a: second insulating film
24b : 제2절연막 스페이서 26a : 제3절연막24b: second insulating film spacer 26a: third insulating film
26b : 제3절연막 스페이서 28 : LDD영역26b: third insulating film spacer 28: LDD region
30 : 소오스/드레인영역 32 : 콘택패드30: source / drain area 32: contact pad
33 : 잔류물 34 : 제1층간절연막33 Residue 34 First Interlayer Insulating Film
36a : 콘택플러그용 도전층 36b : 콘택플러그36a: conductive plug for contact plug 36b: contact plug
38 : 제2층간절연막 40 : 금속배선38: second interlayer insulating film 40: metal wiring
42 : 감광막패턴 44 : 산화막 스페이서42: photosensitive film pattern 44: oxide film spacer
이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 제조방법은,Method for manufacturing a semiconductor device according to the present invention for achieving the above object,
셀영역 및 주변회로영역으로 구분되는 반도체기판 상부에 게이트절연막패턴, 게이트전극, 마스크절연막패턴의 적층구조를 형성하는 공정과,Forming a stacked structure of a gate insulating film pattern, a gate electrode, and a mask insulating film pattern on a semiconductor substrate divided into a cell region and a peripheral circuit region;
상기 셀영역의 적층구조 양측 반도체기판에 LDD영역을 형성한 다음, 상기 셀영역 및 주변회로영역의 적층구조의 측벽에 절연막 스페이서를 형성하는 공정과,Forming an LDD region on both semiconductor substrates of the stacked structure of the cell region, and then forming insulating film spacers on sidewalls of the stacked structure of the cell region and the peripheral circuit region;
전체표면 상부에 제1절연막과 상기 제1절연막과 식각선택비 차이를 갖는 제2절연막을 순차적으로 형성하는 공정과,Sequentially forming a first insulating film and a second insulating film having an etch selectivity difference with the first insulating film over the entire surface thereof;
상기 주변회로영역에서 트랜지스터가 형성될 부분을 노출시키는 식각마스크를 이용하여 상기 제2절연막과 제1절연막을 식각해 상기 절연막 스페이서의 측벽에 제2절연막 스페이서와 제1절연막 스페이서를 형성하는 공정과,Etching the second insulating layer and the first insulating layer by using an etching mask exposing a portion where the transistor is to be formed in the peripheral circuit region to form a second insulating layer spacer and a first insulating layer spacer on sidewalls of the insulating layer spacer;
상기 제2절연막 스페이서와 제1절연막 스페이서의 양쪽 반도체기판에 고농도 불순물을 이온주입하여 소오스/드레인영역을 형성하는 공정과,Forming a source / drain region by ion implanting high concentration impurities into both semiconductor substrates of the second insulating film spacer and the first insulating film spacer;
전체표면 상부에 제1다결정실리콘층을 형성하고, 상기 주변회로영역의 트랜지스터 영역을 보호하는 식각마스크로 상기 제1다결정실리콘층을 패터닝하여 콘택패드를 형성하는 공정과,Forming a contact pad by forming a first polysilicon layer on the entire surface and patterning the first polycrystalline silicon layer with an etch mask that protects the transistor region of the peripheral circuit region;
상기 셀영역 상의 제2절연막을 제거하는 공정과,Removing a second insulating film on the cell region;
전체표면 상부에 층간절연막을 형성한 다음, 상기 층간절연막을 화학적 기계적 연마공정으로 평탄화하여 상기 콘택패드를 노출시키는 공정과,Forming an interlayer insulating film on the entire surface, and then planarizing the interlayer insulating film by a chemical mechanical polishing process to expose the contact pads;
상기 셀영역에서 비트라인 콘택영역 및 저장전극 콘택영역으로 예정되는 부분을 노출시키는 콘택마스크를 식각마스크로 상기 층간절연막과 제1절연막을 식각하여 콘택홀을 형성하는 공정과,Forming a contact hole by etching the interlayer insulating layer and the first insulating layer by using a contact mask that exposes a predetermined portion of the cell region to a bit line contact region and a storage electrode contact region, using an etch mask;
전체표면 상부에 제2다결정실리콘층을 형성하고, 상기 제2다결정실리콘층을 화학적 기계적 연마공정으로 제거하여 콘택플러그를 형성하되, 상기 주변회로영역의 콘택패드 상부도 동시에 제거하여 분리시키는 공정을 포함하는 것을 제1특징으로 한다.Forming a second polysilicon layer on the entire surface and removing the second polysilicon layer by a chemical mechanical polishing process to form a contact plug, and simultaneously removing and separating the upper contact pad of the peripheral circuit region. Let it be a 1st characteristic to do.
또한, 이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 제조방법은,In addition, the method of manufacturing a semiconductor device according to the present invention for achieving the above object,
셀영역 및 주변회로영역으로 구분되는 반도체기판 상부에 게이트절연막패턴, 게이트전극, 마스크절연막패턴의 적층구조를 형성하는 공정과,Forming a stacked structure of a gate insulating film pattern, a gate electrode, and a mask insulating film pattern on a semiconductor substrate divided into a cell region and a peripheral circuit region;
상기 셀영역의 적층구조 양측 반도체기판에 LDD영역을 형성한 다음, 상기 셀영역 및 주변회로영역의 적층구조의 측벽에 절연막 스페이서를 형성하는 공정과,Forming an LDD region on both semiconductor substrates of the stacked structure of the cell region, and then forming insulating film spacers on sidewalls of the stacked structure of the cell region and the peripheral circuit region;
전체표면 상부에 제1절연막과 상기 제1절연막과 식각선택비 차이를 갖는 제2절연막을 순차적으로 형성하는 공정과,Sequentially forming a first insulating film and a second insulating film having an etch selectivity difference with the first insulating film over the entire surface thereof;
상기 주변회로영역에서 트랜지스터가 형성될 부분을 노출시키는 식각마스크를 이용하여 상기 제2절연막과 제1절연막을 식각해 상기 절연막 스페이서의 측벽에제2절연막 스페이서와 제1절연막 스페이서를 형성하는 공정과,Etching the second insulating layer and the first insulating layer by using an etching mask exposing a portion where the transistor is to be formed in the peripheral circuit region to form a second insulating layer spacer and a first insulating layer spacer on sidewalls of the insulating layer spacer;
상기 제2절연막 스페이서와 제1절연막 스페이서의 양쪽 반도체기판에 고농도 불순물을 이온주입하여 소오스/드레인영역을 형성하는 공정과,Forming a source / drain region by ion implanting high concentration impurities into both semiconductor substrates of the second insulating film spacer and the first insulating film spacer;
전체표면 상부에 제1다결정실리콘층을 형성하고, 상기 주변회로영역의 트랜지스터 영역을 보호하는 식각마스크로 상기 제1다결정실리콘층을 패터닝하여 콘택패드를 형성하는 공정과,Forming a contact pad by forming a first polysilicon layer on the entire surface and patterning the first polycrystalline silicon layer with an etch mask that protects the transistor region of the peripheral circuit region;
상기 셀영역 상의 제2절연막을 제거하는 공정과,Removing a second insulating film on the cell region;
전체표면 상부에 층간절연막을 형성한 다음, 상기 층간절연막을 화학적 기계적 연마공정으로 평탄화하여 상기 콘택패드를 노출시키는 공정과,Forming an interlayer insulating film on the entire surface, and then planarizing the interlayer insulating film by a chemical mechanical polishing process to expose the contact pads;
전체표면 상부에 상기 콘택패드의 상부를 노출시키는 감광막패턴을 형성한 후 상기 감광막패턴의 측벽에 산화막 스페이서를 형성하는 공정과,Forming an oxide spacer on the sidewall of the photoresist pattern after forming a photoresist pattern on the entire surface to expose the upper portion of the contact pad;
상기 감광막패턴 및 산화막 스페이서를 식각마스크로 상기 콘택패드의 상부를 식각하여 분리하는 공정을 포함하는 것을 제2특징으로 한다.The second feature is that the photoresist pattern and the oxide spacer are etched to separate an upper portion of the contact pad with an etch mask.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 6 은 본 발명에 따른 반도체소자의 제조방법을 도시한 단면도이다.1 to 6 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
먼저, 셀영역(Ⅰ)과 주변회로영역(Ⅱ)으로 구성되는 반도체기판(10)에서 소자분리영역으로 예정되는 부분에 소자분리절연막(12)을 형성하고, 전체표면 상부에 게이트절연막, 게이트전극용 도전층, 마스크절연막을 순차적으로 형성하고, 게이트전극 마스크를 식각마스크로 상기 적층구조를 식각하여 마스크절연막패턴(20), 게이트전극(16) 및 게이트절연막패턴(14)의 적층구조패턴을 형성한다.First, an element isolation insulating film 12 is formed on a portion of the semiconductor substrate 10 including the cell region I and the peripheral circuit region II, which is intended to be an element isolation region, and the gate insulating layer and the gate electrode on the entire surface. A conductive layer and a mask insulating film are sequentially formed, and the stacked structure is etched using a gate electrode mask as an etch mask to form a stacked structure pattern of the mask insulating film pattern 20, the gate electrode 16, and the gate insulating film pattern 14. do.
다음, 상기 셀영역(Ⅰ)에 형성되는 적층구조패턴의 양측 반도체기판(10)에 저농도의 불순물을 이온주입하여 LDD영역(28)을 형성한다.Next, the LDD region 28 is formed by ion implantation of low concentrations of impurities into both semiconductor substrates 10 of the stacked structure pattern formed in the cell region I.
그 다음, 전체표면 상부에 제1절연막(도시 안됨)을 형성하고, 상기 제1절연막을 전면식각하여 상기 적층구조패턴의 측벽에 제1절연막 스페이서(22)를 형성한다.Next, a first insulating film (not shown) is formed over the entire surface, and the first insulating film is etched entirely to form first insulating film spacers 22 on sidewalls of the laminated structure pattern.
다음, 전체표면 상부에 제2절연막(24a)과 제3절연막(26a)을 순차적으로 형성하되, 상기 제2절연막(24a)은 산화막으로 형성하고, 상기 제3절연막(26a)은 질화막으로 형성한다. (도 1 참조)Next, the second insulating layer 24a and the third insulating layer 26a are sequentially formed on the entire surface, and the second insulating layer 24a is formed of an oxide film, and the third insulating layer 26a is formed of a nitride film. . (See Figure 1)
그 다음, 상기 주변회로영역(Ⅱ)에서 트랜지스터가 형성될 부분을 노출시키는 식각마스크를 이용하여 상기 제3절연막(26a)과 제2절연막(24a)을 식각하여 상기 제1절연막 스페이서(22)의 측벽에 제2절연막 스페이서(24b)와 제3절연막 스페이서(26b)의 적층구조를 형성하고, 소오스/드레인영역으로 예정되는 반도체기판(10)을 노출시킨다.Next, the third insulating layer 26a and the second insulating layer 24a are etched using an etching mask that exposes a portion where the transistor is to be formed in the peripheral circuit region II, thereby forming the first insulating layer spacer 22. A stack structure of the second insulating film spacers 24b and the third insulating film spacers 26b is formed on the sidewalls, and the semiconductor substrate 10, which is intended as a source / drain region, is exposed.
다음, 상기 주변회로영역(Ⅱ)에서 노출되는 반도체기판(10)에 고농도의 n+불순물을 이온주입하여 소오스/드레인영역(30)을 형성한다. (도 2 참조)Next, a source / drain region 30 is formed by ion implantation of a high concentration of n + impurity into the semiconductor substrate 10 exposed in the peripheral circuit region II. (See Figure 2)
그 다음, 전체표면 상부에 언도프트 다결정실리콘층(도시 안됨)을 형성하고, 상기 주변회로영역(Ⅱ) 상에 형성된 트랜지스터를 보호하는 식각마스크를 사용하여 상기 언도프트 다결정실리콘층을 식각하여 상기 소오스/드레인영역(30)에 접속되는 콘택패드(32)를 형성한다. 이때, 상기 셀영역(Ⅰ)은 소자가 밀집되어 있기 때문에상기 언도프트 다결정실리콘층을 식각한 후 소자 간에 상기 언도프트 다결정실리콘층의 잔류물(33)이 남게 된다. (도 3 참조)Next, an undoped polysilicon layer (not shown) is formed over the entire surface, and the undoped polysilicon layer is etched using an etch mask that protects the transistor formed on the peripheral circuit region (II). The contact pads 32 connected to the / drain regions 30 are formed. At this time, since the cell region I is densely packed, the residue 33 of the undoped polysilicon layer remains between the devices after the undoped polysilicon layer is etched. (See Figure 3)
다음, 상기 셀영역(Ⅰ) 상의 제3절연막(26a)을 제거한다. 이때, 상기 잔류물(33)이 제거된다.Next, the third insulating layer 26a on the cell region I is removed. At this time, the residue 33 is removed.
그 다음, 전체표면 상부에 제1층간절연막(34)을 형성하고, 상기 제1층간절연막(34)을 화학적 기계적 연마(chemical mechanical polishing, 이하 CMP라 함)공정으로 평탄화시켜 상기 주변회로영역(Ⅱ)의 콘택패드(32)를 노출시킨다. (도 4 참조)Next, a first interlayer insulating film 34 is formed over the entire surface, and the first interlayer insulating film 34 is flattened by a chemical mechanical polishing (hereinafter referred to as CMP) process to form the peripheral circuit region (II). The contact pad 32). (See Figure 4)
다음, 상기 셀영역(Ⅰ)에서 비트라인 콘택 및 저장전극 콘택으로 예정되는 부분을 노출시키는 콘택마스크를 식각마스크로 상기 제1층간절연막(34)과 제2절연막(24a)을 식각하여 상기 반도체기판(10)을 노출시킨다.Next, the first interlayer insulating layer 34 and the second insulating layer 24a are etched using a contact mask that exposes portions of the cell region I, which are intended as bit line contacts and storage electrode contacts, as an etch mask. Expose (10).
그 다음, 전체표면 상부에 다결정실리콘층(36a)을 형성하여 상기 노출된 반도체기판(10)에 접속되게 한다. (도 5 참조)Then, a polysilicon layer 36a is formed over the entire surface so as to be connected to the exposed semiconductor substrate 10. (See Figure 5)
다음, 상기 다결정실리콘층(36a)을 CMP공정으로 평탄화시키되, 상기 CMP공정은 상기 게이트전극(16) 상의 마스크절연막패턴(20)이 노출될 때까지 실시하여 콘택플러그(36b)를 형성한다. 이때, 주변회로영역(Ⅱ)에서는 마스크절연막패턴(20) 상에 형성된 상기 다결정실리콘층(36a) 및 콘택패드(32)가 동시에 제거되어 상기 콘택패드(32)의 상부가 분리된다.Next, the polysilicon layer 36a is planarized by a CMP process, and the CMP process is performed until the mask insulating film pattern 20 on the gate electrode 16 is exposed to form a contact plug 36b. In this case, in the peripheral circuit region II, the polysilicon layer 36a and the contact pad 32 formed on the mask insulating film pattern 20 are simultaneously removed to separate the upper portion of the contact pad 32.
그 다음, 전체표면 상부에 제2층간절연막(38)을 형성하고, 상기 셀영역(Ⅰ) 및 주변회로영역(Ⅱ)에서 콘택으로 예정되는 부분을 노출시키는 콘택마스크를 식각마스크로 이용하여 상기 제2층간절연막(38) 및 제1층간절연막(34)을 식각하여 콘택홀을 형성한다.Next, a second interlayer insulating film 38 is formed on the entire surface, and a contact mask that exposes a portion intended for a contact in the cell region I and the peripheral circuit region II is used as an etching mask. The two-layer insulating film 38 and the first interlayer insulating film 34 are etched to form contact holes.
다음, 전체표면 상부에 도전층(도시 안됨)을 형성하여 상기 콘택홀을 매립시킨 후 패터닝하여 콘택플러그(36b) 또는 콘택패드(32)에 접속되는 도전배선(40)을 형성한다. (도 6 참조)Next, a conductive layer (not shown) is formed on the entire surface to fill the contact hole, and then pattern the conductive hole 40 to be connected to the contact plug 36b or the contact pad 32. (See Figure 6)
한편, 도 7 은 본 발명의 제2실시예에 따른 반도체소자의 제조방법을 도시한 단면도로서, 제1실시예의 도 4 까지의 공정을 실시한 다음, 전체표면 상부에 주변회로영역의 콘택패드의 상부를 노출시키는 감광막패턴(42)을 형성하고, 상기 감광막패턴(42)의 측벽에 산화막 스페이서(44)를 형성한 것을 도시한다. 이때, 상기 감광막패턴(42)의 측벽에 산화막 스페이서(44)를 형성하는 것은 게이트전극의 폭이 작기 때문에 사진공정을 통해 형성되는 스페이스보다 더 작게 형성하여 콘택패드의 면적을 극대화할 수 있다. (도 7 참조)FIG. 7 is a cross-sectional view illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention. The process of FIG. The photoresist pattern 42 exposing the photoresist layer is formed, and an oxide film spacer 44 is formed on the sidewall of the photoresist pattern 42. In this case, forming the oxide spacer 44 on the sidewall of the photoresist pattern 42 may be smaller than the space formed by the photo process because the width of the gate electrode is small, thereby maximizing the area of the contact pad. (See Figure 7)
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 제조방법은, 반도체기판의 주변회로영역에 형성되는 게이트전극의 측벽에 형성되는 절연막 스페이서의 표면까지 콘택패드를 형성함으로써 후속 콘택공정 시 공정 마진을 확보할 수 있고, 게이트전극 간의 피치(pitch)를 줄여 반도체소자의 고집적화를 유리하게 하고, MOSFET 내의 포화영역(saturation region)에서의 전류량에 영향을 미치는 접합영역의 저항을 줄여 소자의 동작 특성 및 신뢰성을 향상시키는 이점이 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, a contact pad is formed to a surface of an insulating film spacer formed on a sidewall of a gate electrode formed in a peripheral circuit region of a semiconductor substrate, thereby securing a process margin during a subsequent contact process. It is possible to reduce the pitch between the gate electrodes, which is advantageous for high integration of semiconductor devices, and to reduce the resistance of the junction region which affects the amount of current in the saturation region in the MOSFET, thereby improving the operation characteristics and reliability of the device. There is an advantage to improve.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US7588979B2 (en) | 2003-02-06 | 2009-09-15 | Samsung Electronics Co., Ltd. | Method of manufacturing a semiconductor integrated circuit using a selective disposable spacer technique and semiconductor integrated circuit manufactured thereby |
| KR101031459B1 (en) * | 2003-12-24 | 2011-04-26 | 주식회사 하이닉스반도체 | Method for manufacturing a semiconductor device |
| CN108807268A (en) * | 2017-04-26 | 2018-11-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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2000
- 2000-07-31 KR KR1020000044273A patent/KR20020010793A/en not_active Application Discontinuation
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7588979B2 (en) | 2003-02-06 | 2009-09-15 | Samsung Electronics Co., Ltd. | Method of manufacturing a semiconductor integrated circuit using a selective disposable spacer technique and semiconductor integrated circuit manufactured thereby |
| US8222684B2 (en) | 2003-02-06 | 2012-07-17 | Samsung Electronics Co., Ltd. | Method of manufacturing a semiconductor integrated circuit using a selective disposal spacer technique and semiconductor integrated circuit manufactured thereby |
| KR101031459B1 (en) * | 2003-12-24 | 2011-04-26 | 주식회사 하이닉스반도체 | Method for manufacturing a semiconductor device |
| CN108807268A (en) * | 2017-04-26 | 2018-11-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN108807268B (en) * | 2017-04-26 | 2020-10-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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