JP3147161B2 - Field effect transistor and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to control of a threshold voltage in a field effect transistor. In particular, it relates to a field-effect transistor used for a high-speed, highly integrated LSI.

[0002]

2. Description of the Related Art FIG. 34 is a sectional view of a normal n-channel field effect transistor (MOSFET). On a p ^- type silicon substrate 101 via a thin gate oxide film 102,
A gate electrode 103 made of n ⁺ polysilicon is provided. On the surface of the silicon substrate 101 on both sides of the gate electrode 103, n ⁺ -type source / drain regions 105 are provided. In this transistor, when a voltage higher than the threshold voltage is applied to the gate electrode, a region (inversion layer) having a high electron concentration is formed in the silicon substrate (channel formation region 104) below the gate electrode, and this region is formed. It becomes a current path (channel).

In general, the threshold voltage of a field effect transistor depends on the concentration of an impurity (for example, boron) in the channel formation region 104 and the silicon substrate 101 in the vicinity thereof. This is because, when the impurity concentration is changed, the magnitude of the electric field caused by the impurity ions changes, and as a result, the threshold voltage changes. Therefore, the threshold voltage can be set to a desired voltage by adjusting the impurity concentration. Generally, an n-channel transistor is set to have a positive threshold voltage, and a p-channel transistor is set to have a negative threshold voltage.

A method of setting a threshold voltage by a method different from the method of introducing impurities is disclosed in Ushiki et al.
996 IEDM Technical Digest, 117 pages (T. Ushiki et. Al., 1996 IED)
M Tech Dig. , P. 117). FIG. 35 shows the structure. A gate insulating film 10 is formed on an SOI substrate in which a buried oxide film 110 and an SOI layer 111 made of a single crystal semiconductor are stacked on a silicon substrate 101.
A gate electrode 113 is provided through the gate electrode 2, and n ⁺ -type source / drain regions 1 are formed on the surface of the SOI layer on both sides of the gate electrode.
05 is provided. The insulating film 1 is formed on the side surface of the gate electrode 113.
A channel is formed in the SOI layer (channel formation region 104) below the gate electrode. This transistor uses n ⁺ instead of adjusting the impurity concentration.
The threshold voltage is set by using Ta having a larger work function than polysilicon as the material of the gate electrode 113.

This utilizes the property that the threshold voltage depends not only on the impurity concentration but also on the work function of the gate electrode. This will be described in detail. The potential of the gate electrode decreases as the work function increases. Therefore, when a material having a larger work function than n ⁺ polysilicon is used as a gate electrode in an n-channel transistor, a higher voltage needs to be applied to the gate electrode in order to form a channel. That is, the threshold voltage for forming a channel increases. In a normal n-channel transistor, the threshold voltage is 0 V or lower unless impurities are introduced into the channel formation region. However, Ta
When such a material is used for the gate electrode, the threshold voltage is increased, so that the threshold voltage can be set to a positive value in the n-channel transistor without introducing impurities.

Although the object of the present invention is not the setting of the threshold voltage, the object is different from that of the present invention. However, the field effect transistor shown in FIG. Are described in JP-A-60-43863. This transistor is a semiconductor substrate 1
01, a source / drain region 105 of a conductivity type different from that of the substrate, a first gate electrode (p ⁺ polysilicon gate 115 in the figure) provided on the semiconductor substrate via the gate insulating film 102, And a second gate electrode (in the figure, n ⁺ polysilicon 116) having a different work function from the first gate electrode provided in contact with the side wall of the gate electrode. The semiconductor substrate is p-type (the source / drain regions are n-type. N
When using a channel transistor, the work function of the second gate electrode is made smaller than the work function of the first gate electrode. Semiconductor substrate is n-type (source / drain region is p
Type. When a p-channel transistor is used, the work function of the second gate electrode is made larger than the work function of the first gate electrode. In addition, an example is shown in which one of the first gate electrode and the second gate electrode is Mo or Mo silicide. In the invention shown in FIG. 36, a shallow inversion layer is induced under the second gate electrode to alleviate the drain electric field, thereby improving the reliability or suppressing the short channel effect. In the materials described here,
The work function of p ⁺ silicon (or p ⁺ polysilicon) is the largest, followed by Mo or Mo silicide, and n ⁺ silicon (or n ⁺ polysilicon) is the smallest.

[0007] A similar structure is disclosed in Japanese Patent Laid-Open No. 3-227.
562 and JP-A-6-151828. An object of the invention described in JP-A-3-227562 is to alleviate an electric field induced in a deeply depleted region of a drain region in a region where a gate overlaps a source / drain region and reduce a leakage current. The object of the invention described in JP-A-6-151828 is to suppress the short channel effect.

In an n-channel transistor having n-type source / drain regions, the work function of the second gate electrode is set to be larger than that of the first gate electrode, contrary to the conventional example of FIG. JP-A-59-20 discloses a method of selecting respective materials from silicon, polysilicon, metal and the like.
No. 0465, JP-A-6-232389, JP-A-8-340104 and the like. This is shown in FIG. The purpose of these inventions is disclosed in JP-A-59-20.
No. 0465 discloses a relaxation of an electric field.
No. 9 and Japanese Patent Application Laid-Open No. 8-340104 relate to suppression of the short channel effect.

In addition, instead of the channel forming region, LDD
In a region (a region adjacent to the source / drain region, having the same conductivity type as the source / drain region and having a lower impurity concentration than the source / drain region), a method of providing a sidewall with a conductive material different from the gate electrode is used. , JP 6
JP-A-3-144574, JP-A-64-89461, JP-A-1-232765, JP-A-5-226
No. 361. These are intended to prevent deterioration over time due to trapping of electrons (hot carriers) in the LDD portion.

[0010]

The first problem is that the impurity introduced into the channel forming region for controlling the threshold voltage is a drain current (a current flowing into the drain region).
(First problem). The reason that the current is reduced by the introduction of impurities is mainly due to the electric field in the direction perpendicular to the channel surface formed by the impurity ions when the impurity concentration is low, and due to the impurity ions when the impurity concentration is high. The main cause is carrier scattering (impurity scattering). This problem becomes more serious when the field-effect transistor is miniaturized and a thin gate oxide film is used (or when the gate capacitance per unit area is increased). It has been studied to use a gate oxide film with a gate length of less than 0.25 μm and a thickness of 5 nm or less, but the absolute value of the threshold voltage becomes smaller as the gate oxide film becomes thinner. In order to secure the threshold voltage, it is necessary to increase the impurity concentration. Then, the first task becomes more serious. Also, in particular,
S for forming an element on a thin semiconductor layer (SOI) on an insulating film
In an OI field-effect transistor, it is necessary to dispose only impurities necessary for setting a threshold voltage in a thin semiconductor layer. As a result, the impurity concentration in a region where carriers flow is increased, and the current is reduced. Become serious.

Second Problem In the case where the threshold voltage is set by introducing impurities, the distribution of impurities differs for each transistor, and as a result, characteristics such as threshold voltage differ for each transistor (statistical problem). (Variation) occurs. It is known that this problem becomes significant with miniaturization of elements.

Third Problem As described above, the method of controlling the threshold voltage by introducing impurities has a problem.
It becomes obvious by applying the SOI structure.

In the structure shown in FIG. 35, the first and second problems can be solved because the threshold value can be set without using impurities. However, in this method, the threshold voltage is determined by a work function inherent to the material forming the gate electrode. In order to adjust the threshold voltage, it is necessary to reselect the material of the gate electrode. Since the change of the material involves the change of the manufacturing apparatus, the manufacturing process, and the raw material, it is difficult to easily change the threshold voltage. In addition, a gate electrode material that can provide a necessary threshold value does not always exist. Originally, it is desirable to determine the threshold voltage so that the operation of a circuit formed by transistors is optimized. However, this method has a third problem that it is difficult to optimize the threshold voltage. .

Fourth Problem The technique disclosed in Japanese Patent Application Laid-Open No. Sho 60-43863 (FIG. 36) and similar techniques are not aimed at suppressing the introduction of impurities or controlling the threshold voltage. Of course, the first and second issues will not be solved. These techniques aim at relaxing the electric field and suppressing the short channel effect.
However, focusing on the threshold voltage, these technologies have an essential defect that a normal threshold voltage cannot be obtained when a transistor is formed (fourth problem). Therefore, even if the field-effect transistors described in these publications are manufactured, a normal threshold voltage cannot be obtained, and the circuit cannot operate normally.

The fourth problem will be described in detail. In the prior art, taking an n-channel transistor as an example,
The threshold voltage of the second gate electrode is lower than that of the first gate electrode. For the second gate electrode, n ⁺ polysilicon or a material having a higher work function is used. A material having a higher work function than the second gate electrode is used for the first gate electrode. Since the gate electrode of a normal transistor is n ⁺ polysilicon, this results in the work function of the first gate electrode being larger than that of a normal transistor. In the transistor of FIG. 36, the threshold voltage is determined by a potential barrier formed below the first gate electrode. However, since the work function of the first gate electrode is large, the threshold voltage is lower than that of a normal transistor. Too high. Since the threshold voltage depends on the work function of the first gate electrode, the same problem as the third problem that the threshold voltage cannot be set freely occurs.
In general, when a transistor is miniaturized, an impurity (boron or the like) is introduced at a slightly higher concentration into or below a channel formation region in order to prevent punch-through (abnormal operation in which leakage current flows). Since this impurity has an effect of increasing the threshold voltage, if a material having a large work function is used for the first gate electrode, the threshold voltage becomes too high. Therefore, even when the work function of the first gate electrode is larger than that of a normal transistor, a structural device is required so that the threshold voltage can be set to a desired value. In the invention of FIG. 37 as well, the first and second problems occur similarly. If a material having a larger work function than n ⁺ polysilicon (in the case of n-channel) is used in the center,
The third and fourth problems occur similarly to the technique of FIG. For controlling the threshold value, the same method as in either the structure of FIG. 34 (introduction of impurities) or the structure of FIG. 35 (use of a gate work function) is used. The introduction of impurities causes the first and second problems. Also, if the center part of the gate is made of a material different from the usual,
The third problem occurs, in which the threshold voltage becomes too high, and it is not possible to adjust to a required value.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, and to provide a field effect transistor capable of freely setting a threshold voltage without doping impurities and a method of manufacturing the same. is there.

[0017]

According to the present invention, FIG.
As shown in the figure, the gate electrode of the field effect transistor is
It has a three-layer structure including a first gate electrode 7 at the center and second gate electrodes 8 on both sides thereof. The first gate electrode and the second gate electrode use materials having different work functions. If the first gate electrode length (T _m , the length in the horizontal direction in FIG. 1) is smaller than a certain length, the electric field generated by the first gate electrode and the electric field generated by the second gate electrode interfere with each other. The work function of the electrode has an intermediate value (effective work function) between the work function of the material forming the first gate electrode and the work function of the material forming the second gate electrode. act. Then
In this structure, by changing the width of the first gate electrode 7, the effective work function can be changed and the threshold voltage can be freely adjusted.

Therefore, according to the present invention, since the channel doping for setting the threshold value is not required, the first and second problems can be solved, and the threshold value can be freely adjusted. Therefore, the third problem is solved.
Further, since the effective work function of the gate electrode is effectively smaller than the work function of the material forming the first gate electrode, the fourth problem can be reduced. Also, the present invention
It can be composed of a combination of ordinary materials such as polysilicon and metal, and does not necessarily require a special material (for example, a material having a lower work function than n ⁺ polysilicon).

The electric field generated by the first gate electrode and the electric field generated by the second gate electrode interfere with each other, and the effect of the present invention becomes remarkable when the threshold voltage is applied to the gate electrode. An electric field that causes the potential of the semiconductor layer to be higher than the gate electrode when the source / drain region is n-type, and an electric field that causes the potential of the semiconductor layer to be lower than the gate electrode when the source / drain region is p-type Such that the second gate electrode forms in the center of the gate electrode,
In the case where the first gate electrode has a distance between both interfaces in contact with the second gate electrode, that is, the length of the first gate electrode, the distance between both interfaces in contact with the second gate electrode in the first gate electrode, that is, The length of the first gate electrode is 4
In the case of an SOI MOSFET in which an impurity is not introduced into the channel region, these two conditions match as described later.

In order to make the effect of the present invention more conspicuous, the distance between the two interfaces in contact with the second gate electrode in the first gate electrode, that is, the length of the first gate electrode is set to T.
_m , when the threshold voltage of the transistor is V _th ,
absolute value of the coefficient dV _th / dT _m obtained by differentiating _th with T _m (| dV
_th / dT _m |) in the range is greater than 4 × 10 ^-3 V / nm, setting the T _m.

Hereinafter, the means will be specifically described.

In the present invention, the insulating film 4 is formed on the semiconductor 3.
And a semiconductor layer below the gate electrode forms a channel forming region 9, and a source / drain region 6 of the first conductivity type is formed with the channel forming region interposed therebetween. In the field-effect transistor, the gate electrode is a first gate electrode 7 located at the center thereof.
And second gate electrodes 8 located on both sides thereof,
In the second gate electrode, at least a part thereof is located on the channel formation region, and when the first conductivity type is n-type, the work function of the second gate electrode is higher than the work function of the first gate electrode. Is small, and when the first conductivity type is a p-type,
When the work function of the second gate electrode is larger than the work function of the first gate electrode, and the threshold voltage is applied to the gate electrode, and the source / drain region is n-type, the potential of the semiconductor layer becomes higher. An electric field that is higher than the gate electrode
When the source / drain regions are p-type, an electric field such that the potential of the semiconductor layer is lower than that of the gate electrode is applied to the first gate electrode such that the second gate electrode forms at the center of the gate electrode. The distance between the two interfaces contacting the gate electrode, that is, the length of the first gate electrode. Specifically, this condition clearly appears when _Tm is 40 nm or less (see FIGS. 44 and 45), and this condition adjusts the threshold voltage by changing the width of the first gate electrode. This is consistent with the condition that the effect of performing the operation becomes remarkable (see FIGS. 39 and 41).

In the present invention, a gate electrode (7, 8) is provided on the semiconductor 3 with an insulating film 4 interposed therebetween, and a semiconductor layer below the gate electrode forms a channel formation region 9, and the channel formation region is formed. In the field-effect transistor in which the source / drain region 6 of the first conductivity type is formed sandwiching,
The gate electrode includes a first gate electrode 7 located at a central portion thereof and second gate electrodes 8 located on both sides thereof. At least a part of the second gate electrode is located on a channel formation region. When the first conductivity type is n-type, the work function of the second gate electrode is smaller than the work function of the first gate electrode, and when the first conductivity type is p-type, The work function of the gate electrode is larger than the work function of the first gate electrode, and the distance between both interfaces of the first gate electrode that contacts the second gate electrode, that is, the length of the first gate electrode is 40 nm or less. It is characterized by the following. When this condition is satisfied, the effect of adjusting the threshold voltage becomes significant by changing the width of the first gate electrode (see FIGS. 39 and 41).

In the present invention, a gate electrode (7, 8) is provided on the semiconductor layer 3 via an insulating film 4, and a semiconductor layer below the gate electrode forms a channel forming region 9,
In the field-effect transistor in which the source / drain regions 6 of the first conductivity type are formed with the channel forming region interposed therebetween, the gate electrode is composed of the first gate electrode 7 located at the center and the first gate electrode 7 located on both sides thereof. A second gate electrode, at least a part of which is located on a channel forming region; and when the first conductivity type is n-type, the work function of the second gate electrode is the second gate electrode. When the work function of the first gate electrode is smaller than the work function of the one gate electrode and the first conductivity type is p-type, the work function of the second gate electrode is larger than the work function of the first gate electrode. Assuming that the distance between both interfaces in contact with the second gate electrode, that is, the length of the first gate electrode is T _m and the threshold voltage of the transistor is V _th , the coefficient dV _th / d obtained by differentiating V _th by T _m. d
The absolute value of T _m (| dV _th / dT _m |) is 4 × 10 ⁻³ V / nm
It is characterized in that _Tm is set in a larger range. When this condition is satisfied, the effect of adjusting the threshold voltage becomes more remarkable by changing the width of the first gate electrode (see FIGS. 39 and 41).

In the present invention, an extension of the first gate electrode 54 is provided above the second gate electrode 53 as shown in FIG. This increases the contact area between the first gate electrode and the second gate electrode, improves the conduction between the two electrodes, and stabilizes the potential of both electrodes.

In the present invention, as shown in FIGS. 26 and 28, an insulating film is interposed between the first gate electrodes 54 and 64 and the second gate electrode 53. This has the effect of suppressing the diffusion of impurities between the two electrodes or the chemical reaction between the materials forming the two electrodes.

In the present invention, as shown in FIG. 29, on the first gate electrode 64 and the second gate electrode 53,
A conductor 66 connected to both of them is provided. This has the effect of improving conduction between both gate electrodes and stabilizing the potential of both gate electrodes.

In the present invention, as shown in FIGS. 19 to 26, a dummy pattern is formed, and a source / drain region is formed in a semiconductor using the dummy pattern as a mask.
The whole surface is covered with an insulating film, an opening is provided in the insulating film on the dummy pattern, the dummy pattern is removed by etching from the opening, the opening is extended downward, and the first conductive film is formed in the extended opening. By depositing a conductive material and etching it back, a sidewall is provided in the opening, followed by depositing a second conductive material and patterning the same.
A sidewall is the second gate electrode, and a second conductive material is the first gate electrode.

Further, in the manufacturing method of the present invention, FIG.
2. As shown in FIGS. 23, 25, and 26, the first conductive material is deposited in the extended opening and etched back to form a sidewall in the opening. It is characterized in that an insulating film is formed on the surface, and subsequently, a second conductive material is embedded.

[0030]

In the manufacturing method of the present invention, when an opening is provided for removing the dummy pattern by etching, the insulating film on the dummy pattern is removed by CMP to form an insulating film on the dummy pattern.
An opening in the membrane can be provided .

[0032]

[0033]

[0034]

Further, the present invention is the above-mentioned method for manufacturing a field effect transistor, wherein a dummy pattern is formed,
Using the dummy pattern as a mask, source / drain regions are formed in the semiconductor on both sides of the dummy pattern, the entire surface is covered with an insulating film, an opening is provided in the insulating film on the dummy pattern, and the dummy pattern is etched from the opening. By removing and extending the opening downward, depositing the first conductive material in the extended opening and etching it back, a sidewall is provided in the opening, and at least a region including the opening is provided. After depositing the second conductive material, the second conductive material deposited in the region excluding the opening is removed by CMP,
The present invention relates to a method for manufacturing a field-effect transistor, wherein a side wall in an opening is the second gate electrode, and a second conductive material embedded in the opening is the first gate electrode. Further, the present invention provides the above-mentioned production method,
The top of the first gate electrode, and the second gate electrode
At the top, a conductor connected to both of these gate electrodes is formed.
Of field effect transistors characterized by lengthening
Construction method.

By using these manufacturing methods, the above-described transistor structure can be easily formed.

The manufacturing method using the dummy pattern according to the present invention is a transistor having first and second gate electrodes, which differs from the structure of FIG. 1 in the size of the first gate electrode and the setting of the work function ( For example, the present invention may be applied to one having a different purpose such as the conventional example in FIG. The advantage of these manufacturing methods is firstly that the formation of the pattern is easy. Generally, the larger the gate electrode is, the easier it is to process.
However, in the step of first forming the first gate electrode and providing the second gate electrode on the side wall thereof, the first gate electrode is reduced to a dimension smaller than the gate length (the total length of the first and second gate electrodes). To form the gate electrode by lithography. However, according to the manufacturing method of the present invention, a dummy pattern equal to the entire length of the gate may be formed by lithography, so that the burden on the lithography process is reduced. The second is to reduce the effect of heat. Since the first and second gate electrodes are formed after the source / drain regions are formed using the dummy pattern as a mask, a chemical reaction occurs at the interface between the first and second gate electrodes due to the heat treatment when forming the source / drain regions. No migration of ions between interfaces occurs.

Further, if a manufacturing method of exposing the dummy pattern by removing the insulating film on the dummy pattern by CMP is used, it is necessary to perform a photolithography step when removing the insulating film on the dummy pattern and exposing the dummy pattern. In addition, the process is simplified, the load on the process is reduced, and defects due to pattern displacement due to photolithography can be reduced. After the conductive material is embedded in the opening, the conductive material is processed by CMP to obtain a gate electrode, whereby a flat structure can be obtained.
It should be noted that the advantages of the CMP process described above can also be obtained when applied to a case where the gate is made of a single material.

If an opening wider than the dummy pattern is provided on the dummy pattern, the width can be increased above the gate electrode to be formed, so that the gate resistance can be reduced.

[0040]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment First, the configuration of an embodiment of the present invention will be described with reference to FIG.

A first gate electrode 7 is provided on a semiconductor layer (SOI layer) 3 on an insulator 2 with a gate insulating film 4 interposed therebetween. On the gate insulating film on both sides of the first gate electrode, a second gate electrode 8 is provided in contact with the side surface of the first gate electrode, and on the surface of the semiconductor layer outside the second gate electrode, A source / drain region 6 of the first conductivity type is provided. When the first conductivity type is n-type, the work function of the second gate electrode is smaller than the work function of the first gate electrode. When the first conductivity type is p-type, the work function of the second gate electrode is The materials of the first and second gate electrodes are selected so that the function is larger than the work function of the first gate electrode. The first and second gate electrodes conduct with each other, and the same voltage is applied.
The first gate electrode length (T _m , the length of the first gate electrode in the horizontal direction in FIG. 1) is set to 40 nm or less.

FIG. 38 and FIG. 40 show the results obtained by using a device simulator to determine the dependence of the threshold voltage on the first gate electrode length (T _m ) in this structure. The simulation was performed on a transistor (n-channel transistor) having n ⁺ -type source / drain regions.
The gate length (L: the total length of the gate including the first gate electrode 7 and the two second gate electrodes 8 and the width in the horizontal direction in FIG. 1) is 0.1 μm and 0.2 μm, respectively. The gate oxide thickness is 1.5 nm, 3 nm, 5 nm, S
The OI film thickness was 10 nm, and the drain voltage was 0.1 V.
The second gate electrode was n ⁺ polysilicon, and the work function of the first gate electrode was the center of the forbidden band of silicon. The SOI layer 3 in the channel formation region 9 is not doped. Note that the threshold voltage was a gate voltage at which the drain current of a transistor having the same gate width as the gate length was 10 ^-7 A.

[0043] Changing the first gate electrode length T _m, it can be seen that the threshold voltage V _th is changed. This effect is particularly remarkable when T _m is 40 nm or less. The reason will be described. When _Tm is 50 nm or more, the threshold voltage increases as the gate oxide film becomes thicker. This is the same behavior as a normal transistor. In this behavior, an electric field is formed in the gate oxide film in a direction that makes the potential of the gate electrode higher than the potential of the channel through which electrons flow. The potential difference between the two interfaces increases,
This reflects an increase in the potential of the gate electrode. However, when _Tm is 40 nm or less, the threshold voltage decreases as the thickness of the gate oxide film increases, and the behavior differs from that of a normal transistor. This reflects that the electric field of the first gate electrode and the electric field of the second gate electrode interfere with each other, and a potential distribution different from that of a normal transistor is formed between the gate electrode and the channel. . In this area,
The threshold voltage of the transistor is determined not by the electric field from either the first or the second gate electrode, but by the electric field formed by mixing the two electric fields. This is as if the work function of the gate electrode is
It behaves as if it had changed to an effective work function having an intermediate value between the material forming the first gate electrode and the material forming the second gate electrode. As a result, FIG.
As shown in FIG. 8 and FIG. 40, the threshold voltage can be largely changed by changing the width of the first gate electrode and changing the interference state of the electric field. Then, as shown in these figures, the condition that the electric field of the first gate electrode and the electric field of the second gate electrode interfere with each other ( _Tm is 40
(nm or less), the threshold voltage can be largely changed by changing the length of the first gate electrode. Further, since the same simulation result is obtained when the gate length is changed, it can be said that this relationship holds even when the gate length is different. Therefore, as in the present invention, if the first gate electrode length is changed in a range where the electric field of the first gate electrode and the electric field of the second gate electrode interfere with each other (40 nm or less), the threshold voltage is changed. Can be set freely. The above simulation results show that a positive threshold voltage can be obtained in an n-channel transistor without introducing an impurity into a channel formation region.

The same holds true for the p-channel transistor if the polarities are all reversed.

By the above operation, the field effect transistor of the present invention can freely set the threshold voltage without the need of introducing impurities, thereby solving the first and second problems. In addition, since the threshold voltage can be freely adjusted by changing the width of the first gate electrode, there is no need to change the material forming the first gate electrode in order to change the threshold value. The problem is solved.

The interference between the electric field of the first gate electrode and the electric field of the second gate electrode will be specifically described.

FIG. 42 is a sectional view of a transistor of the present invention. In the case of an n-channel transistor, since the work function of the second gate electrode 165 is smaller than the work function of the first gate electrode 164, the potential of the second gate electrode is higher than that of the first gate electrode. Therefore, the potential below the first gate electrode rises due to the electric field from the second gate electrode, as shown by the arrow in FIG. This is the above-mentioned electric field interference, which becomes more conspicuous as the first gate electrode length is smaller. In addition, immediately below the first gate electrode,
Since the influence of the first gate electrode is large and the potential is low, this effect is obtained in a portion of the lower portion of the first gate electrode, which is a little away from the first gate electrode, specifically, for example, in a channel formation region. Become noticeable.

FIG. 43 shows the rise in potential. this
At the center of the first gate electrode.
FIG. The element structure is shown in FIG.
The curve (b) in the center of FIG.
_m= 30 nm. The drain voltage is 0.1V
is there. The curve (a) in FIG. 43 indicates that the entire gate electrode is n. ⁺
In the case of polysilicon, the curve (c) shows the entire gate electrode.
If the body is metal (the work function is
If specified). For the structure of curve (b), the curve
In the structure of (a), the entire gate electrode is formed as a second gate electrode.
For the same material, the structure of curve (c) is
This corresponds to the case where the whole is made of the same material as the first gate electrode.
However, looking at FIG. 43, it can be seen that in the SOI layer in the curve (b)
Is halfway between the curves (a) and (b),
The electric field in the structure of (b) is n ⁺For polysilicon
As if the electric field of the metal and the electric field of the metal were mixed
It can be seen that the behaviors are as follows. Tiger on the gate electrode
When a voltage that becomes the threshold voltage of the transistor is applied,
The potential distribution in the vertical direction is shown in FIGS. Element structure
Is the same as that in FIG. 39, and the drain voltage is
0.1V. Length T of first gate electrode_mIs 30n
In the case of m and 40 nm (FIG. 44), the potential of the SOI layer is
Higher than the gate electrode, causing the mixing of the electric field.
coming. In this case, the electric field from the second gate electrode
The interference is significant and T_mIs changed by 10 nm.
The threshold voltage changes by 40 mV or more (change in potential at the right end of the figure)
Equivalent to quantity. ). In contrast, the length of the first gate electrode
T_mAre 50 nm, 60 nm and 70 nm (FIG. 4)
In 5), the potential of the gate electrode is higher than that of the SOI layer.
The same bias condition was given to the MOSFET of
It is no different from the case. That is, as described above,
No significant electric field interference and mixing_mIs changed by 10 nm.
The change in threshold voltage is as small as 10 to 15 mV
No.

Therefore, in the present invention, the condition that the mixing of the electric field becomes remarkable ( _Tm is 40 nm or less. The potential of the SOI layer is higher than that of the gate electrode. The potential in the gate oxide film becomes lower on the gate electrode side). Is positively used to control the first gate electrode length _Tm, thereby making it possible to greatly control the threshold voltage.

When a threshold voltage is applied to the gate electrode, the potential distribution in which the potential of the SOI layer is higher than that of the gate electrode shows that even in a normal SOIMOSFET, when the drain voltage is extremely high, particularly in the source / drain region. Although the present invention is observed in a near region or the like, the present invention is generated by the interference between the electric fields of the first and second gate electrodes, and is generated even when the drain voltage is low. In the present invention, this is the center of the gate (in FIGS. 43 and 44,
In a transistor having a gate length of 0.1 μm, it is also recognized at a position 0.05 μm from the source). Also, SOI
The potential distribution in which the potential of the layer is higher than that of the gate electrode is represented by SO
When a large amount of donor is introduced into the I layer (in this case, first,
Although the second problem occurs), the present invention is excellent in that the first and second problems do not occur without introducing a donor. A potential distribution in which the potential of the SOI layer is higher than that of the gate electrode also occurs when a positive voltage is applied to the supporting substrate. In this case, a power supply and a wiring for applying a voltage to the substrate are required. There are drawbacks. The present invention does not have these disadvantages.

FIGS. 39 and 41 show n-channel transistors.
Star threshold voltage V_thIs the first gate electrode width T_mIn fine
Divided value (dV_th/ DT_m). Figure 39 shows the gate length
FIG. 41 shows the case of 0.1 μm, and FIG. 41 shows the case of 0.2 μm. T_mBut
When it is larger than 40 nm, the value becomes T_mIs small area
(T_m= 10 nm) to 20% or less. dV_th
/ DT_mIs T_m= 1 × 2 × 10 at 10 nm^-2V /
nm, but T_m= 2 × 10 at 50 nm^-3V / nm
Becomes T_m= 60nm and almost T_m= 10nm
It is about 1/10 of the value. Therefore, T_m50 nm or more
Even if thicker, V_thT_mDependence is small, T_mchange
This diminishes the effect of controlling the threshold.
In contrast, T_mDV at = 40 nm_th/ DT_mThe value of
1.5 × 10 ^-34 × 10 from V / nm^-3V / nm range
And T_mIs smaller than 40 nm.
You. Therefore, the electric fields of the first and second gate electrodes cause interference.
Scrub area (T_mIs 40 nm or less)._thT_mDependence
Is large, by adjusting the width of the first gate electrode.
V_thCan be adjusted effectively.

Further, as shown in FIG. 39, even if the first and second gate electrodes cause interference, dV _th / d
Since the value of the T _m decreases the gate oxide film thickness is thin, when it is desired to increase the control the threshold voltage may be set T _m in a range equal to the case where the gate oxide film is thick is obtained . For example, when T _m = 40 nm and the gate oxide film thickness is 5 nm, the value of dV _th / dT _m is 3 × 10 ⁻³ V / nm to 4 × 10 ⁻³ V / nm.
Since it is in the range of 10 ⁻³ V / nm, even when the structural conditions of the device such as the gate oxide film are changed, dV _th / dT is obtained.
T _m is set in a range where the value of _m exceeds 4 × 10 ⁻³ V / nm. In this case, from FIG. 39, the T _m in the gate oxide film thickness 3 nm 37 nm or less, the gate oxide film thickness 1.5 nm T _m
Is set to 32 nm or less. By doing so, V _{t h} are available sensitive region with respect to T _m.

In the p-channel transistor, V _th
And dV _th / dT _m are negative, so that T _m may be set so that the absolute value has the same relationship as above. Accordingly, by replacing the above-described V _th and dV _th / dT _m with their respective absolute values, a relation that holds for both the n-channel transistor and the p-channel transistor can be obtained. Furthermore, the T _m was determined for n-channel transistors, it may be directly applied to the p-channel transistor.

In general, the introduction of impurities into an FET has two purposes: setting a threshold value and suppressing punch-through. Conversely, the impurity concentration affects both the threshold value and punch-through. That is, the normal M
In the OSFET, an impurity is introduced from the viewpoint of suppressing punch-through in addition to the setting of the threshold value. Therefore,
Even if a structure that does not require the introduction of impurities to set the threshold voltage can be formed, the impurities introduced for suppressing punch-through affect the threshold, and the first and second impurities are not affected. There is a problem that causes two problems. However, in the above-described embodiment of the present invention, since the SOI structure that does not easily cause punch-through is used, it is not necessary to introduce impurities from the viewpoint of suppressing punch-through, and the first and second problems are solved. You. Note that the value of _Tm may be set so as to satisfy a necessary threshold voltage within the range described above. For example, the threshold voltage of an n-channel transistor is set to a positive value. FIG.
From FIG. 8, since this is the case of T _m or more, it is desirable to set the value of T _m to 3.5 nm or more. This is especially important in circuits requiring a positive threshold voltage, such as CMOS circuits. In addition, the off current (0 V is applied to the gate electrode)
, The threshold voltage needs to be about 0.12 V or more, which satisfies this requirement. _Is set as follows. In this case, from FIG. 38, it is preferable that T _m is 11 nm or more. In general, in a CMOS circuit operating at a power supply voltage of about 1.2 to 1.5 V, the threshold voltage is set to 0.2 to 0.
It is considered that the operation speed, the leak current, and the noise margin can be simultaneously and satisfactorily maintained by setting the voltage to 3 V (Taua et al., 1997, IEDM Technical Digest, page 215). it is desirable to set the T _m so as to satisfy this. In this case, from FIG. 38, Tm is desirably in the range of 18 _nm to 30 nm.

For example, in the conventional example of FIG. 36, the work function of the first gate electrode (p ⁺ polysilicon, Mo, Mo silicide) is n ⁺ polysilicon which is a material used as a gate electrode in a normal transistor. Greater than. In this case, a problem occurs that the threshold voltage of the transistor becomes too high. Although the threshold voltage depends on the impurity concentration of the channel formation region and the work function of the gate, the impurity doping of the channel formation region is also necessary for suppressing punch-through (generation of leakage current due to unnecessary conduction). Therefore, if doping for suppressing punch-through is performed, the threshold voltage becomes too high and cannot be applied to an actual device. This can be said to cause the same problem as the third problem because the threshold value depends on the work function of the first gate electrode. With respect to this, in the present invention, when the first gate electrode length is set to 40 nm or less, the threshold value is prevented from becoming excessively high by utilizing the fact that the electric fields by the first and second gate electrodes significantly interfere with each other. It can be set to obtain an optimal threshold. Therefore, when the present invention is applied to the conventional example shown in FIG. 36, the work function of the first gate electrode can be effectively lowered, so that the problem that the threshold voltage becomes too high is solved, and the application to a circuit is solved. Becomes possible.

In the structure of the present invention, the threshold voltage is determined by the interference between the electric field of the first gate electrode and the electric field of a region of the second gate electrode adjacent to the first gate electrode. Therefore, when the second gate electrode length (the horizontal length of the second gate electrode in the horizontal direction in FIG. 1) is large, the outer portion (source
The portion adjacent to the drain region) does not contribute to the threshold voltage. Therefore, if the length of the first gate electrode is constant, even if the length of the second gate electrode is increased, only the length of the outer portion that does not contribute to the threshold value changes. It no longer depends on the total length of the gate. That is, the short channel effect is suppressed. The suppression of the short channel effect (effect by relaxing the electric field) is also claimed in the conventional examples of FIGS. 36 and 37, but the present invention uses a different principle (the length of the second gate electrode is shorter). , The effect on the threshold value is small) to suppress the short channel effect, and the effect is superior to the conventional example.
This effect is obtained by a configuration in which the electric field interference of the first and second gate electrodes claimed in the present invention occurs.

In a normal field-effect transistor, when the source / drain region enters below the gate electrode due to diffusion of impurities, the distance (execution channel length) between the two source / drain regions decreases. As a result, the threshold voltage fluctuates. However, in the structure of the present invention,
Since the potential below the first gate electrode changes due to the interference of the electric field of the second gate electrode, the structure below the second gate electrode does not significantly affect the threshold voltage. Therefore, even if the source / drain region enters under the gate electrode due to diffusion of impurities, if the source / drain region partially penetrates under the second gate electrode, the variation in threshold voltage is small. Variations in element characteristics due to the lateral diffusion of impurities are suppressed.

Although the same effect can be obtained by connecting two or more combinations of the first gate electrode sandwiched between the second gate electrodes, the same effect can be obtained. The fewer components of the electrode, the better. Therefore, the above three-layer structure in which the first gate electrode is sandwiched between two second gate electrodes is most desirable from the viewpoint of miniaturization of the device. The three-layer structure also satisfies the requirement that the source / drain regions be symmetric with respect to the replacement.

In the description relating to the present invention, the conductivity type of the source / drain region is called the first conductivity type, unlike the description in Japanese Patent Application Laid-Open No. 60-43863. this is,
In an SOI transistor or the like, the conductivity type of a channel formation region may not always be the conductivity type opposite to that of a source / drain region. One conductivity type,
This is because the source / drain region may not be defined as the second conductivity type. Note that the conductivity type (channel type) of the field-effect transistor always matches the conductivity type of the source / drain regions, and thus the conductivity type described as the first conductivity type in the description of the present invention is the same as the channel type of the transistor. Matches.

Next, a description will be given of a structural example in which a part of the structure shown in FIG. 1 is changed.

If the source / drain region does not reach below the boundary between the first and second gate electrodes, a part thereof may enter under the second gate electrode (FIG. 3). This is because the electric field generated by the first and second gate electrodes interferes with each other to set the threshold voltage, so that at least a part of the second gate electrode only needs to be on the channel formation region. .

The thickness of the gate insulating film below the second gate electrode may be smaller than the thickness below the first gate electrode (FIG. 4). When the oxide film below the second gate electrode is thinned, the electric field from the source / drain region is terminated at the gate electrode, which is advantageous for suppressing the short channel effect. On the other hand, since the threshold value of the first gate oxide film becomes lower as it is thicker, this structure is effective when the threshold value is set higher and the short channel effect is desired to be suppressed.

This structure can be obtained when the oxide film is over-etched after the first gate electrode is etched in the manufacturing method shown in FIGS. When the central oxide film is thickened by oxidation or the like after the formation of the second gate electrode, it is formed when the oxide film is deposited again by CVD or the like.

Conversely, the thickness of the gate insulating film may be thicker below the second gate electrode than below the first gate electrode (FIG. 5). When the thickness of the insulating film below the second gate electrode is increased, the electric field between the second gate electrode and the source / drain region is weakened. However, in this case, the effect that the second gate electrode terminates the electric field from the source / drain region is weakened. Therefore, when the gate length is relatively long (for example, 0.25 μm) or the like, it is not necessary to suppress the short channel effect. (For example, elements used for dynamic memory)
This structure is effective. This structure is obtained when the first gate electrode is oxidized again after etching in the manufacturing method shown in FIGS.
26 to 26 are formed, for example, when the oxide film at the center is thinned by etching or the like after the formation of the second gate electrode.

The length of the second gate electrode (in the horizontal direction of the cross section in FIG. 6) may be the same as the length of the first gate electrode (FIG. 6) or may be thinner than the first gate electrode (FIG. 7). ). Also,
An LDD region 2 in which a part of the source / drain region is of the first conductivity type and has a lower impurity concentration than the source / drain region 2
It may be 1 (FIG. 8). In addition, a part of the source / drain region is of the first conductivity type, has an impurity concentration as high as the source / drain region, and is formed shallower than other portions of the source / drain region.
(FIG. 9). However, in any case, in the present invention, at least a part of the second gate electrode must be located at the top of the channel formation region, not the LDD region or the extension region, and the first gate electrode length T _m is the first, the electric field from the second gate electrode must be set significantly interfering range (40 nm or less).

Next, specific dimensions of the transistor configuration will be shown as an example of the embodiment.

FIG. 1 is a sectional view of a field effect transistor according to the present invention. In an SOI substrate in which a semiconductor layer 3 (SOI layer) made of single-crystal silicon having a thickness of 10 nm is provided on a supporting substrate 1 made of a silicon wafer via a buried oxide film 2 made of SiO ₂ having a thickness of 400 nm. Width (horizontal direction in the cross section of FIG. 1) 2
A first gate electrode 7 made of TiN and having a thickness of 0 nm and a thickness (height direction) of 100 nm is provided. First gate electrode 7
On both sides of the gate insulating film 4, a second gate electrode 8 having a width (horizontal direction in the cross section in FIG. 1) of 50 nm is provided on the gate insulating film 4 in contact with the side surface of the gate electrode 7. The semiconductor layer 3 on both sides of the second gate electrode has a high concentration of phosphorus (for example, 10 ¹⁹ c).
The n ⁺ -type source / drain regions 6 introduced at m ⁻³ ) are formed. A region between the source / drain regions 6 below the first and second gate electrodes forms a channel forming region 9 in which a channel is formed by electrons.

Here, the thickness of the semiconductor layer 3 is usually 5 nm.
To 100 nm. The thickness of 5 nm or more is to suppress the influence of the quantum mechanical size effect (fluctuation of the subband level), and the thickness of 100 nm or less is because a fully depleted device having good device characteristics is easily formed. is there. If the effect of suppressing the short channel effect is more strongly sought, and if the effect of the quantum mechanical size effect can appear, the thickness may be made smaller. In addition, when the gate length is long (for example, 1 micron or more) in a high breakdown voltage MOS or the like and a short channel effect is unlikely to occur, or when a fully depleted element is not formed in an LSI (when a partially depleted element is used). For example, the thickness of the semiconductor layer may be 100 nm or more. The impurity introduced into the source / drain regions may be arsenic. Further, the source / drain region may have an elevated structure that projects above the surface of the channel formation region. Further, the semiconductor layer may be a polycrystalline semiconductor. In this case, the leakage current increases, the current decreases due to grain boundary scattering, etc., as compared with the case of a single crystal layer. However, there is an advantage that the substrate can be easily manufactured.

The thickness of the buried oxide film 2 is not particularly limited for obtaining the effects of the present invention. Usually, the buried oxide film is about 1 μm to 2 μm in the SOI substrate manufactured by the bonding technology, and 80 nm to 400 μm in the SOI substrate manufactured by the SIMOX technology.
The thickness is on the order of nm, but the present invention can be applied to cases where the thickness is thinner or thicker. Further, the present invention can be applied to a structure having a thick insulating substrate such as sapphire instead of the buried oxide film and having no support substrate 1.

The thickness of the gate insulating film is usually 2 nm to 20 nm.
nm. If the thickness is smaller than this, a leakage current from the gate electrode is generated due to the tunnel current. However, if the leakage current may be large depending on the use of the device, an insulating film thinner than this may be used. Further, it is LS
In order to obtain a drain current that is generally required as an element for I, in a high breakdown voltage element or the like, the thickness may be larger if the electric field relaxation in the gate oxide film is more important than the drain current. The gate insulating film is made of SiO ₂
However, other insulators such as Si ₃ N ₄ , Ta
_It may be ₂ O ₅ or the like. Further, a plurality of materials may be stacked.

The total length of the gate electrode (the total of the first gate electrode and the two second gate electrodes, the horizontal length of the cross section in FIG. 1) is, for example, in the range of about 30 nm to 0.6 μm. This is a dimension normally used when assuming a transistor for LSI, and a dimension that is said to be used in the future. Good.

In the n-channel transistor, the first gate electrode may be p ⁺ polysilicon, a metal such as Mo, W, Ta, or the like, a metal silicide, a metal compound such as TiN, or the like. When the first gate electrode is made of p ⁺ polysilicon, the second gate electrode may be made of a metal such as Mo, W, or Ta, or a metal silicide. Among these materials, p ⁺ polysilicon has the largest work function, followed by Mo, W, Ta, or a metal silicide such as tungsten silicide or TiN, and n ⁺ polysilicon has the smallest work function. The work function of the second gate electrode may be set to be smaller than that of the first gate electrode, including these materials or other materials. When setting the threshold value to 0.5 V or less,
The first gate electrode is made of metal or metal silicide,
A combination in which the second gate electrode is made of n ⁺ polysilicon is appropriate for obtaining a required threshold voltage. When forming a p-channel transistor, the source
The drain region is a p ⁺ type with boron introduced, and the work function of the second gate electrode is set to be larger than that of the first gate electrode. For example, if the first gate electrode is Ti
N, a second gate electrode is formed of p ⁺ polysilicon.

When channel doping is not performed, the material of the first gate electrode must have a work function larger than that of the source / drain regions so that the threshold voltage of the n-channel transistor has a positive value. Must. In order for a p-channel transistor to have a negative threshold voltage, the material of the first gate electrode must have a work function smaller than that of the source / drain region.

FIG. 3 shows a case where the source / drain region has entered the lower portion of the second gate electrode over a width of 10 nm in the structure of FIG. If a part of the second gate electrode is on the channel formation region, as described above, the effect of the present invention can be obtained even if a part of the second gate electrode is on the source / drain region as shown in FIG. Will not be replaced.

In the structure of FIG. 4, the thickness of the gate insulating film is
For example, the thickness is 5 nm below the first gate electrode and 3 nm below the second gate electrode. In the structure of FIG.
The thickness of the gate insulating film is, for example, 3 nm below the first gate electrode and 5 nm below the second gate electrode.

FIG. 6 shows a case where the width of the second gate electrode is the same as that of the first gate electrode in the structure of FIG.
0 nm). FIG. 7 shows a case where the width of the second gate electrode is smaller than that of the first gate electrode in the structure of FIG. For example, when the width of the first gate electrode is 20 nm,
The width of the second gate electrode is 15 nm.

Next, a manufacturing method will be described with reference to FIGS.

As shown in FIG. 10, a buried oxide film 3 of 400 nm thick SiO ₂ is formed on a silicon substrate 31.
2, the surface of the semiconductor layer 33 is thermally oxidized on the SOI substrate on which the semiconductor layer 33 (SOI layer) made of single-crystal silicon having a thickness of 12 nm
A gate insulating film made of O ₂ is formed. Subsequently, a TiN film having a thickness of 100 nm is deposited on the entire surface by a CVD method or a sputtering method, and a photoresist 36 is patterned thereon to have a width of 30 nm. Here, in order to obtain a fine pattern of 30 nm, the resist is exposed using an electron beam direct writing technique (EB direct writing, for example, described in Nikkei Micro Devices, November 1997, pages 141 to 144), As the resist, a material having a cyclic molecular structure such as calixarene and chloromethylated calixarene may be used. TiN by RIE (Reactive Ion Etching) using photoresist 36 as a mask
Pattern the film, made of TiN, thickness 50nm,
A first gate electrode 35 having a width of 30 nm is formed to obtain the structure shown in FIG.

In the SOI element, the step in the element isolation portion (LOCOS) is small, so that when patterning TiN, etching residue of TiN hardly occurs in the step at the element isolation end. Therefore, over-etching for the purpose of preventing etching residue can be reduced. Over-etching damages the gate oxide film on both sides of the first gate electrode. However, over-etching can be suppressed, so that damage to the gate oxide film can be suppressed. When an element is formed on a bulk substrate, the problem of over-etching can be similarly solved by using an element isolation having a small step such as a trench isolation.

Next, as shown in FIG.
0 nm n ⁺ polysilicon 37 (doped polysilicon)
Is deposited by CVD. Next, n ⁺ polysilicon is etched back over a thickness of 50 nm by anisotropic etching by RIE, and a second gate electrode made of n ⁺ polysilicon 37 having a width of 50 nm is formed on the side surface of the first gate electrode 35. To form Subsequently, high-concentration phosphorus is introduced into the semiconductor layer 33 using the first and second gate electrodes as masks, and n ⁺ -type source / source regions are formed outside the first and second gate electrodes.
A drain region 38 is formed (FIG. 12). The lower part of the gate electrode becomes the channel formation region 39. The source / drain regions are formed by, for example, ion implantation at a low acceleration voltage. Alternatively, using the first and second gate electrodes as a mask, the gate insulating film in the region outside the gate electrodes is removed by RIE, and then phosphorus glass (PSG) is deposited on the entire surface, and 850 is deposited.
By performing a heat treatment at 10 ° C. for 10 seconds, phosphorus is diffused from the PSG into the semiconductor layer 33 to form source / drain regions. In addition, before the PSG is deposited, a sidewall of the oxide film may be provided outside the second gate electrode to suppress the diffusion of phosphorus from entering the lower portion of the second gate electrode. The second gate electrode is formed by first depositing polysilicon containing no impurities (non-doped polysilicon) and diffusing phosphorus from PSG simultaneously with the formation of the source / drain regions,
This may be an n ⁺ type.

Further, the gate oxide film is set to a thicker thickness of 5 nm in advance, and overetching is performed in RIE for forming the first gate electrode, and the oxide films on both sides of the first gate electrode are slightly removed, or When the oxide film is etched for a short time using the first gate electrode as a mask, a structure in which the gate insulating film is thinner under the second gate electrode is obtained as shown in FIG.

Here, the removal of the oxide film at the time of over-etching is remarkable when the selectivity of TiN to the oxide film is low in the RIE step. Also,
After the first gate electrode processing, if thermal oxidation is performed for a short time,
The thickness of the oxide film becomes large outside the first gate electrode, and a shape as shown in FIG. 5 is obtained.

Second Embodiment For the various structures of the first embodiment, the semiconductor layer on the insulator and the buried oxide film may be replaced with a normal bulk substrate. An example is shown in the sectional view of FIG.

On a p ^- silicon substrate 10 containing 5 × 10 ¹⁷ cm ^{−3 of} boron, a width (horizontal direction in the cross section of FIG. 2) 2 is interposed via a gate insulating film 4 made of a thermal oxide film having a thickness of 3 nm.
A first gate electrode 7 made of TiN and having a thickness of 0 nm and a thickness (height direction) of 100 nm is provided. On both sides of the first gate electrode 7, a second gate electrode 8 having a width (horizontal direction in the cross section in FIG. 2) of 50 nm is provided on the gate insulating film 4 in contact with the side surface of the gate electrode 7. On the silicon substrate on both sides of the second gate electrode, a high concentration of arsenic (for example, 10
An n ⁺ -type source / drain region 6 having a depth of 0.15 μm and being introduced at ¹⁹ cm ⁻³ ) is formed. A region between the source / drain regions 6 below the first and second gate electrodes forms a channel forming region 9 in which a channel is formed by electrons.

The structure shown in FIG. 2 is different from the structure having a semiconductor layer on an insulator (SOI structure) in that a normal semiconductor substrate 10 is used.
And the source / drain regions are provided on the surface of the semiconductor substrate. In this case, since the amount of the impurity is sufficient to suppress punch-through, the doping amount can be suppressed, and the first and second problems can be reduced. For example, when an impurity for suppressing punch-through is introduced, the threshold becomes too high when the threshold is controlled by the work function of the gate as in the conventional example of FIG. Utilizing the fact that the ability of the first gate electrode to form a barrier is weakened, it is possible to prevent the threshold from becoming too high, and to obtain an optimal threshold.

Third Embodiment A third embodiment will be described with reference to FIG. In the above manufacturing process, after forming the second gate electrode,
An oxide film having a thickness of 20 nm is deposited on the side surface by a CVD method, and this is etched back to form an oxide film side wall 40. At the time of etch back, the gate insulating film located outside the oxide film side wall is simultaneously removed. Next, an epitaxial layer 41 made of n ⁺ -type silicon is grown to a thickness of 30 nm on the semiconductor layer 33 outside the oxide film side wall 40 by a selective epitaxial method. By mixing a gas containing phosphorus at the time of epitaxial growth, the epitaxial layer 41 can be made n ⁺ type. At this time, n ⁺
An n ⁺ -type polycrystalline layer 42 also grows on the polysilicon layer 37, but this does not affect the device characteristics. Subsequently, the source / drain regions 33 are formed by diffusing phosphorus from the epitaxial layer into the semiconductor layer 33 by a short-time heat treatment (for example, at 850 ° C. for 10 seconds).

Fourth Embodiment A configuration and a manufacturing method of another embodiment will be described with reference to FIGS. On an SOI substrate in which a semiconductor layer 33 (SOI layer) made of single-crystal silicon having a thickness of 10 nm is provided on a silicon substrate 31 via a buried oxide film 32 made of SiO ₂ having a thickness of 400 nm, the entire surface is formed by CVD. A SiO ₂ film having a thickness of 100 nm was deposited, and this was processed to a width of 120 nm by lithography by EB exposure, etching by RIE, and the like.
As shown in FIG. 4, a dummy oxide film 51 is formed.

Next, by selective epitaxial growth, as shown in FIG. 14, both sides of the dummy oxide film 51 are made of n ⁺ -type single-crystal silicon having a thickness of 50 n
The m epitaxial layers 41 are formed.

Next, the dummy oxide film is removed by HF (hydrofluoric acid). Subsequently, an oxide film having a thickness of 30 nm is deposited on the entire surface by CVD, and is etched back by RIE.
As shown in FIG. 7, a sidewall oxide film 52 is provided. Heat treatment is performed for a short time (for example, at 850 ° C. for 10 seconds) to diffuse phosphorus in the epitaxial layer 41 into the semiconductor layer 33 to form an n ⁺ -type source / drain region 38 (FIG. 15).

Next, the surface of the semiconductor layer 33 is thermally oxidized to form a gate insulating film 34 of 3 nm thick made of SiO ₂ . Subsequently, an n ⁺ polysilicon (doped polysilicon) layer 53 having a thickness of 50 nm is deposited on the entire surface by CVD or sputtering (FIG. 16).

Next, the n ⁺ polysilicon layer 5 is formed by RIE.
3 is etched back, and this is left only on the side surface of the side wall oxide film 52 as shown in FIG. 17 to form a second gate electrode made of an n ⁺ polysilicon layer 53. Next, the thickness 70n
An m-type W layer 54 is deposited by CVD or sputtering (FIG. 17).

If the resist 55 is further processed to a width of 120 nm using electron beam exposure or the like and the W layer is processed by RIE or the like using this as a mask, the second gate electrode (n
⁺ Polysilicon 53) and the W layer in the region interposed therebetween becomes the first gate electrode 54 (FIG. 18). Here, after forming the shape shown in FIG. 16, after etching back the n ⁺ polysilicon layer 53, the exposed portion of the oxide film is removed by over-etching or the oxide film is lightly etched by RIE or the like, as shown in FIG. Thus, a shape in which the gate oxide film under the first gate electrode is thinner than the gate oxide film under the second gate electrode can be obtained.

Fifth Embodiment Another embodiment and a method of manufacturing the same will be described with reference to FIGS.

On a silicon substrate 31, a buried oxide film 32 of SiO ₂ having a thickness of 400 nm
Semiconductor layer 33 (SOI) made of 0 nm single crystal silicon
Layer) is formed on the surface of the SOI substrate, a pad oxide film 60 having a thickness of 20 nm is formed on the surface thereof by thermal oxidation, and then a Si ₃ N ₄ film having a thickness of 100 nm is deposited on the entire surface by a CVD method. Lithography and RIE by exposure
The dummy nitride film 61 is formed by processing to a width of 120 nm by etching or the like. Next, high-concentration phosphorus is introduced into the semiconductor layers on both sides of the dummy nitride film 61 to form source / drain regions 38, and the whole is formed to a thickness of 120 nm by CVD.
Cover with an oxide film 62 (FIG. 19). Here, the source / drain regions may be formed by ion implantation, plasma doping, diffusion from PSG, or the like, or may be formed by epitaxial growth as in the embodiments shown in FIGS.

Subsequently, as shown in FIG. 20, an opening 7 is formed in the CVD oxide film 62 by photolithography and RIE.
0 is provided to expose the upper part of the dummy nitride film 61. At this time, the opening 70 is made wider than the dummy nitride film so that the CVD oxide film does not remain on the dummy nitride film.
For example, it is made wider by 0.2 μm on both sides. At this time, R
Instead of exposing the dummy nitride film by IE, C
The upper portion of the dummy nitride film 61 may be exposed by shaving off the protrusion of the nitride oxide film on the upper portion of the nitride film by MP (chemical mechanical polishing) (FIG. 21). In the method of exposing the upper part of the nitride film by CMP, it is not necessary to perform lithography for providing the opening 70, and the process can be shortened. In addition, there is an advantage that the formed shape becomes flat. On the other hand, in the step of exposing the dummy nitride film by lithography and RIE, there is an advantage in that the dummy nitride film can be manufactured using an existing apparatus without newly introducing a CMP apparatus.

Subsequently, the dummy nitride film 61 is removed by wet etching using hot phosphoric acid. Then, the pad oxide film 60 is removed with dilute hydrofluoric acid. At this time, CVD
The surface of oxide film 62 is also partially etched. Then CV
D, an oxide film having a thickness of 20 nm is deposited, and this is etched back to form an oxide film sidewall 40 (FIG. 22). The oxide film side wall 40 is for adjusting the surface shape of the side wall of the CVD oxide film opening formed by etching the nitride film 61 and the pad oxide film 60, and may be omitted.

Subsequently, an n ⁺ -doped polysilicon of 45 nm is entirely deposited, and this is etched back by RIE to form a side surface of the CVD oxide film 62 (or a side wall of the oxide film 40).
Is provided with an n ⁺ polysilicon layer 53 (FIG. 2).
3). Here, instead of the n ⁺ polysilicon, it may be used n ⁺ -type doped amorphous silicon.

Subsequently, the W layer 54 or TiN
And the like, and a metal compound is deposited and processed by photolithography and RIE to form a gate electrode as shown in FIG. Here, the W layer 54 becomes a first gate electrode, and the n ⁺ polysilicon 53 becomes a second gate electrode.
The processing of the first gate electrode is not performed by using photolithography and RIE, but is performed by etching back by CMP, and the upper end of the first gate electrode and the first gate electrode are formed as in FIG. The surface of an insulating film such as the CVD oxide film 62 in which the surface is embedded may be flat.
The advantages / disadvantages of using CMP are the same as described above.

Note that each of the manufacturing methods described in the first, third, fourth, and fifth embodiments uses various structures of the first and second embodiments,
The present invention can be applied to the manufacture of devices made of dimensions and materials. In addition, some steps constituting each manufacturing method may be selected and used for manufacturing various structures of the first and second embodiments. Further, the structure in which the material for forming the first gate electrode is extended on the second gate electrode as described in the fourth and fifth embodiments, the various structures and dimensions of the first and second embodiments ,
You may apply to the element which consists of a material.

In the above-described manufacturing method, the step of exposing the dummy pattern by removing the insulating film on the dummy pattern by CMP, and embedding the gate electrode material in the void of the opening after removing the dummy pattern. Thereafter, the step of flattening this by CMP may be used for manufacturing a transistor in which the gate electrode is formed of a single material (FIGS. 46 and 47).

The opening provided in the insulating film on the dummy pattern may be formed so that at least a part of the dummy pattern is exposed. This makes it possible to remove the dummy pattern by wet etching and bury the gate electrode material by CVD or the like, thereby forming a gate electrode. However, in the case of forming a gate electrode in which the first gate electrode and the second gate electrode are combined, at least the first gate electrode needs to be formed by anisotropic etchback on the side wall serving as the second gate electrode. An opening is preferably provided above the position where the gate electrode is to be formed. More preferably, the opening provided in the insulating film on the dummy pattern is preferably provided so as to expose the entire upper portion of the dummy pattern. If the opening provided in the insulating film on the dummy pattern is too narrow than the dummy pattern, the conductive material
When embedding with D or the like, before the conductive material is uniformly embedded in the opening, the upper part of the opening may be blocked by the conductive material, but by exposing the entire upper part of the dummy pattern, The conductive material can be uniformly embedded in the opening. At this time, the step of providing the opening is preferably performed by CMP. The step of providing an opening by CMP has an advantage that it is easy to expose the entire upper portion of the dummy pattern. Further, an opening provided in the insulating film on the dummy pattern may be larger than the dummy pattern. This increases the width of the upper part of the gate electrode to be formed and increases the cross-sectional area of the gate electrode (see FIG. 24; the cross-sectional area in the cross section of FIG. 24), thereby contributing to a reduction in parasitic resistance.

In the above-described manufacturing method, if CMP is used, a photolithography step does not need to be performed when removing the insulating film on the dummy pattern to expose the dummy pattern, which simplifies the process and reduces the burden on the process. In addition to reducing the number of defects, it is possible to reduce defects due to pattern misalignment due to photolithography. Further, as described above, a flat shape is obtained. In addition, a flat structure can be obtained by using a manufacturing method in which a conductive material is processed by CMP after embedding a conductive material in a void in the opening and a gate electrode is obtained.

Further, by using the dummy pattern, the source / drain region can be processed using the dummy pattern as a mask, so that the gate electrode is not affected by the heat treatment for forming the source / drain region.

The advantages of these manufacturing methods are the same for the manufacture of the transistors described in the first and second embodiments and for the manufacture of other transistors.

Further, the manufacturing method using a dummy pattern according to the present invention provides a transistor having first and second gate electrodes, having a different purpose from the structure of FIG. 1, and having a different size and a different work function. For example, it may be applied to the structure of FIG. 36). The advantage of these manufacturing methods is firstly that the formation of the pattern is easy. Generally, the larger the gate electrode is, the easier it is to process. However, in the step of first forming the first gate electrode and providing the second gate electrode on the side wall thereof, the first gate electrode is reduced to a dimension smaller than the gate length (the total length of the first and second gate electrodes). To form the gate electrode by lithography. However, in the manufacturing method of the present invention, a dummy pattern equal to the entire length of the gate may be formed by lithography.
The burden on the lithography process is reduced. The second is to reduce the effect of heat. Since the first and second gate electrodes are formed after the source / drain regions are formed using the dummy pattern as a mask, a chemical reaction occurs at the interface between the first and second gate electrodes due to the heat treatment when forming the source / drain regions. No migration of ions between interfaces occurs.

Sixth Embodiment In the present invention, in the various structures of the above embodiments, a thin oxide film (or another insulating film such as a nitride film) is provided between the first gate electrode and the second gate electrode. ) May be interposed (for example, FIGS. 26, 27, and 28). In each of the above-described manufacturing methods, a step of sandwiching a thin oxide film (or another insulating film such as a nitride film) between the first gate electrode and the second gate electrode may be added. This will be described.

If the thin oxide film 63 between the first gate electrode and the second gate electrode is too thick, it is difficult to form a channel below the thin oxide film 63. Therefore, the thinner the film, the better.
From the simulation, it was confirmed that if the film thickness was 1 nm or less, the current was not affected, and if the film thickness was 10 nm or less, the current was deteriorated but the influence was slight.

By forming the thin oxide film 63, the diffusion of impurities between the first gate electrode and the second gate electrode and the chemical reaction (for example, the metal of the first gate electrode and the second gate electrode (Reacting into silicide due to the reaction of polysilicon). Since impurity diffusion between the first gate electrode and the second gate electrode can be reduced, the first and second gate electrodes can be made of p ⁺ polysilicon and the second gate electrode of n ⁺ polysilicon. Semiconductors having different conductivity types can be used as the gate electrode of the semiconductor device.

A method of manufacturing the structure having the thin oxide film will be described. After forming the shape of FIG. 23, the surface of n ⁺ polysilicon 53 is oxidized by 2 nm to form a thin oxide film 63 as shown in FIG. At this time, the gate oxide film 4 also becomes thicker at the center. Subsequently, W is buried and planarized by CMP to obtain the shape shown in FIG. At this time, the thin oxide film 63 on the n ⁺ polysilicon 53 is removed by, for example, RIE after thermal oxidation. At this time, the thickness of the central portion of the gate oxide film also becomes thin again. Or a small amount of W
The thin oxide film 63 on the n ⁺ polysilicon 53 may be removed by RIE or wet etching after burying the gap between the n ⁺ polysilicon 53 and protecting the gate oxide film 4 by D and RIE. Here, n ⁺ polysilicon 53 is a second gate electrode, and W54 is a first gate electrode.

FIGS. 27 and 28 show FIGS.
Step 3 shows a structure in which p ⁺ polysilicon is used as the first gate electrode and n ⁺ polysilicon is used as the second gate electrode, and a thin oxide film 63 is inserted between them. Here, the thin oxide film 63 is formed of p ⁺ polysilicon 64
After patterning, the surface is oxidized (for example, 1 nm) and formed. This oxidation may be performed using heating or simply by exposure to air or an environment containing oxygen.

Referring to FIG. 28, thin oxide film 63 on p ⁺ polysilicon 64 is simultaneously removed in an etch-back process for forming oxide film sidewall 65.

FIG. 29 shows an example of a structure in which a conductor is further formed on the structure shown in FIG. In FIG. 29, a 20-nm-thick tungsten layer 66 was selectively grown on the first and second gate electrodes in order to establish electrical continuity between them. Since the tungsten layer also grows in the lateral direction, the tungsten on the first gate electrode and the second gate electrode grows and connects with each other on the thin oxide film 63, and the mutual conduction is established. A similar effect is W
Such a metal is deposited by a non-selective condition, is silicidized, and is obtained by a normal silicide process of removing excess metal with aqua regia or the like. This is because the silicide on the first gate electrode and the silicide on the second gate electrode are grown and connected respectively.

When an insulating layer is interposed between the first gate electrode and the second gate electrode, in the manufacturing method having the steps shown in FIGS. 10 to 18, the gate corresponding to the position below the second gate electrode is used. In the manufacturing method including the steps shown in FIGS. 19 to 26, the oxide film corresponding to the position below the first gate electrode is removed once, and then the first gate electrode and the second gate electrode are removed. It may be formed again at the same time as the insulating film inserted between the gate electrode and the gate electrode. For example, in the manufacturing method having the steps shown in FIGS.
When the shape shown in FIG. 1 is formed, the gate oxide film in the region where the second gate electrode does not exist is once removed by etching such as RIE, and then the gate oxide film to be located under the first gate electrode is removed. , At the same time as the formation of the thin oxide film 63. In this case, the thickness of the thin oxide film is, for example, 3 nm.
Degree. Further, thermal oxidation may be used in the step of simultaneously forming the thin oxide film 63 and the gate insulating film,
Method may be used. Also, the insulating film that is re-formed here
The material may be different from that of the initially formed gate insulating film 4 (FIG. 30). For example, Si ₃ N ₄ , Ta ₂ O ₅ or the like may be used. In this case, these thin insulating films are used instead of the thin oxide film 63 to separate the first and second gate electrodes.

After a part of the gate insulating film described above is once removed, when forming an insulating film sandwiched between the first and second gates, a part of the gate insulating film is simultaneously formed again. FIG. 30 shows an example in which the manufacturing method is applied to the structure of FIG. This is because the gate insulating film 4 is formed on the semiconductor layer 33 by thermal oxidation, and then the p ⁺ polysilicon 64 deposited by CVD is patterned to form a first gate electrode. at the same time,
Alternatively, after formation, the gate insulating film remaining on the region where the first gate electrode 64 does not exist is removed by RIE, a 7 nm Si ₃ N ₄ film 71 is deposited by CVD, and then n ⁺ poly is deposited by CVD. By depositing silicon 53 and etching back the n ⁺ polysilicon and the Si ₃ N ₄ film, a second gate electrode 53 is formed, and a tungsten layer 66 is formed thereon (the tungsten layer is a source / drain region). Alternatively, another insulating film such as SiO ₂ may be used instead of the Si ₃ N ₄ film.

In the structure shown in FIG. 30, the thin insulating film sandwiched between the first gate electrode 64 and the second gate electrode 53 and the gate insulating film below the second gate electrode are integrally formed. On the other hand, after forming the structure of FIG. 23, after removing the gate insulating film in the center,
If an insulating film is deposited on both the surface of the semiconductor layer 33 and the side surface of the second gate electrode, a thin insulating film sandwiched between the first gate electrode 64 and the second gate electrode 53, A structure in which the gate insulating film below the gate electrode is integrally formed is obtained.

Note that, as shown in FIGS. 29 and 30, a structure and a structure in which a tungsten layer 66 or another conductor such as metal, silicide, or semiconductor is provided on both the first and second gate electrodes. The manufacturing method may be applied to devices having various structures and dimensions of the first and second embodiments, which do not have the thin insulating film 63. This has the effect of reducing the parasitic resistance of the gate electrode.

Seventh Embodiment Finally, the configuration of an embodiment in which the structure below the semiconductor layer is changed will be described.

As one example, as shown in FIG.
It has the element structure shown in FIG.
Structures above and below layer 3 may be mentioned. In this case, an effect that the short channel effect can be more strongly suppressed is added. This structure can be formed by applying a double gate SOIMOSFET manufacturing process using lamination. As shown in FIG. 1, once a gate electrode on one side is formed, a buried oxide film 2 is deposited on the gate electrode, and a supporting substrate is adhered on the buried oxide film 2 by a bonding step.
The wafer may be inverted to remove the original supporting substrate and the buried oxide film, exposing the SOI layer 3, and forming a gate electrode similar to that of FIG. The upper gate electrode may be positioned with respect to the element region (field layer) or the lower gate. Another example having the element structure shown in FIG. 1 is a structure in which a lower portion of an SOI layer is formed of a material layer 81 having a lower dielectric constant than SiO ₂ , as shown in FIG. For example, porous SiO ₂ or an organic film may be used. As shown in FIG. 33, the lower part of the SOI layer is a cavity 82 and the SOI layer is an insulator 83 (for example, SiO _2).
Or Si ₃ N ₄ side walls).
In this case, the electric field from the source / drain region to the channel through the buried oxide film is reduced, so that the short channel effect can be suppressed more strongly. Structure shown in FIG. 33, after forming the structure shown in FIG. 1, is provided a sidewall 83 the Si ₃ N ₄ by etch back using CVD and RIE, an opening is formed by photolithography in a portion the Si ₃ N ₄ sidewall, It can be formed by removing SiO ₂ from the opening by etching with hydrofluoric acid or the like.

When the seventh embodiment is applied to the structure of each of the first to sixth embodiments, or various structures obtained by combining them, the same effect as when applied to the structure of FIG. 1 is obtained. can get.

In the first to seventh embodiments, the following dimensions, materials, conditions and the like may be used.

In the above description, an n-channel transistor has been mainly described as an example. However, in a p-channel transistor, the polarities may be all reversed. For example, the source / drain regions may be p-type with boron introduced, the first gate electrode may be formed of TiN, W, or the like, and the second gate electrode may be formed of p ⁺ polysilicon. The work function of the second gate electrode may be larger than the work function of the first gate electrode. Making the first gate electrode length 40 nm or less is n
This is similar to the case of the channel transistor.

In the present invention, the impurities introduced into the source / drain regions are not limited to those described above.
Phosphorus, arsenic or other donors may be used for a channel transistor, and boron or another acceptor may be used for a p-channel transistor. The concentration of these impurities introduced into the source / drain regions is generally 5 × 10 ¹⁸ cm ⁻³ to 2 × 10 ²¹ cm ⁻³ , typically 1 × 10 ¹⁸ cm ^−3.
It is in the range of × 10 ¹⁹ cm ^-3 to 2 × 10 ²⁰ cm ^-3 , and may be set so as to realize a reduction in the resistance of the source / drain region and an assurance of the crystallinity.

From the viewpoint of solving the first and second problems, it is most preferable not to introduce impurities into the channel region. However, it is preferable to suppress punch-through of the transistor on the bulk substrate or to prevent back-up of the SOI transistor. A small amount of impurities may be introduced for the purpose of suppressing channel formation. As an impurity to be introduced into the channel region, boron or another acceptor may be used for an n-channel transistor, and phosphorus, arsenic, or another donor may be used for a p-channel transistor. The concentration of these impurities is typically between 2 × 10 ¹⁷ cm ⁻³ and 2 × 10 ¹⁸
cm ^-3 . Even when such a small amount of impurities are introduced, in the transistor of the present invention,
Compared to a normal structure (a structure in which n ⁺ polysilicon is used for an n-channel transistor and p ⁺ polysilicon is used for a p-channel transistor as a gate electrode), a larger amount of impurities is introduced to set a threshold value. There is an advantage that the impurity concentration can be suppressed because it is not necessary.

Conversely, a small amount of phosphorus, arsenic or another donor may be introduced into a semiconductor layer (or a semiconductor substrate) in an n-channel transistor, and boron or another acceptor may be introduced in a p-channel transistor.
This is a necessary measure mainly when a material other than n ⁺ polysilicon is used for the n-channel transistor and a material other than p ⁺ polysilicon is used for the p-channel transistor for the gate electrode. In the present invention, the electric field of the first gate electrode is weakened, so that the introduction of these impurities can be omitted. However, the amount of impurities required in combination with the method of introducing these impurities can be reduced.

The impurity concentrations of n ⁺ polysilicon and p ⁺ polysilicon are the same as the range of the concentration introduced into the source / drain regions. These may be replaced with n ⁺ amorphous silicon and p ⁺ amorphous silicon.

[0126]

As is apparent from the above description, according to the device structure of the present invention, the introduction of impurities is not required, the concentration of impurities can be suppressed, and the threshold voltage can be freely adjusted. It becomes possible to set. Further, according to the element structure of the present invention, the short channel effect can be suppressed by an original principle.

Further, according to the manufacturing method of the present invention, it is possible to satisfactorily manufacture a field effect transistor having the above effects.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure of the present invention.

FIG. 2 is a sectional view showing the structure of the present invention.

FIG. 3 is a sectional view showing the structure of the present invention.

FIG. 4 is a sectional view showing the structure of the present invention.

FIG. 5 is a sectional view showing the structure of the present invention.

FIG. 6 is a sectional view showing the structure of the present invention.

FIG. 7 is a sectional view showing the structure of the present invention.

FIG. 8 is a sectional view showing the structure of the present invention.

FIG. 9 is a sectional view showing the structure of the present invention.

FIG. 10 is a cross-sectional view for explaining the structure and the manufacturing method of the present invention.

FIG. 11 is a cross-sectional view for explaining the structure and the manufacturing method of the present invention.

FIG. 12 is a cross-sectional view for explaining the structure and the manufacturing method of the present invention.

FIG. 13 is a cross-sectional view for explaining the structure and the manufacturing method of the present invention.

FIG. 14 is a cross-sectional view for explaining the structure and the manufacturing method of the present invention.

FIG. 15 is a cross-sectional view for explaining the structure and the manufacturing method of the present invention.

FIG. 16 is a cross-sectional view for explaining the structure and the manufacturing method of the present invention.

FIG. 17 is a cross-sectional view for explaining the structure and the manufacturing method of the present invention.

FIG. 18 is a cross-sectional view for explaining the structure and the manufacturing method of the present invention.

FIG. 19 is a cross-sectional view for explaining the structure and the manufacturing method of the present invention.

FIG. 20 is a cross-sectional view for explaining the structure and the manufacturing method of the present invention.

FIG. 21 is a cross-sectional view for explaining the structure and the manufacturing method of the present invention.

FIG. 22 is a cross-sectional view for explaining the structure and the manufacturing method of the present invention.

FIG. 23 is a cross-sectional view for explaining the structure and the manufacturing method of the present invention.

FIG. 24 is a cross-sectional view for explaining the structure and the manufacturing method of the present invention.

FIG. 25 is a cross-sectional view for explaining the structure and the manufacturing method of the present invention.

FIG. 26 is a cross-sectional view for explaining the structure and the manufacturing method of the present invention.

FIG. 27 is a cross-sectional view for explaining the structure and the manufacturing method of the present invention.

FIG. 28 is a cross-sectional view for explaining the structure and the manufacturing method of the present invention.

FIG. 29 is a cross-sectional view for explaining the structure and the manufacturing method of the present invention.

FIG. 30 is a sectional view showing the structure of the present invention.

FIG. 31 is a sectional view showing the structure of the present invention.

FIG. 32 is a sectional view showing the structure of the present invention.

FIG. 33 is a sectional view showing the structure of the present invention.

FIG. 34 is a cross-sectional view illustrating a conventional technique.

FIG. 35 is a cross-sectional view illustrating a conventional technique.

FIG. 36 is a cross-sectional view illustrating a conventional technique.

FIG. 37 is a cross-sectional view illustrating a conventional technique.

FIG. 38 shows an effect of the present invention.

FIG. 39 is a view showing an effect of the present invention.

FIG. 40 shows an effect of the present invention.

FIG. 41 shows an effect of the present invention.

FIG. 42 is a cross-sectional view of a transistor for illustrating the operation principle of the present invention.

FIG. 43 is a diagram showing a potential distribution for describing an operation principle of the present invention.

FIG. 44 is a diagram showing a potential distribution for describing an operation principle of the present invention.

FIG. 45 is a diagram showing a potential distribution for describing an operation principle of the present invention.

FIG. 46 is a view showing an element structure manufactured by a manufacturing method of the present invention.

FIG. 47 is a view showing an element structure manufactured by the manufacturing method of the present invention.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 support substrate 2 buried oxide film 3 semiconductor layer 4 gate insulating film 5 gate electrode 6 source / drain region 7 first gate electrode 8 n ⁺ polysilicon 9 channel formation region 10 silicon substrate 21 LDD region 22 extension region 31 silicon substrate 32 Buried oxide film 33 semiconductor layer 34 gate insulating film 35 first gate electrode 36 resist 37 n ⁺ polysilicon layer 38 source / drain region 39 channel formation region 40 oxide film sidewall 41 epitaxial layer 42 polycrystalline layer 51 dummy oxide film 52 sidewall oxide film 53 n ⁺ polysilicon layer 54 first gate electrode 55 photoresist 60 pad oxide film 61 dummy oxide film 62 CVD oxide film 63 thin oxide film 64 p ⁺ polysilicon 65 oxide film sidewall 66 tungsten layer 70 openings 71 S ₃ N ₄ film 81 SiO lower material layer 82 cavity 83 dielectric constant than _second insulator 101 silicon substrate 102 a gate oxide film 103 gate electrode 104 channel forming region 105 source and drain regions 110 buried oxide film 111 SOI layer 112 insulating film 113 Tantalum gate electrode 115 p ⁺ polysilicon gate 116 n ⁺ polysilicon gate 117 n ⁻ type inversion layer 160 support substrate 161 buried oxide film 162 source / drain region 163 gate insulating film 164 first gate electrode 165 second gate electrode 166 Semiconductor layer 167 Channel formation region

Claims (16)

(57) [Claims] A gate electrode is provided on a semiconductor via an insulating film, a semiconductor layer below the gate electrode forms a channel formation region, and a source / drain region of a first conductivity type is formed across the channel formation region. In the formed field-effect transistor, the gate electrode comprises a first gate electrode located at the center thereof and second gate electrodes located on both sides thereof, and at least a part of the second gate electrode Is located on the channel forming region, and when the first conductivity type is n-type, the work function of the second gate electrode is smaller than the work function of the first gate electrode, and the first conductivity type is p-type. In the case where the work function of the second gate electrode is larger than the work function of the first gate electrode and the threshold voltage is applied to the gate electrode and the first conductivity type is n-type, The potential of the layer is An electric field that is higher than the gate electrode, and an electric field that makes the potential of the semiconductor layer lower than the gate electrode when the first conductivity type is p-type.
The first gate electrode has a distance between both interfaces in contact with the second gate electrode, that is, a length of the first gate electrode, such that the second gate electrode is formed at the center of the gate electrode. , Field-effect transistors. 2. A semiconductor device comprising: a gate electrode provided on a semiconductor via an insulating film; a semiconductor layer below the gate electrode forms a channel formation region; and a first conductivity type source / drain region sandwiches the channel formation region. In the formed field-effect transistor, the gate electrode comprises a first gate electrode located at the center thereof and second gate electrodes located on both sides thereof, and at least a part of the second gate electrode Is located on the channel forming region, and when the first conductivity type is n-type, the work function of the second gate electrode is smaller than the work function of the first gate electrode, and the first conductivity type is p-type. In the case of, the work function of the second gate electrode is larger than the work function of the first gate electrode, and the distance between the two interfaces in contact with the second gate electrode in the first gate electrode, that is, 40n in length
m or less, and a field-effect transistor. 3. A gate electrode is provided on a semiconductor via an insulating film, a semiconductor layer below the gate electrode forms a channel formation region, and a source / drain region of a first conductivity type sandwiches the channel formation region. In the formed field-effect transistor, the gate electrode comprises a first gate electrode located at the center thereof and second gate electrodes located on both sides thereof, and at least a part of the second gate electrode Is located on the channel forming region, and when the first conductivity type is n-type, the work function of the second gate electrode is smaller than the work function of the first gate electrode, and the first conductivity type is p-type. In the case of, the work function of the second gate electrode is larger than the work function of the first gate electrode, and the distance between the two interfaces in contact with the second gate electrode in the first gate electrode, that is, When the length is T _m and the threshold voltage of the transistor is V _th , the absolute value of the coefficient dV _th / dT _m obtained by differentiating V _th by T _m is 4 ×
2. The field effect transistor according to claim 1, wherein _Tm is set in a range larger than 10 ^-3 V / nm. 4. The field effect transistor according to claim 1, wherein an extension of the first gate electrode is provided above the second gate electrode. 5. The field-effect transistor according to claim 1, wherein an insulating film is interposed between the first gate electrode and the second gate electrode. 6. The field effect transistor according to claim 5, wherein a conductor connected to both the first gate electrode and the second gate electrode is provided above the first gate electrode and the second gate electrode. 7. The method for manufacturing a field-effect transistor according to claim 1, wherein a dummy pattern is formed, and a source / drain region is formed in a semiconductor on both sides of the dummy pattern using the dummy pattern as a mask. Is covered with an insulating film, an opening is provided in the insulating film on the dummy pattern, the dummy pattern is removed by etching from the opening, the opening is extended downward, and the first conductive material is provided in the extended opening. By depositing a conductive material and etching it back, a sidewall is provided in the opening, and then a second conductive material is deposited and patterned, whereby the sidewall is formed by the second gate electrode and the second gate electrode. A method for manufacturing a field-effect transistor, wherein a second conductive material is used as the first gate electrode. 8. A method of depositing a first conductive material in an extended opening and etching back the first conductive material to form an opening in the opening.
8. The field effect type according to claim 7 , wherein after providing a side wall made of the first conductive material , an insulating film is formed on a surface of the side wall, and subsequently, a second conductive material is deposited. A method for manufacturing a transistor. 9. The semiconductor device according to claim 1, wherein the extended surface has a semiconductor surface.
First conductive material is deposited via a gate insulating film on the
The first conductive material is etched back to open
After providing the side wall made of the first conductive material at the mouth,
Is provided on the semiconductor in a region where the side wall does not exist.
The gate insulating film that has been removed is removed, and
Forming an insulating film on the surface of the side wall and the semiconductor surface,
And depositing a second conductive material.
A method for manufacturing a field-effect transistor according to claim 7. 10. An opening made of a first conductive material.
After the side wall is provided,
Removing the gate insulating film provided on the semiconductor,
Surface of a sidewall made of a first conductive material and the semiconductor surface
Characterized by forming an insulating film on the surface by thermal oxidation,
A method for manufacturing a field-effect transistor according to claim 9. 11. An opening made of a first conductive material.
After the side wall is provided,
Removing the gate insulating film provided on the semiconductor,
Surface of a sidewall made of a first conductive material and the semiconductor surface
For CVD on the surface Characterized by forming an insulating film more,
A method for manufacturing a field-effect transistor according to claim 9. 12. An opening made of a first conductive material.
After the side wall is provided,
Removing the gate insulating film provided on the semiconductor,
Surface of a sidewall made of a first conductive material and the semiconductor surface
Si on the surface _Three N _Four Membrane or Ta _Two O _Five Characteristic of forming a film
10. The method for manufacturing a field effect transistor according to claim 9, wherein
Law. 13. The method for manufacturing a field-effect transistor according to claim 1, wherein a dummy pattern is formed, and source / drain regions are formed in the semiconductor on both sides of the dummy pattern using the dummy pattern as a mask. Is covered with an insulating film, an opening is provided in the insulating film on the dummy pattern, the dummy pattern is removed by etching from the opening, the opening is extended downward, and the first conductive material is provided in the extended opening. By depositing a conductive material and etching it back, a side wall is provided in the opening, a second conductive material is deposited at least in a region including the opening, and then a second conductive material is deposited in a region excluding the opening. Wherein the conductive material is removed by CMP, a side wall inside the opening is used as the second gate electrode, and a second conductive material embedded in the opening is used as the first gate electrode. Method of manufacturing a field-effect transistor. 14. an upper portion of the first gate electrode, and the upper portion of the second gate electrode, and wherein the growing the conductor connected to the gate electrodes of both claim 7
14. A method for manufacturing a field-effect transistor according to claim 13 . 15. The method according to claim 15, further comprising:
Selectively grow tungsten on top of second gate electrode
To connect to both of these gate electrodes.
The method according to claim 14, wherein the conductor is grown.
Method for manufacturing a field-effect transistor. 16. The method according to claim 16, further comprising the step of:
The top of the gate electrode, And a sidewall made of a first conductive material
A first gate electrode on top of the insulating film provided on the surface of
Grow a conductor connected to both the first and second gate electrodes
14. The electric field effect according to claim 7, wherein:
Method of manufacturing a type transistor.