KR100811424B1 - Method for manufacturing semiconductor device - Google Patents

Abstract

The present invention relates to a method for manufacturing a semiconductor device, and may form a thin first gate polysilicon layer and then perform source / drain ion implantation and C-halo ion implantation to mitigate changes in the impurity concentration distribution of the junction. In addition, the present invention discloses a technique of reducing ion implantation energy to reduce penetration of boron into the storage electrode region to improve refresh characteristics and process margins.

Description

Method for manufacturing a semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
3a to 3c are simulations and graphs showing the distribution of boron particles immediately after ion implantation of the prior art and the present invention.

The present invention relates to a method for manufacturing a semiconductor device, and to reduce the change in the impurity concentration distribution of the junction by performing a second source / drain ion implantation process and a C-halo ion implantation process after forming a thin first gate polysilicon layer In addition, the present invention discloses a technique of reducing ion implantation energy to reduce penetration of boron into the storage electrode region to improve refresh characteristics and process margins.

As the recent design rule becomes smaller, the Cell-Vt dose increases to meet the Vt target, and the increase of the Tr threshold voltage dose increases the electric field of the storage electrode junction, which increases the leakage current and decreases the refresh time. do. Accordingly, a method of improving the refresh characteristics by performing a C-halo ion implantation process on the bit line contact region while reducing the Cell-Vt dose is used.

1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

Referring to FIG. 1A, a first source / drain ion implantation process may be performed on an upper portion of a semiconductor substrate 10 provided with an isolation layer 15.

Referring to FIG. 1B, the recess gate region 30 is formed by etching the active region of the semiconductor substrate 10 to a predetermined depth.

In this case, the bit line contact region 31 is defined, and the storage electrode contact region 33 is defined at both sides of the bit line contact region 31.

1C and 1D, a gate oxide film 35 having a predetermined thickness is formed on the entire surface of the semiconductor substrate 10 including the recess gate region 30, and the gate filling the recess gate region 30. The polysilicon layer 40 is formed.

Referring to FIG. 1E, after forming the photoresist pattern 43 exposing the bit line contact region 31, a C-halo ion implantation process is performed using the photoresist pattern 43 as a mask to the bit line contact region 31. The boron ion implantation region is formed.

At this time, the gate polysilicon layer 40 is formed to a thickness of 1200 to 1500Å, the ion implantation is performed with an energy of 40 to 50 KeV so that boron ions can sufficiently pass through the thickness of the gate polysilicon layer 40. do.

1F and 1G, after forming a lamination structure of the gate metal layer 45 and the gate hard mask layer 50 on the gate polysilicon layer 40, the lamination structure and the gate polysilicon layer 40 are formed. Is patterned to form a gate.

In this case, the C-halo ion implantation process was performed after the gate polysilicon layer was formed in order to prevent a region that is not implanted during the C-halo ion implantation process due to misalignment between the recess gate region and the gate.

In the above-described method of manufacturing a semiconductor device according to the related art, when the C-halo ion implantation process is performed after the gate polysilicon layer is formed, the ion implantation energy is increased so as to pass through the thickness of the gate polysilicon layer. Although no misalignment occurs between the recess gate region and the gate, a considerable amount of boron ions penetrate into the storage electrode region.

Therefore, the distribution characteristic of the threshold voltage is deteriorated, and the refreshing characteristic is deteriorated by increasing the junction electric field of the storage electrode. In addition, as the design rule decreases to improve the degree of integration, the phenomenon of penetration of boron ions into the storage electrode region during C-halo ion implantation increases rapidly.

In addition, when only one ion implantation is performed to form the source / drain junction, there is a difficulty in optimizing the junction concentration to improve the refresh characteristics and minimize the loss of the driving current.

In order to solve the above problems, after forming the first gate polysilicon layer with a thin thickness, a source / drain ion implantation process is performed, and a C-halo ion implantation process is performed in the bit line contact region, but the C-halo ion The implanted energy may be performed to compensate the input depth by the thickness difference between the conventional gate polysilicon layer and the first gate polysilicon layer, thereby reducing the penetration of boron ions into the storage electrode region. In addition, the planar etching process is performed after the second gate polysilicon layer is formed to prevent generation of a seam during the formation of the gate metal layer and the hard mask layer formed in a subsequent process.

Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device that improves threshold voltage fluctuations and refresh characteristics.

Method for manufacturing a semiconductor device according to the present invention

Performing a primary source / drain ion implantation process on the semiconductor substrate;

Etching the semiconductor substrate to a predetermined depth to form a recess gate region;

Forming a gate oxide film having a predetermined thickness on an entire surface including the recess gate region;

Performing a second source / drain ion implantation process after forming the first gate polysilicon layer filling the recess gate region;

Forming a photoresist pattern exposing a bit line contact region on the first gate polysilicon layer, and performing a C-halo ion implantation process using the photoresist pattern as a mask;

Removing the photoresist pattern and forming a second gate polysilicon layer on the first gate polysilicon layer;

Forming a stacked structure of a gate metal layer and a hard mask layer on the second gate polysilicon layer;

And patterning the stacked structure and the first and second gate polysilicon layers to form a gate.

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Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Although not shown, the device isolation film forming process will be described. A layer structure of a pad oxide film and a pad nitride film is formed on a semiconductor substrate, and the pad nitride film and the pad oxide film are etched to a predetermined depth to form a trench defining an active region.

Next, the trench is filled with an oxide film to form an element isolation film.

Here, the pad oxide film is formed to a thickness of 50 to 100 GPa, and the pad nitride film is formed to a thickness of 1500 to 2000 GPa.

Referring to FIG. 2A, a primary source / drain ion implantation process is performed on a semiconductor substrate 100 provided with an isolation layer 110 to form a primary ion implantation region 120.

Here, the primary source / drain ion implantation process uses arsenic (Arsenic) or antimony (Antimony) to implant the ion at an energy of 10 to 30 KeV to improve the contact resistance.

Referring to FIG. 2B, the recess 125 is formed by etching the semiconductor substrate 100 by a predetermined depth.

In this case, the bit line contact region 127 is defined, and the storage electrode contact region 129 is defined at both sides of the bit line contact region 127.

Referring to FIG. 2C, the gate oxide layer 130 is formed on the entire surface of the semiconductor substrate 100 including the recess 125.

Referring to FIG. 2D, after forming the first gate polysilicon layer 140a over the entire region including the recess 125, the secondary ion implantation region 145 is formed by performing a secondary source / drain ion implantation process. Form.

Here, the first gate polysilicon layer 140a is formed to be thinner than the conventional thickness of 300 to 500 내지, and the secondary source / drain ion implantation process is ion implanted with energy of 40 to 50 KeV using phosphorus (Phosphorus). In this way, the impurity distribution is smoothed to improve the refresh characteristics.

In this case, since the secondary ion implantation process is performed using more energy than the primary ion implantation process, the secondary ion implantation region 145 is formed deeper than the primary ion implantation region 120.

Referring to FIG. 2E, after forming the photoresist pattern 150 exposing the bit line contact region 127, a C-halo ion implantation process is performed using the photoresist pattern 150 as a mask to the bit line contact region 127. C-halo ion implantation region 155 is formed.

At this time, by forming the first gate polysilicon layer 140a thin and performing a C-halo ion implantation process with low energy, the phenomenon that boron ions penetrate into the source junction can be reduced. Here, the C-halo ion implantation process is ion implanted with an energy of 10 to 15 KeV using boron to make the maximum concentration depth of the boron less than 400 kW from the surface of the semiconductor substrate, more preferably 200 to 400 kW Make sure to inject into the depth of
The C-halo ion implantation region 155 formed by performing the C-halo ion implantation process is formed deeper than the primary and secondary ion implantation regions 120 and 145.

Referring to FIG. 2F, after removing the photoresist pattern 150, a second gate polysilicon layer 140b is formed on the first gate polysilicon layer 140a.

Here, the second gate polysilicon layer 140b is formed to a thickness of 700 to 1000 GPa.

Next, a planarization etching process may be performed to leave the stacked thickness of the first gate polysilicon layer 140a and the second gate polysilicon layer 140b of 500 to 1000 mm 3.

Referring to FIG. 2G, after forming a lamination structure of the gate metal layer 165 and the gate hard mask layer 170 on the gate polysilicon layer 143, the lamination structure and the gate polysilicon layer 143 are patterned to form a gate. And a spacer 180 on the sidewalls of the gate.

Here, the gate metal layer 165 is formed to a thickness of 1000 to 1500Å, and the gate hard mask layer 170 is formed to a thickness of 1500 to 2000Å.

3A to 3C are simulations and graphs showing the distribution of boron particles immediately after ion implantation of the prior art and the present invention.

FIG. 3A illustrates a simulation in which the ion implantation process is performed at an energy of 45 KeV after the formation of the gate polysilicon layer of 1100 kV according to the prior art, and FIG. 3B is the formation of the first gate polysilicon layer of 300 kV according to the present invention. The simulation is performed when the ion implantation process is performed at an energy of 20 KeV. Referring to the concentration of boron at the position A, it can be seen that FIG. 3A according to the prior art has a significant amount of boron ions penetrated to the storage electrode region. have.

Referring to FIG. 3C, concentrations of boron according to ion implantation energies of lines A and B of FIGS. 3A and 3B are compared. The concentration is based on the depth at which the concentration of boron is maximized as the ion implantation energy increases. It can be seen that the distance to become the level is increased, and when performing the ion implantation process according to the invention it can be seen that the reduction of 40 to 55% compared to the prior art.

Here, the threshold voltage is determined by the boron concentration of the bit line region, and when the boron concentration of the storage electrode region is increased, the refresh characteristic of the device is deteriorated. Therefore, when the ion implantation energy is low, the phenomenon that boron penetrates into the storage electrode region at the same threshold voltage is reduced than in the high case, thereby improving the refresh characteristics.

In the method of manufacturing a semiconductor device according to the present invention, the first gate polysilicon layer may be thinly formed, and then the second source / drain ion implantation process and the C-halo ion implantation process may be performed to mitigate the change in the impurity concentration distribution of the junction. In addition, the ion implantation energy may be reduced to reduce penetration of boron into the storage electrode contact region, thereby improving refresh characteristics and process margins.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (11)

Performing a primary source / drain ion implantation process on the semiconductor substrate; Etching the semiconductor substrate to a predetermined depth to form a recess gate region; Forming a gate oxide layer having a predetermined thickness on an entire surface including the recess gate region; Performing a second source / drain ion implantation process after forming a first gate polysilicon layer filling the recess gate region; Forming a photoresist pattern exposing a bit line contact region on the first gate polysilicon layer, and performing a C-halo ion implantation process using the photoresist pattern as a mask; Removing the photoresist pattern and forming a second gate polysilicon layer on the first gate polysilicon layer; Forming a stacked structure of a gate metal layer and a hard mask layer on the second gate polysilicon layer; And Patterning the stacked structure and the first and second gate polysilicon layers to form a gate Method of manufacturing a semiconductor device comprising a. The method of claim 1, The first source / drain ion implantation process is a method of manufacturing a semiconductor device, characterized in that the ion implantation using an arsenic (Arsenic) or antimony (Antimony) at an energy of 10 to 30 KeV. The method of claim 1, The first gate polysilicon layer is a manufacturing method of a semiconductor device, characterized in that formed to a thickness of 300 to 500Å. The method of claim 1, The secondary source / drain ion implantation process is a method of manufacturing a semiconductor device, characterized in that the ion implantation using an energy of 40 to 50 KeV using Phosphorus. The method of claim 1, The second gate polysilicon layer is a manufacturing method of a semiconductor device, characterized in that formed in a thickness of 700 to 1000Å. The method of claim 1, The C-halo ion implantation process is a method of manufacturing a semiconductor device, characterized in that the ion implantation using energy of 10 to 15 KeV using Boron. The method of claim 6, The boron is a method of manufacturing a semiconductor device, characterized in that the ion implantation to a depth of 200 ~ 400Å from the surface of the semiconductor substrate. The method of claim 1, And forming a planar etching process after the second gate polysilicon layer is formed. The method of claim 8, The planarization etching process is a method of manufacturing a semiconductor device, characterized in that the stacking thickness of the first and second gate polysilicon layer is left to 500 to 1000Å. The method of claim 1, The ion implantation region formed by the C-halo ion implantation process is formed deeper than the ion implantation region formed by the primary and secondary source / drain ion implantation process. The method of claim 10, The ion implantation region formed by the secondary source / drain ion implantation process is formed deeper than the ion implantation region formed by the primary source / drain ion implantation process.

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