JPH0794686A - Nonvolatile semiconductor device and fabrication thereof - Google Patents

Abstract

PURPOSE:To prevent write disturb by employing an NOR type bit contactless cell and suppressing the fluctuation of writing time between the memory cells of an EEPROM in Virtual Ground Memory array. CONSTITUTION:P-wells 16 made in an SOI substrate are isolated electrically for each memory cell in the direction of a word line 4. In the direction of a bit line 6, an N-type diffusion layer 3 is formed continuously to constitute a second bit line and the P-wells 16 are formed continuously for a predetermined number of memory cells and connected electrically with the bit line 6 through select transistors thus constituting a first bit line. At the time of erase and write operations, the first bit line functions as a select line along with the word line 4 and the second bit line functions as the select line only at the time of read operation when high voltage is not applied. Erasure and writing are effected through FN tunneling and electrons communicate between a floating gate 11 and the P-well 16 over the entire surface of channel region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an EPROM (Erasable
and Programmable Read Only Memory) and EEPROM
(Electrically Erasable and Programmable Read Only
Memory) and a method for manufacturing the same.

[0002]

2. Description of the Related Art A typical non-volatile PROM (Pr
Programmable Read Only Memory), which is an EPROM that writes electrically and erases all at once by UV irradiation.
There is an electrically writable and erasable EEPROM.

A novel cell structure of such a non-volatile semiconductor memory device is "A NOVEL MEMORY CELL USING FLASH ARR".
AY CONTACTLESS EPROM (FACE) TECHNOLOGY "(BJ Woo
et al .: IEDM 90, pp.91-94: 1990 IEEE).

The feature of the cell array described in the first document is that the source / drain diffusion layer of each memory cell also serves as a bit line as it is, and the drain contact for each memory cell which has been conventionally present in this type of NOR type cell array. It is possible to reduce the cell size by omitting. The bit line is configured to be applied with the reference potential or the program voltage, and therefore, the circuit is a virtual ground type array.

However, in the configuration described in the first document,
Since the source / drain diffusion layer serving as a bit line is formed in common with the source / drain diffusion layers of the memory cells adjacent in the word line direction, and also serves as the source / drain of the memory cells adjacent in the word line direction, For example, at the time of writing, there is a drawback that write disturb (erroneous writing) of unselected cells adjacent in the word line direction is likely to occur.

As a means for overcoming this drawback, "A 1.28
μm ² Contactless Memory Cell Technology for a 3V-O
nly 64Mbit EEPROM "(Kume et al .: IEDM 92, pp.991-993:
1992 IEEE).

The technique described in the second document will be described below with reference to FIGS.

The features of the cell structure described in the second document are as follows.
The source / drain diffusion layers used as bit lines are not used also as the source / drain of the memory cells located on both sides of the source / drain diffusion layer, and the insulating film for element isolation is improved to
That is, the drain diffusion layer is separated and independent for each memory cell in the direction along the word line.

FIG. 15 is a circuit diagram of the cell array described in the second reference, FIG. 16 is a sectional view taken along the bit line, and FIG. 17 is a sectional view taken along the word line.

As shown in FIG. 17, a SiO ₂ film 101 for element isolation is formed on the surface of a P well 116 of a CMOS.
Is formed, and the N-type diffusion layer 103 is formed on the lower side thereof. Then, a floating gate 111 is formed in the element region between the SiO ₂ films 101 via a tunnel oxide film 113, and a silicon oxide film / silicon nitride film / silicon oxide film (ONO film) is formed on the floating gate 111. ) 11
4, the word line 104 which is a control gate is formed. Further, the interlayer insulating film 11 is formed on the word line 104.
5 is formed, and the main bit line 106 made of a metal wiring is formed on the interlayer insulating film 115.

Although not shown in the drawing, the N-type diffusion layer 1
03 are continuously formed in the longitudinal direction of the main bit line 106 (direction perpendicular to the paper surface). Further, as shown in FIG. 16, each memory cell is separated by the parasitic channel stopper P-type diffusion layer 112 in the bit line direction.

In the structure described in the second document, as shown in FIG. 17, a protruding portion 101a protruding downward is formed at the bottom of the SiO ₂ film 101, and the protruding portion 101 is formed.
The N-type diffusion layer 103 is divided into two by a. That is, the N-type diffusion layer 103 is the SiO ₂ film 10 for element isolation.
The memory cells on both sides sandwiching 1 function independently of each other and are not shared by the memory cells on both sides sandwiching the element isolation insulating film as described in the above-mentioned first document. Therefore, in the configuration shown in the figure, the N-type diffusion layer 103 can be fixed to one of the source and the drain in each memory cell, and it is not necessary to form the virtual ground type array.

Then, as shown in FIG. 15, one of the N-type diffusion layers, which is the source, is connected to the sub-source line 10 in the P-well.
7 and is connected to the main source line 108 via the selection transistor 121. The other N-type diffusion layer, which is the drain, functions as the sub bit line 105 in the P well, and the main bit line 1 via the select transistor 120.
It is connected to 06.

As shown in the figure, the array has a NOR type configuration, and there are 32 memory cells (referred to as "1 block") between the selection transistors 120 and 121, which is circuit-wise. For each gate, W
Word lines 104 indicated by _{0 to} W ₃₁ are connected.
The selection transistors 120 and 121 prevent stress on the source or drain of the memory cell in the non-selected block and avoid write (program) disturb.

Next, the EEPROM described in the second document
The operation will be described with reference to FIGS. 18 (a) to 18 (c).

FIG. 18A is an explanatory diagram showing the bias state during the erase operation. For example, when the memory cell M ₂₀ is erased, 13 V is applied only to the selected word line W ₂ and the remaining non-current is applied. 0V is applied to the selected word lines W ₀ , W ₁ , W _{3 to} W ₃₁ . Further, ₀ V is applied to the main bit lines D ₀ and D ₁ , the main source line 108, and the P well 116, respectively, and the gate electrodes ST of the selection transistors 120 and 121 are applied.
3V is applied to each of ₁ and ST ₂ , the selection transistors 120 and 121 are turned on, and 0V is applied to each of the sub-bit line 105 and the sub-source line 107. As a result, in all the memory cells connected to the selected word line W ₂ , electrons are injected from the P well 116 shown in FIG. 17 to the floating gate 111 via the tunnel oxide film 113, and erasing is performed. . That is, in this case,
Sector erase is performed in which all memory cells connected to the selected word line W ₂ are erased.

FIG. 18B is an explanatory diagram showing the bias state during the read operation. For example, when the memory cell M ₂₀ is selected, 3 V (V _cc ) is applied only to the word line W ₂ and the remaining non-current is applied. 0V is applied to the selected word lines W ₀ , W ₁ , W _{3 to} W ₃₁ . Further, ₁ V is applied to the main bit line D ₀ , and 0 V is applied to the main bit line D ₁ , the main source line 108 and the P well 116, respectively, and the selection transistors 120 and 12 are selected.
3V (V _cc ) is applied to each of the gate electrodes ST ₁ and ST ₂ of ₁ to turn on the selection transistors 120 and 121, so that 1 is applied to the sub-bit line 105 which is electrically connected to the main bit line D _0.
V, 0V is applied to the sub-bit line 105 and the sub-source line 107 which are electrically connected to the main bit line D ₁ . In this state,
The current flowing in the memory cell M ₂₀ is detected,
₂₀ readings are done.

FIG. 18C is an explanatory view showing the bias state during the write operation. For example, when writing to the memory cell M ₂₀ , -9V is applied only to the word line W ₂ and the remaining non-selected words. 3V is applied to the lines W ₀ , W ₁ , W _{3 to} W ₃₁ . Further, 3 V is applied to the main bit line D ₀ , ₀ V is applied to the main bit line D ₁ , the main source line 108 and the P well 116, respectively, and 3 V is applied to the gate electrode ST ₁ of the selection transistor 120 and the gate electrode of the selection transistor 121. 0V is applied to ST ₂ to select transistor 1
20 is turned on, the selection transistor 121 is turned off, 3 V is applied to the sub-bit line 105 which is electrically connected to the main bit line D _0, and the sub-bit line 105 and the sub-source line 10 which are electrically connected to the main bit line D ₁ are connected.
0V is applied to 7 respectively. As a result, Fowler-Nordheim tunneling (hereinafter referred to as “FN” is performed through the tunnel oxide film 113 shown in FIG. 17).
Tunneling ". ) Happened, floating gate 1
The electrons in 11 are extracted to the N-type diffusion layer 103 on the drain side, and the memory cell M ₂₀ is written.

[0019]

In the conventional nonvolatile semiconductor memory device described with reference to FIGS. 15 to 18, in order to prevent write disturb, as shown in FIG. 17, a SiO ₂ film 101 for element isolation is formed. 1 on the bottom of the
There is a drawback that a complicated structure such as the provision of 01a must be taken especially in the manufacturing process.

Also in the non-volatile semiconductor memory device described in the second document, as in the structure described in the first document, the tunnel oxide film 113 and the SiO ₂ film 101 for element isolation at the time of writing. Since the FN tunneling is performed by using a region (locus edge) in the vicinity of the boundary as a tunnel region, there is a problem in that the writing time varies between memory cells due to variations (especially variations in film thickness) caused by the manufacturing process.

Therefore, an object of the present invention is to reduce the variation of the write time and effectively prevent the write disturb while maintaining the high integration in the NOR type bit contactless structure as described above. Another object of the present invention is to provide a nonvolatile semiconductor memory device that can be rewritten in bit units as well as collectively erased, and a manufacturing method thereof.

[0022]

In order to solve the above-mentioned problems, a nonvolatile semiconductor memory device of the present invention has a first conductivity type single crystal semiconductor layer provided on an insulating layer and the single crystal. An element isolation insulating film selectively formed on the surface portion of the semiconductor layer, and a pair formed separately from each other on the surface portion of the single crystal semiconductor layer in a region sandwiched by the pair of element isolation insulating films. A second conductivity type impurity diffusion layer, a charge storage layer formed on the single crystal semiconductor layer between the pair of impurity diffusion layers, and a control gate formed on the charge storage layer. It has a memory cell provided.

In the present invention, preferably, the charge storage layer is a floating gate formed of a conductive film formed on the single crystal semiconductor layer between the pair of impurity diffusion layers via a first gate insulating film. And a second on top of this floating gate
The control gate is formed through the gate insulating film.

More preferably, in the present invention, at least one of the element isolation insulating film and the impurity diffusion layer is formed to a depth reaching the insulating layer.

More preferably, in the present invention, the impurity diffusion layer is formed in contact with the side surface and the lower surface of the element isolation insulating film, and is adjacent to each other with the element isolation insulating film interposed therebetween.
The impurity diffusion layers of the two memory cells are formed continuously with each other.

In a preferred aspect of the present invention, the memory cells are arranged in a matrix to form a cell array, and the control gates are continuously formed in a row direction of the cell array to form a word line. The element isolation insulating film and the impurity diffusion layer are continuously formed in the column direction of the cell array, and the substrate portion made of the single crystal semiconductor layer between the pair of impurity diffusion layers forming each memory cell is The memory cells are continuously formed in a predetermined number of memory cells arranged in the column direction of the cell array.

In this case, preferably, selection transistors are formed at both ends in the column direction of each of the predetermined number of memory cells arranged in the column direction of the cell array.

In this case, it is more preferable to have a first bit line formed in the column direction of the cell array and a second bit line formed of the impurity diffusion layer continuous in the column direction of the cell array. The first bit line is electrically connected to the continuous substrate portion in each of the predetermined number of memory cells arranged in the column direction of the cell array via the selection transistor.

According to the method of manufacturing a non-volatile semiconductor memory device of the present invention, an insulating layer is formed at a predetermined depth position on a semiconductor substrate of the second conductivity type, and a portion of the semiconductor substrate above the insulating layer is formed into a second portion. A step of forming a conductive type semiconductor layer, a step of further introducing an impurity of a second conductivity type into a surface portion of the semiconductor layer to be an element isolation region, and a step of selectively selecting the surface portion of the semiconductor layer to be an element isolation region. To form an element isolation insulating film and form second conductivity type high-concentration impurity diffusion layers on both sides and the lower side of the element isolation insulating film. After introducing a first conductivity type impurity into the semiconductor layer using the element isolation insulating film as a mask, a heat treatment is performed to form a first conductivity type substrate portion in the semiconductor layer, and a second conductivity type substrate is formed. Ensure high-concentration impurity diffusion layer And forming a first insulating film on the substrate portion and a pair of the second-conductivity-type high-concentration impurity diffusion layers formed on both sides of the substrate portion. A step, a step of forming a floating gate on the first insulating film, a step of forming a second insulating film on the floating gate, and a control gate on the second insulating film And a step of performing.

In this case, preferably, the floating gate and the control gate are each formed of a polycrystalline silicon film.

In a method of manufacturing a nonvolatile semiconductor memory device according to another aspect of the present invention, an insulating layer is formed at a predetermined depth position of a semiconductor substrate of the second conductivity type, and the semiconductor substrate above the insulating layer is formed. A step of forming the portion as a second conductivity type semiconductor layer,
A step of further introducing a second conductivity type impurity into a surface portion of the semiconductor layer to be an element isolation region, and selectively oxidizing the surface portion of the semiconductor layer to be an element isolation region to form an element isolation insulating film. Forming the second conductivity type high-concentration impurity diffusion layer on both sides of the element isolation insulating film and on the lower side of the semiconductor layer; Forming an ion implantation mask on the semiconductor layer, and introducing an impurity of the first conductivity type into the semiconductor layer using the ion implantation mask and the element isolation insulating film as a mask, and then performing a heat treatment to form the semiconductor Forming a first conductivity type substrate portion in the layer and forming the second conductivity type high-concentration impurity diffusion layer to a depth that reliably reaches the insulating layer; and removing the ion implantation mask. Then, the substrate portion, a pair of the second-conductivity-type high-concentration impurity diffusion layers formed on both sides of the substrate portion, and the semiconductor layer in a portion where the first-conductivity-type impurities are not introduced 1 step of forming an insulating film, and forming a first polycrystalline silicon film on the entire surface and patterning the same to form a portion on the substrate portion and the pair of second conductivity type high-concentration impurity diffusion layers. A floating gate is formed on the first insulating film, and a gate of the selection transistor is formed on the first insulating film on a portion where the impurities of the first conductivity type are not introduced. Forming a half part, forming a second insulating film on the floating gate, forming a second polycrystalline silicon film on the entire surface, and patterning the second polycrystalline silicon film to form the second insulating film. A control gate on top of the Forming an upper half of the gate of the selection transistor on the lower half of the gate of the transistor for use, and the substrate using the element isolation insulating film, the control gate, and the gate of the selection transistor as a mask A step of further introducing a first conductivity type impurity into the portion to form a first conductivity type high-concentration impurity diffusion layer.

A nonvolatile semiconductor memory device according to another aspect of the present invention includes a cell array in which memory cells having a composite gate structure of a floating gate and a control gate are arranged in a matrix, and the cell array is arranged in a row direction. A plurality of word lines electrically connected to the control gates of the arranged memory cells to form the row lines of the cell array, and electrically connected to a substrate portion of the memory cells arranged in the column direction of the cell array; A plurality of first bit lines that function as select lines of the memory cell during a write operation and an erase operation,
A plurality of second bit lines electrically connected to the source or drain of each memory cell arranged in the column direction of the cell array and functioning as a select line of the memory cell during a read operation.

In the present invention, the word line direction is defined as the "row" direction and the bit line direction is defined as the "column" direction for the sake of convenience, but the terms "row" and "column" in the matrix are used. Does not relate to the essence of the present invention. For example, in the case of a device in which the word line is connected to the column decoder and the bit line is connected to the row decoder, the "row" and "column" The technical idea of the present invention should be construed by replacing the terms "" with each other.

[0034]

In the memory cell of the nonvolatile semiconductor memory device of the present invention, the FN tunneling is performed between the first conductivity type single crystal semiconductor layer provided on the insulating layer and the charge storage layer formed thereon. Electrons can be transferred, and the entire surface of the channel region under the charge storage layer can be used as a tunnel region. Therefore, for example, variations in characteristics between memory cells due to manufacturing process factors are reduced.

Further, in the nonvolatile semiconductor memory device of the present invention, the first conductivity type single crystal semiconductor layer forming the substrate portion of each memory cell is electrically separated into each memory cell in the direction of the word line. In addition, in the direction of the bit line, a predetermined number of memory cells are commonly configured, and the substrate portion thereof is connected to the first bit line that functions as a select line of the memory cell during the write operation and the erase operation to connect the first bit. The second conductivity type impurity diffusion layer continuously formed in the direction of the bit line is used as a second bit line which functions as a select line of a memory cell only during a read operation. As a result, it is not necessary to apply a high voltage that causes write disturb to the read-only second bit line, so that the second conductivity type impurity diffusion layers are adjacent to each other in the word line direction. Also be shared with the Moriseru does not cause a problem. Therefore, there is no need for a relatively complicated element isolation structure for isolating the second conductivity type impurity diffusion layers from adjacent memory cells in the word line direction as in the conventional case.

Further, the substrate portion forming the sub-bit line of the first bit line is electrically separated into each memory cell in the direction of the word line, and by using this in the gate negative voltage system which will be described later, the The memory cells can be independently selected, and thus rewriting can be performed in bit units.
As a result, it is not necessary to erase the data in the memory cells that do not need to be rewritten, the number of times of rewriting of the memory cells is effectively reduced, and the reliability is improved.

[0037]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment in which the present invention is applied to an N-channel floating gate type EEPROM is shown in FIG.
~ It demonstrates with reference to FIG.

FIG. 1 is a schematic plan view showing a part of the cell array of the EEPROM of this embodiment, FIG. 2 is a sectional view taken along line II-II of FIG. 1, and FIG. 3 is taken along line III-III of FIG. FIG.

As shown in FIG. 2 and FIG.
The cell array of EPROM is SOI (Silicon On Insulate)
r) is formed on the substrate of the structure. That is, the substrate is composed of the buried oxide film layer 18 having a thickness of about 500 nm, and the lower N-type silicon substrate portion 17 and the upper P well 16 (having a depth of about 30).
0 nm).

As shown in FIG. 3, the P well 16 includes an element isolation insulating film 1 and an N ⁺ diffusion layer 3 formed under the element isolation insulating film 1 to a depth reaching the buried oxide film layer 18. Are separated from each other in the longitudinal direction of the word lines 4. On the other hand, in the longitudinal direction of the bit line, as shown in FIG. 2, N formed at both ends of a column of a predetermined number of memory cells.
The P-type well 16 is separated from the other substrate by the type silicon layer 19. Each P well 16 is commonly configured by a predetermined number of memory cells arranged in the longitudinal direction of the bit line, and in this direction, each memory cell is separated by the parasitic channel stopper P ⁺ diffusion layer 12. .

As shown in FIGS. 2 and 3, each P well 1
6, a first gate insulating film 13 having a thickness of about 10 nm, which is a tunnel oxide film, and an N-type doped thickness of about 150 are formed.
Floating gate 11 made of a polycrystalline silicon layer of 10 nm, silicon oxide film / silicon nitride film / silicon oxide film (ONO
Film: an oxide film equivalent film thickness of about 20 nm), a second gate insulating film 14, and a word line 4 composed of an N-type doped polycrystalline silicon layer having a film thickness of about 300 nm and constituting a control gate are sequentially laminated. There is.

Further, as shown in FIG. 2, each P well 16
Select transistors 20 having a gate electrode are formed on the N-type silicon layer 19 at both ends of. Then, the portion of the P well 16 sandwiched by the pair of selection transistors 20 is set as one block. As shown in the figure, a P-type silicon layer 16 'is provided between each block, and a P ⁺⁺ diffusion layer 7 is formed in a P ⁺ diffusion layer 12' formed on the surface of the P-type silicon layer 16 '. Then, the contact hole 9 is formed in the interlayer insulating film 15 on the P ⁺⁺ diffusion layer 7. Then, the contact hole 9 is filled with a tungsten plug 10, and the tungsten plug 10 is
It is connected to the main bit line 6 made of aluminum wiring formed on the interlayer insulating film 15.

In this embodiment, the P well 16 is electrically connected to the main bit line 6 through the selection transistor 20, so that the P well 16 is connected to the sub bit line 5 which will be described later.
(See FIGS. 1 and 4). Further, the main bit line 6 and the sub bit line 5 are referred to as a first bit line.

As shown in FIG. 3, the N ⁺ diffusion layer 3 forming the source / drain of each memory cell is shared by two memory cells adjacent to each other with the element isolation insulating film 1 interposed therebetween. The N ⁺ diffusion layer 3 is formed along with the element isolation insulating film 1 in the longitudinal direction of the main bit line 6, that is, as shown in FIG.
In, the sheet is continuously formed in the direction perpendicular to the paper surface.
In this embodiment, this N ⁺ diffusion layer 3 is used as the second bit line.

Next, a method of manufacturing the EEPROM of this embodiment will be described with reference to FIGS.

First, as shown in FIG. 6, about 500 is formed by implanting oxygen ions into a predetermined depth position of an N-type silicon substrate.
A buried oxide film layer 18 having a thickness of nm is formed, and an N-type single crystal silicon layer 19 having a thickness of about 300 nm is relatively formed thereon. Then, a pad oxide film 34 having a thickness of 40 to 50 nm is formed on the N-type single crystal silicon layer 19 by a thermal oxidation method, and a silicon nitride film 23 is further formed thereon by a chemical vapor deposition (CVD) method. Deposit to a thickness of 150 nm. Then, by photolithography and reactive ion etching (RIE), the silicon nitride film 23 is left only on the portion to be the active region, and the photoresist 22 and the silicon nitride film 23 left on the silicon nitride film 23 are used as a mask. Arsenic ion implantation 30 is performed under the conditions of 70 keV and 5 × 10 ¹⁵ cm ⁻² .

Next, as shown in FIG.
After removing 2, the element isolation insulating film 1 is formed by the selective oxidation (LOCOS) method, and the N ⁺ diffusion layers 3 are formed on both sides and the lower side of the element isolation insulating film 1 by heat treatment at that time.
To form. The element isolation insulating film 1 is 1000
The final oxide film thickness is set to about 200 nm by pyrogenic oxidation at 30 ° C. for 30 minutes.

Next, as shown in FIG. 8, 100 kev,
BF ₂ ⁺ ion implantation 31 is performed under the condition of 7 × 10 ¹³ cm ⁻² . Then, heat treatment is performed at 1200 ° C. for 60 minutes in a nitrogen atmosphere to fill the bottom of the N ⁺ diffusion layer 3 with the buried oxide film layer 1.
8 in a substantially complete contact with the P well 16
To form. A longitudinal sectional view of the bit line in this step is shown in FIG. 9, and only the portion to be the channel region of the select transistor 20 (see FIG. 2) is masked with the photoresist 26, and the above ion implantation 31 is performed.

Next, as shown in FIG. 10, after removing the photoresist 26, oxidation is performed at 800 to 900 ° C. for 10 minutes in a steam atmosphere or an HCl atmosphere to form a first gate having a thickness of about 10 nm on the active region. Insulating film (tunnel oxide film)
13 is formed. Then, a phosphorus-doped polycrystalline silicon film 24 is deposited to a thickness of about 150 nm by the CVD method, and this polycrystalline silicon film 24 is used as the element isolation insulating film 1.
After they are separated from each other (see FIG. 3), the second gate insulating film 14 having an oxide film thickness of about 20 nm formed of an ONO film is formed on the entire surface. The lower oxide film of this ONO film is formed to have a thickness of about 10 nm by oxidizing the polycrystalline silicon film 24 under conditions of 1000 ° C. and 6 minutes in a dry oxygen atmosphere. The upper oxide film is formed to a thickness of about 10 nm by the CVD method, and the upper layer oxide film is formed to a thickness of about 3 nm by oxidizing the silicon nitride film in a steam atmosphere at 900 ° C. for 3 hours. After that, the photoresist 27 is patterned by photolithography, and R using the photoresist 27 as a mask
The second gate insulating film 14 in the region where the gate electrode of the select transistor 20 is formed is removed by IE.

Next, as shown in FIG. 11, after removing the photoresist 27, a phosphorus-doped polycrystalline silicon film 25 is deposited by the CVD method to a thickness of about 150 nm,
The photoresist 28 is patterned by photolithography to cover the control gate of each memory cell and the portion to be the gate electrode of the select transistor 20.

Next, as shown in FIG. 12, the polycrystalline silicon film 24, the second gate insulating film 14, and the polycrystalline silicon film 25 are sequentially etched by RIE by self-alignment,
The photoresist 28 is removed, and the control gate and floating gate of each memory cell and the gate electrode of the select transistor 20 are formed. After that, with the control gate of the memory cell, the gate electrode of the selection transistor 20 and the isolation insulating film 1 as a mask, 70 kev, 5 × 10 ¹³ cm
BF ₂ ⁺ ion implantation 32 is performed under the condition of ^{-2 to form} the parasitic channel stopper P ⁺ diffusion layer 12 and P ⁺ diffusion layer 12 '.
To form.

Next, as shown in FIG. 13, the photoresist 29 is patterned by photolithography to form an opening on the P ⁺ diffusion layer 12 'in the portion of the P type silicon layer 16', and through this opening, 70 kev, 5 × 10 ¹⁵
BF ₂ ⁺ ion implantation 33 is performed under the condition of cm ⁻² , the photoresist 29 is removed, and then annealing treatment is performed at 900 ° C. in a nitrogen atmosphere to form the P ⁺⁺ diffusion layer 7.

Next, as shown in FIG. 14, a BPSG film doped with boron and phosphorus by atmospheric pressure CVD is deposited to about 1 μm.
Then, the inter-layer insulating film 15 is formed by performing a reflow process. Then, the contact hole 9 is opened in the interlayer insulating film 15 and the first gate insulating film 13 by photolithography and RIE. Then, selective tungsten CVD is performed using WF ₆ gas to fill the contact hole 9 with tungsten to form a buried tungsten plug 10.

Thereafter, as shown in FIG. 2, the interlayer insulating film 1
A main bit line 6 is formed on the wiring 5 by aluminum wiring, and the main bit line 6 and the buried tungsten plug 10 are connected to each other.

Next, each operation of the EEPROM of this embodiment will be described with reference to FIGS. In these figures, BL ₁ and BL ₂ are main bit lines 6, LD ₁ and LD ₂ of the first bit line connected to the Y decoder and program voltage supply line (not shown), and P well 16 is formed. The sub bit line 5 of the first bit line, RD _{0 to} RD ₂ is N
^{+ A} second bit line formed of the diffusion layer 3, ST is a gate electrode of the selection transistor 20, W _{0 to} W ₃₁ are control lines of memory cells, and word lines connected to an X decoder (not shown), respectively. Shows.

First, FIG. 4 shows an example of bias during erase operation.
It shows in (a). When the memory cell M ₁₂ is selected, the second bit lines RD _{0 to} RD ₂ are opened, and the word line W ₁ connected to the control gate of the memory cell M ₁₂ has 12 lines.
0V is applied to V and the other word lines W ₀ and W _{2 to} W ₃₁ respectively. Further, by applying 5V to the gate electrode ST to turn on the selection transistor 20, the main bit line 6 of the first bit line and the sub bit line 5 including the P well 16 are brought into conduction, and the selected main bit line BL is selected. -10V is applied to ₂ and 0V is applied to the non-selected main bit line BL ₁ . As a result, the sub-bit line LD of the first bit line formed of the P well 16 forming the substrate portion of the selected memory cell M ₁₂ is formed.
-10V is applied to ₂ and 0V is applied to the non-selected sub-bit line LD ₁ . That is, during the erase operation, the word line W _n and the first bit lines BL _n and LD _n become the selection lines.

During this erase operation, a high electric field is applied between the control gate (word line 4) of the selected memory cell M ₁₂ and the substrate portion (P well 16). At this time, a tunnel oxide film is formed. The electric field strength applied to the (first gate insulating film 13) (see FIG. 3) is determined by the selected cell M ₁₂ and the non-selected cell M ₁₂ .
Consider ₁₁ and M ₂₂ .

Now, the potential of the floating gate is V _fg , the potential of the control gate is V _cg , the substrate potential is V _sub , the capacitance between the floating gate and the control gate is C ₂ , and the capacitance of the tunnel oxide film is C _1.
Then, the equivalent circuit of the gate portion of the memory cell is as shown in FIG. Assuming that the capacitance ratio C ₂ / (C ₁ + C ₂ ) is 0.5 and the charge in the floating gate is Q (positive),
Using the law of conservation of charge, the potential V _{fg of the} floating gate is expressed as V _fg = 0.5 V _cg +0.5 V _sub + Q / (C ₁ + C ₂ ) ... (1).

Further, assuming that the electric field strength applied to the tunnel oxide film is E _t and the film thickness of the tunnel oxide film is T _t (= 10 nm), the electric field strength E _t is E _t = (V _fg −V _sub ) / T _t = {0.5 (V _cg −V _sub ) + Q / (C ₁ + C ₂ )} / T _t (2)

Therefore, assuming that the threshold voltage V _t of the memory cell in the written state (defined as “1”) is 1 V, V _t = Q / C ₂ , and this Q is given by the equation (2). It is substituted _{into, E t = {0.5 (V} cg -V sub) + C 2 · V t / (C 1 + C 2)} / T t = {0.5 (V cg -V sub) +0.5 × 1} / T _t (3)

Therefore, from this equation (3), the selected cell M ₁₂ ,
The electric field strengths applied to the tunnel oxide films of the non-selected cells M ₁₁ and M ₂₂ are 11.5 MV / cm and 6.5 MV / cm, respectively.
Calculated as 5.5 MV / cm, FN only in selected cell M _12.
It can be seen that tunneling occurs and electrons are injected from the substrate portion to the floating gate to perform the erase operation.

Next, an example of the bias during the read operation is shown in FIG.
It shows in (b). In the figure, when the memory cell M ₁₂ is selected for reading, ₀ V is applied to the second bit line RD ₀ and 0 is applied to the second bit line RD ₁ which is the source of the memory cell M _12.
V, the second bit line RD serving as the drain of the memory cell M _12.
1V is applied to ₂ respectively, 5V is applied to the word line W ₁ connected to the control gate of the memory cell M ₁₂ , and other word lines W
0V is applied to each of ₀ and W _{2 to} W _31, and 0V is applied to the gate electrode ST to turn off the selection transistor 20.
The main bit lines BL ₁ and BL ₂ of the bit lines are grounded. That is, during the read operation, the word line W _n and the second bit line RD _n become the selection lines.

In this state, if the memory cell M ₁₂ is in the "1" state (write state), an on-current flows through this memory cell M ₁₂ and the potential of the second bit line RD ₂ changes, and data "1" is detected by the sense amplifier connected to the other end of the second bit line RD _2. On the other hand, if the memory cell M ₁₂ is in the state of “0” (erased state), no current flows in the memory cell M ₁₂ and the potential of the second bit line RD ₂ does not change, so the second bit line RD Data "0" is detected by the sense amplifier connected to the other end of ₂ .

Next, FIG. 4 shows an example of bias in the write operation.
It shows in (c). In the figure, when writing by selecting the memory cell M _12, the source / second bit line RD ₀ ~ Rd ₂ is the drain of the memory cell is in an open state, connected to the control gates of the memory cells M ₁₂ Existing word line W ₁
-9V, and other word lines W ₀ and W _{2 to} W ₃₁ 0V
By applying 5 V to the gate electrode ST to turn on the selection transistor 20, the main bit line 6 of the first bit line and the sub-bit line 5 formed of the P well 16 are electrically connected to each other and selected. applying a 18V to the main bit line BL _2, 0V is applied to main the bit lines BL ₁ unselected. As a result, the sub-bit line LD of the first bit line formed of the P well 16 forming the substrate portion of the selected memory cell M ₁₂ is formed.
18V is applied to ₂ and 0V is applied to the non-selected sub-bit line LD ₁ . That is, during the erase operation, the word line W
_n and the first bit lines BL _n and LD _n serve as select lines.

During this write operation, a high electric field is applied between the control gate (word line 4) of the selected memory cell M ₁₂ and the substrate portion (P well 16). At this time, the tunnel oxide film is formed. (First gate insulating film 13) (Third
The electric field strength applied to the
Using the formula (3), the selected cell M ₁₂ , the non-selected cells M ₁₁ and M
_When calculated for _22, each is 10 MV / cm, 1 MV / cm
cm, 5.5 MV / cm, and F only in the selected cell M _12.
N tunneling occurs, electrons are extracted from the floating gate to the substrate portion, and a write operation is performed. In the calculation here, the threshold voltage V _t of the memory cell in the erased state is assumed to be 7V.

As can be seen from the above description, in the EEPROM of this embodiment, the N ⁺ diffusion layer 3 (second bit) which constitutes the source / drain of each memory cell and is shared with the source / drain of the adjacent memory cell is used. Since it is not necessary to apply a high voltage to the line RD _n ) (see FIG. 3) during all erase, read and write operations, the occurrence of write disturb in unselected cells is prevented.

In addition, erasing and writing of memory cells
In both cases, the FN between the substrate portion composed of the P well 16 shown in FIG. 3 and the floating gate 11 formed thereon is used.
Since the electron transfer is performed by tunneling, and the entire surface of the channel region under the floating gate 11 is used as a tunnel region, there is almost no variation in characteristics between memory cells due to the conventional manufacturing process. In addition, the durability can be expected to be improved by averaging the wear of the tunnel oxide film 13 as compared with the conventional case where only a specific portion of the tunnel oxide film 13 is used as a tunnel region. The sexual life is improved.

Although the present invention has been described with reference to one embodiment, the above embodiment is not intended to limit the present invention, and various effective modifications can be made to the above embodiment based on the technical idea of the present invention. It is possible. For example, although the rewriting operation in bit units has been described in the above-mentioned embodiment, it is possible to carry out a batch erasing or writing operation as in the conventional case.
In that case, in order to further suppress the variation in the threshold voltage distribution after erasing or writing, it is possible to add an operation algorithm for preliminarily aligning the threshold voltages of all the memory cells with one of the states.

Further, in the above-mentioned embodiment, the substrate by the SIMOX (Separation by IMplanted OXygen) method is used as the SOI substrate, but the SOI substrate by the manufacturing method such as epi-growth or bonding can also be used.

Further, the present invention is not limited to the floating gate type non-volatile semiconductor memory device, and for example, MIO (Metal Insulator) using a silicon nitride film formed on the channel region via a silicon oxide film as a charge storage layer. Oxide Sili
It is also applicable to a trap type non-volatile semiconductor memory device having a con) structure.

[0071]

According to the nonvolatile semiconductor memory device of the present invention, both the erasing operation and the writing operation correspond to the low power consumption between the substrate portion and the charge storage layer formed thereon. Since electron transfer is performed by FN tunneling, and the entire surface of the channel region is used as a tunnel region, variations in characteristics between memory cells due to manufacturing process factors are reduced, and wear of the tunnel insulating film is reduced. By averaging and improving durability,
The number of rewritable times is increased and the reliability life of the memory cell is improved as compared with the conventional nonvolatile semiconductor memory device.

Further, a substrate portion of a predetermined number of memory cells arranged in the direction of the bit line is continuously formed and used as the first bit line, and the impurity diffusion layer forming the source / drain of the memory cell is formed into the second bit line. As the bit line, the first bit line is used as the select line of the memory cell during the erase and write operations, and the second bit line is used as the select line only during the read operation, so that the impurity diffusion layer forming the source / drain of the memory cell is formed. Eliminates the need to apply a high voltage that causes write disturb. Therefore, a complicated isolation structure for isolating the impurity diffusion layers in the memory cells adjacent to each other in the word line direction is not required.

[Brief description of drawings]

FIG. 1 is a schematic plan view of a main part of an EEPROM cell array according to an embodiment of the present invention.

FIG. 2 is a sectional view taken along line II-II of FIG.

FIG. 3 is a sectional view taken along line III-III in FIG.

FIG. 4 is a conceptual diagram showing a bias example during each operation of the EEPROM of FIG.

5 is an equivalent circuit diagram of a memory cell of the EEPROM of FIG.

FIG. 6 is a cross-sectional view showing the method of manufacturing the EEPROM according to the embodiment of the present invention.

FIG. 7 is a cross-sectional view showing the method of manufacturing the EEPROM according to the embodiment of the present invention.

FIG. 8 is a cross-sectional view showing the method of manufacturing the EEPROM according to the embodiment of the present invention.

FIG. 9 is a cross-sectional view showing the method of manufacturing the EEPROM according to the embodiment of the present invention seen from another direction.

FIG. 10 is a sectional view showing the method for manufacturing the EEPROM according to the embodiment of the present invention, as seen from another direction.

FIG. 11 is a cross-sectional view showing the method of manufacturing the EEPROM according to the embodiment of the present invention, as seen from another direction.

FIG. 12 is a cross-sectional view showing the method of manufacturing the EEPROM according to the embodiment of the present invention as seen from another direction.

FIG. 13 is a cross-sectional view showing the method of manufacturing the EEPROM according to the embodiment of the present invention as seen from another direction.

FIG. 14 is a cross-sectional view showing the method of manufacturing the EEPROM according to the embodiment of the present invention seen from another direction.

FIG. 15 is a circuit diagram of a conventional EEPROM cell array.

FIG. 16: XV of FIG. 15 of a conventional EEPROM cell array
FIG. 6 is a sectional view taken along a line I-XVI.

FIG. 17: XV of FIG. 15 of a conventional EEPROM cell array
FIG. 7 is a cross-sectional view taken along the line II-XVII.

FIG. 18 is a conceptual diagram showing bias conditions during each operation of the conventional EEPROM.

[Explanation of symbols]

1 Insulation film for element isolation 3 N ⁺ Diffusion layer (source / drain) (second bit line) 4 Word line (control gate) 5 Sub bit line (first bit line) 6 Main bit line (first bit line) 9 Contact hole 11 Floating gate 12 P ⁺ diffusion layer for parasitic channel stopper 13 First gate insulating film (tunnel oxide film) 14 Second gate insulating film 15 Interlayer insulating film 16 P well 16 'P-type single crystal silicon layer 17 N-type silicon Substrate part 18 Buried oxide film layer 19 N-type single crystal silicon layer 20 Select transistor

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display area H01L 29/792

Claims (11)

[Claims] 1. A first-conductivity-type single crystal semiconductor layer provided on an insulating layer, an element isolation insulating film selectively formed on a surface portion of the single crystal semiconductor layer, and a pair of the elements. A pair of second conductivity type impurity diffusion layers formed separately from each other on a surface portion of the single crystal semiconductor layer in a region sandwiched by isolation insulating films, and the single crystal between the pair of impurity diffusion layers. A nonvolatile semiconductor memory device comprising a memory cell including a charge storage layer formed on a semiconductor layer and a control gate formed on the charge storage layer. 2. The charge storage layer is a floating gate formed of a conductive film formed on the single crystal semiconductor layer between the pair of impurity diffusion layers with a first gate insulating film interposed therebetween. The nonvolatile semiconductor memory device according to claim 1, wherein the control gate is formed on the floating gate via a second gate insulating film. 3. The nonvolatile semiconductor memory according to claim 1, wherein at least one of the element isolation insulating film and the impurity diffusion layer is formed to a depth reaching the insulating layer. apparatus. 4. The impurity diffusion layer is formed in contact with a side surface and a lower surface of the element isolation insulating film, and the impurity diffusion layers of two memory cells adjacent to each other with the element isolation insulating film interposed therebetween are continuous with each other. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is formed by: 5. The memory cells are arranged in a matrix to form a cell array, the control gate is continuously formed in a row direction of the cell array to form a word line, the insulating film for element isolation and the Impurity diffusion layers are continuously formed in the column direction of the cell array, and the substrate portion made of the single crystal semiconductor layer between the pair of impurity diffusion layers forming each memory cell is arranged in the column direction of the cell array. 5. The nonvolatile semiconductor memory device according to claim 3, wherein each of the predetermined number of memory cells is continuously formed. 6. The non-volatile semiconductor according to claim 5, wherein selection transistors are formed at both ends of each of the predetermined number of memory cells arranged in the column direction of the cell array in the column direction. Storage device. 7. A first bit line formed in the column direction of the cell array, and a second bit line formed of the impurity diffusion layer continuous in the column direction of the cell array. 7. The non-volatile memory according to claim 6, wherein is electrically connected to the continuous substrate portion in each of the predetermined number of memory cells arranged in the column direction of the cell array via the selection transistor. Semiconductor memory device. 8. A step of forming an insulating layer at a predetermined depth position of a second conductivity type semiconductor substrate, and making a portion of the semiconductor substrate above the insulation layer a second conductivity type semiconductor layer, A step of further introducing a second conductivity type impurity into a surface portion of the semiconductor layer to be an isolation region, and selectively oxidizing the surface portion of the semiconductor layer to be an element isolation region to form an element isolation insulating film And forming a second-conductivity-type high-concentration impurity diffusion layer on both sides and underside of the element isolation insulating film, the semiconductor layer using at least the element isolation insulating film as a mask. After first-conductivity-type impurities are introduced into the semiconductor layer, heat treatment is performed to form a first-conductivity-type substrate portion in the semiconductor layer, and the second-conductivity-type high-concentration impurity diffusion layer is reliably formed in the insulating layer. Process to reach depth And a step of forming a first insulating film on the substrate portion and a pair of the second-conductivity-type high-concentration impurity diffusion layers formed on both sides of the substrate portion, and on the first insulating film. And a step of forming a floating gate on the floating gate, a step of forming a second insulating film on the floating gate, and a step of forming a control gate on the second insulating film. Of manufacturing a non-volatile semiconductor memory device. 9. The method for manufacturing a nonvolatile semiconductor memory device according to claim 8, wherein the floating gate and the control gate are each formed of a polycrystalline silicon film. 10. A step of forming an insulating layer at a predetermined depth position of a second conductivity type semiconductor substrate, and making a portion of the semiconductor substrate above the insulation layer the second conductivity type semiconductor layer. A step of further introducing a second conductivity type impurity into a surface portion of the semiconductor layer to be an isolation region, and selectively oxidizing the surface portion of the semiconductor layer to be an element isolation region to form an element isolation insulating film And forming a second-conductivity-type high-concentration impurity diffusion layer on both sides and the lower side of the element isolation insulating film, and the semiconductor of the portion where the channel of the selection transistor is to be formed. Forming an ion implantation mask on the layer, and using the ion implantation mask and the isolation insulating film as a mask to introduce impurities of the first conductivity type into the semiconductor layer, and then subjecting the semiconductor layer to a heat treatment. In first Forming a conductive type substrate portion and forming the second conductive type high-concentration impurity diffusion layer to a depth that reliably reaches the insulating layer; and after removing the ion implantation mask, the substrate portion and this A first insulating film is formed on the pair of second-conductivity-type high-concentration impurity diffusion layers formed on both sides of the substrate and the semiconductor layer in a portion where the first-conductivity-type impurities are not introduced. Steps: forming a first polycrystalline silicon film on the entire surface, patterning the first polycrystalline silicon film, and patterning the first polycrystalline silicon film to form a portion of the first insulating film on the substrate portion and the pair of second-conductivity-type high-concentration impurity diffusion layers. Forming a floating gate on the first insulating film and forming a lower half of the gate of the selecting transistor on the first insulating film on a portion where the first conductivity type impurity is not introduced; , Above the floating gate Forming a second insulating film, forming a second polycrystalline silicon film on the entire surface, and patterning the second polycrystalline silicon film to form a control gate on the second insulating film; Forming an upper half of the gate of the selection transistor on the lower half of the gate, and using the element isolation insulating film, the control gate, and the gate of the selection transistor as a mask to form a second pattern on the substrate section. 1
And a step of further introducing a conductive type impurity to form a high-concentration impurity diffusion layer of the first conductive type. 11. A memory cell having a composite gate structure of a floating gate and a control gate is arranged in a matrix, and the memory cell is electrically connected to the control gates of the memory cells arranged in the row direction of the cell array. And a plurality of word lines forming row lines of the cell array, and electrically connected to the substrate portion of each memory cell arranged in the column direction of the cell array, and functioning as a memory cell selection line during a write operation and an erase operation. A plurality of first bit lines and a plurality of second bit lines electrically connected to the source or drain of each memory cell arranged in the column direction of the cell array and functioning as a select line of the memory cell during a read operation. A non-volatile semiconductor memory device having.