JPH11224940A - Nonvolatile semiconductor memory device and writing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To effectively prevent erroneous writing into non-selected cells which accompanies reduction in programming voltage. SOLUTION: A nonvolatile semiconductor memory device has memory cells M11a to M1na, which perform basic information storing operations by injecting or drawing charges into or from charge storage means by applying a voltage to first control electrodes (e.g. word liens WL11 to WL1n) deposited on channel- forming regions of a semiconductor via an insulating film including the charge storage means, and cells (e.g. other memory cells or selected cells) for transmitting a predetermined potential to the channel-forming regions of the memory cells in injecting or drawing the charges. Second control electrodes 22, which are capacitively coupled to semiconductor regions between the memory cells and the cells for transmitting the predetermined potential and control the potential and the formation of inter-cell channels or depletion layer in the semiconductor regions, are formed in impurity regions between cells via an insulating film 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for electrically storing data by providing charge storage means in an insulating film between a channel forming region and a control electrode, and injecting or extracting charges into the charge storage means. And a writing method thereof. Specifically,
According to the present invention, even when the writing time of a storage element is long, it is possible to effectively prevent erroneous writing by extending the time during which the writing can be inhibited for another storage element to which the storage element and the control electrode are connected and writing is to be inhibited. The present invention relates to a nonvolatile semiconductor memory device having a configuration and a writing method thereof. Furthermore,
According to the present invention, a depletion layer is induced by a second control electrode on a semiconductor surface between storage elements and between a storage element and a selection element, and the potential of the depletion layer is controlled by the potential of the second control electrode. The present invention relates to a nonvolatile semiconductor memory device capable of more reliably performing write inhibition and a write method thereof.

[0002]

2. Description of the Related Art Conventionally, a nonvolatile semiconductor memory device has an insulating film interposed between a control channel and a channel forming region of a semiconductor (a surface region of a semiconductor substrate or a well where a channel of the device is formed, for example). A charge storage means is provided therein, and the threshold value (generally, a gate threshold voltage) of the memory element is changed in accordance with the presence or absence of charge existing in the charge storage means or the amount of charge. It corresponds to the logic state of the stored data signal. Here, for example, a single conductive layer such as an FG (floating gate) or a small-diameter conductive material such as a nanocrystal, which is disposed in a plurality of planes and is insulated from each other and insulated from each other, may be used as the charge storage means for storing charges. And a charge trap formed in the nitride film or at the interface between the nitride film and the oxide film and discretely formed spatially (in the plane direction and the film thickness direction). FG type, nano-crystal type, MON type
Various types of non-volatile semiconductor memory devices such as the OS type and the MNOS type have been prototyped and provided.

In a nonvolatile semiconductor memory device (nonvolatile memory device) in which a memory cell array is configured by arranging a large number of such memory elements, many types of memory cell systems have been proposed. There is a NAND type as a cell system which is small and capable of increasing the capacity. The NAND type nonvolatile memory device includes a plurality of memory transistors connected in series to form a memory block called a NAND string, and two NAND strings share one bit contact and one source line to thereby form one memory cell. The effective cell area per bit can be reduced.

FIG. 13 is a circuit diagram showing a basic configuration of a memory cell array of a conventional NAND type nonvolatile memory device.

In FIG. 13, reference numeral 100 denotes a memory cell array, M11a to M1na, M11b to M1nb, M21.
a and M21b are memory transistors, S11a, S1
2a, S11b, S12b, S21a, S22a, S2
1b and S22b are selection transistors, BLa and BLb are bit lines, WL11 to WLn1 and WL21 are word lines, SL is a source line, SG11 and SG21 are bit line selection signal lines, SG12 and SG22 are source line selection signal lines, and BC is Indicates a bit contact. A repeating unit called a string includes two selection transistors (selection gates) connected to a bit line or a source line, and n (n is, for example, 8, 16, 32, or the like) between the two selection transistors. And a NAND string in which memory transistors are connected in series. Select transistors S11a, S11b, S21a and S21b connected to bit lines
Is controlled by the bit line selection signal line SG11 or SG21, and is connected to the selection transistor S12 connected to the source line.
a, S12b, S22a and S22b are controlled by the source line selection signal line SG12 or SG22. Also,
Memory transistors M11a and M11b, M12a and M
12b, M13a and M13b, M1na and M1nb
Word lines WL11, WL12, WL13, WL
n1. Similarly, the memory transistor M
21a and M21b are controlled by word line WL21.

FIG. 14 is a cross-sectional view of a conventional nonvolatile memory device in the column direction centering on the NAND column located at the lower left of FIG. Here, a case where the memory transistor is an FG (Floating Gate) type is exemplified.
In FIG. 14, reference numeral 2 denotes, for example, an n-type semiconductor substrate,
Denotes a p-type well (p-well), 24 denotes an interlayer insulating layer, and 24a denotes a bit contact hole formed in the interlayer insulating layer 24. The bit contact hole 24a, together with the connection plug embedded therein,
Construct C. Each of the memory transistors M11a to M1n
a is formed by stacking a tunnel insulating film 40, a floating gate FG, an inter-gate insulating film 42, and a control gate CG on a p-well 4. The control gates CG of the respective memory transistors form word lines WL11 to WL1n, respectively.

The selection transistors SG11, SG12, S
G21 has basically the same laminated structure as that of the memory transistor, but in these select transistors, the layer that becomes the floating gate FG and the layer that becomes the control gate CG in the memory transistor are the inter-gate insulating films 42.
Is short-circuited through the connection hole provided in the. As a result, the gate electrode layers on the gate insulating film are all at the same potential, as in a normal single-layer gate, whereby the bit line selection signal lines SG11 and SG21 and the source line selection signal line SG12 are formed. ing.

The source / drain impurity regions 6c of the memory transistor and the selection transistor are formed in the surface region of the p well 4 located in the space region between the gate electrodes arranged as described above. A drain impurity region 6a common to two strings in the bit direction is formed in the surface region of the p-well 4 located in a space between the gate electrodes of the select transistors SG11 and SG21. The surface area of the p well 4 located outside the gate electrode of the other select transistor SG12 includes
A source impurity region 6b forming the source line SL common to other strings adjacent in the bit direction is formed.

FIG. 14 shows the FG type. However, even when a non-volatile memory element in which charge storage means is discretized in a plane is used, a conventional NA is used except that the gate insulating film structure is different.
The ND type is basically the same as FIG. p well 4
In the MONOS type, a tunnel insulating film, a nitride film and a top oxide film are laminated between the gate electrode (word line) and
In the MNOS type, a tunnel insulating film and a nitride film are stacked. In the nano-crystal type, small-diameter conductors are discretely embedded in an insulating film on the tunnel insulating film on the p-well 4.

Next, in the NAND type nonvolatile memory device having such a configuration, an example in which binary information is stored corresponding to a normally on state and a normally off state of a memory transistor will be described. Operation will be described. In the read operation, the potential of the word line (selected word line) to which the cell to be read (selected cell) is connected and the well are fixed to 0 V, and all the selected transistors and word lines other than the selected word line (non-selected word lines) are connected. A voltage VRG that makes all of the connected memory transistors conductive is applied to all selected signal lines and unselected word lines. The voltage V RG is such a magnitude that writing and erasing cannot be performed on the memory transistor only by the potential difference from the well, and is, for example, 5 V to 5 V.
It is about 7V. In this state, when a positive voltage is applied only to the bit line (selected bit line) to which the selected cell is connected, all the memory transistors other than the cell from which information is read are in a conductive state.
Whether the current flows or does not flow in the selected bit line is determined depending on whether it is normally on or normally off. The presence or absence of this current is detected, and the logical state “1” or “0” of the stored data
Is determined.

The erasing operation is usually performed in units of a block, and 0V and non-selected NAND are applied to all the word lines of the selected block.
A high voltage V _PP is applied to all word lines in the column and the substrate or well. As a result, electrons are extracted from the floating gate to the substrate only in the memory transistor of the selected block, and the threshold voltage of the memory transistor shifts in the negative direction. For example, the normally-on erase state (the logical state is, for example, “1”) "Corresponds to").

On the other hand, the data programming operation is usually
This operation is performed in a so-called page unit for the memory transistors connected to the selected word line. Specifically, with the selection transistor on the bit line side turned on and the selection transistor on the source line side turned off, a high voltage is applied to the selected word line.
An intermediate voltage (pass voltage) is applied to an unselected word line, which does not write to unselected cells but turns on. At this time, 0 V is applied to the selected bit line to which the memory transistor to be programmed (for example, storing “0” data) is connected.
An intermediate potential that is high enough to prevent writing due to a potential difference from the potential due to the applied high voltage is set to a non-selected bit line connected only to a memory transistor for which programming is to be inhibited (for example, holding “0” data). as a result,
Only the selected memory transistor to be programmed has electrons injected into the floating gate, and the threshold voltage of the selected memory transistor shifts in the positive direction to a higher state than the erased state, for example, a normally-off write state.

In this writing operation, the operation time is usually limited by the charging and discharging of a bit line having a high load capacity. Therefore, it is necessary to reduce the voltage for driving the bit line to reduce the load on the booster circuit. The main purpose is non-selection N
A technique of disconnecting only the AND columns from the bit lines by the selection gate is described in Japanese Patent Laid-Open Publication No. Hei 6-97455. In this technique, the applied voltage of the unselected bit line is reduced to a value obtained by subtracting the threshold from the applied voltage of the select gate.
Unselected NAND strings are separated from bit lines. As a result, thereafter, the channel potential (write blocking potential) of the non-selected NAND string is set by the automatic boosting by the pass voltage or the program voltage. Therefore, the technique described in the above-mentioned literature is now widely used as a self-boost technique. Are known.

[0014]

However, when this self-boost technique is applied to, for example, a conventional nonvolatile memory device whose basic configuration is shown in the sectional view of FIG. 14, there are several problems as described below.

In the non-volatile memory, the tunnel insulating film is further thinned as the power supply voltage is reduced and the cell is miniaturized. In particular, it is pointed out that the FG type has a thickness limit due to stress leak. The film thickness limit is 6 nm in theory, and is actually about 8 nm (see Nikkei Microdevices January and February, 1997). If low-voltage driving proceeds without scaling the tunnel film thickness, The writing speed may be slow.
The first problem is that when the writing speed is low for such a reason, the memory transistor of a non-selected cell connected to the same word line as the selected cell to which data is being written is likely to be erroneously written. According to the above-mentioned document (publication publication), there is a certain upper limit for the time during which a non-selected NAND string is effectively in a write-protected state and there is no threshold shift. For example, when the time exceeds 10 msec, the threshold rises. Is shown graphically. Therefore, if the write time becomes longer than this upper limit, electric charges are injected into the memory transistors of the non-selected cells connected to the same selected word line at the final stage of the write, and the write is performed to some extent.

The first problem is basically that the MONOS
Type, MNOS type, etc.
Type, MNOS type, etc., charge traps are discretized, so that it is considered that the gate insulating film is more excellent in scalability than the FG type. In addition, the writing speed is not easily reduced with the lowering of the voltage at the time of writing, which is more advantageous than the FG type in this point.

A second problem is that the threshold value shift amount (Vth window width) between the write state and the erase state, which tends to decrease with the miniaturization of elements, is not suitable for lowering the program voltage. Can be That is, in a NAND type nonvolatile memory in which the tunnel insulating film and the like of the storage element are optimized so as to be programmed at a lower voltage than in the conventional case, if the Vth window width is not reduced to some extent, in particular, the non-selection of the NAND string at the time of reading is performed. The voltage at which the memory transistor is turned on cannot be lowered, and an unselected memory transistor that is weakly written according to the variation in the threshold value is likely to occur. Also in this respect, erroneous writing tends to occur.

The present invention has been made in view of such circumstances, and has as its object to provide a nonvolatile semiconductor memory device having a structure for effectively preventing erroneous writing to unselected cells due to a reduction in program voltage. Another object of the present invention is to provide a writing method of a nonvolatile semiconductor memory device that can be suitably implemented in the nonvolatile semiconductor memory device and that can effectively prevent erroneous writing to an unselected cell due to a reduction in a program voltage. The purpose of.

[0019]

In order to solve the above-mentioned problems of the prior art and to achieve the above object, in a nonvolatile semiconductor memory device of the present invention, for example, a transistor such as a conventional NAND string is connected in series. In such a cell configuration, there is no common impurity added region (source / drain region) between the transistors, and the semiconductor region is connected to a non-selected memory transistor connected to the same word line as the selected memory transistor. To deplete by capacitive coupling, thereby inducing a write blocking potential. That is, in the nonvolatile semiconductor memory device of the present invention, a voltage is applied to the first control electrode stacked on the channel forming region of the semiconductor via the insulating film including the charge storage means, and the charge is applied to the charge storage means. A non-volatile storage element that stores information by electrically injecting or extracting electric charge from the charge storage means, and an element that transmits a predetermined potential to the channel formation region when the electric charge is injected or extracted. A second semiconductor memory device, which is capacitively coupled to a semiconductor region between the storage element and the element transmitting the predetermined potential, and forms a channel between elements or a depletion layer and controls a potential in the semiconductor region. A control electrode is provided on a semiconductor region between the storage element and an element transmitting a predetermined potential via an insulating film. The element for transmitting the predetermined potential may be another storage element such as a NAND type, for example, and a connection and disconnection between a common wiring and the storage element between a plurality of storage elements in a row direction or a column direction. May be a selection element for controlling.

Preferably, the second control electrode has a plate shape that covers the first control electrode and the charge storage means via an insulating film, and at least a plurality of the memory cells arranged in a row direction. It is provided in common between the element rows. Further, preferably, a plurality of selection elements for controlling connection and disconnection between a common wiring and the storage element between a plurality of storage elements in a row direction or a column direction, and a control electrode of the plurality of selection elements, Controlling the first control electrode, the second control electrode, and the voltage applied to the wiring of the storage element to form an inversion layer in the inter-element semiconductor region adjacent to the selected storage element on which writing is performed; While supplying the predetermined potential to the layer via the corresponding conductive selection element, the first control electrode is connected to the inter-element semiconductor region adjacent to an unselected storage element commonly connected to the selected storage element. And a bias control means for shutting off the corresponding selection element to deplete it into an electrically floating state and inducing a predetermined write blocking potential in the inter-element semiconductor region.

According to a writing method of a nonvolatile semiconductor memory device of the present invention, a plurality of memory elements each having a control electrode laminated on a channel forming region of a semiconductor via an insulating film including charge storage means are arranged in a matrix. A nonvolatile semiconductor memory device in which a memory cell array is formed, and a program voltage is applied to the control electrode to electrically inject charges into the charge storage means or to extract information from the charge storage means to store information. In the method for writing, for the storage element to be written, an inversion layer is formed by a minority carrier in a semiconductor region adjacent to a channel formation region, and the inversion layer can be written by a potential difference from a potential caused by application of the program voltage. The writing is performed by holding at a predetermined potential to be performed, and the information in which the storage element and the control electrode are connected to each other is written. Manai the other memory element and a channel formation region in the semiconductor region adjacent to form a depletion layer in the writing, to induce a write blocking potential.

In such a nonvolatile semiconductor memory device and its writing method, minority carriers are present in the channel formation region and the inter-element semiconductor region due to the capacitive coupling between the first and second control electrodes to which a predetermined potential is applied. Then, an inversion layer is formed for each transistor row including one or more memory transistors. However, in the case where there are a plurality of transistor arrays, the surface side portion of the semiconductor region between the elements is electrically connected to the wiring to supply a certain potential, and when the potential is separated from the wiring supplying the potential. And, a time difference occurs when a channel is formed in an adjacent region. In such a control, for example, in the case of a NAND type in which writing is inhibited using a self-boost technique, a selection transistor connected to a NAND column end of a selected block is turned on and a bit line potential (for example, 0 V) is increased. The minority carriers are rapidly supplied from the bit line, and the NA of the selected block is increased.
In the ND column, the channel is formed earlier. On the other hand, in the unselected block, the selection transistor on the bit line side is cut off, so that the well or the like having the channel formation region on the surface is fixed to, for example, the ground potential, but the surface region at the end of the channel formation region is fixed in potential. Because of the lack, there is no rapid source of minority carriers. Therefore, as compared with the case where a predetermined potential (for example, a ground potential) is supplied from the bit line, channel formation is slower, and the depleted state is maintained longer. At this time, the potential of the inter-element semiconductor region of the non-selected block is pulled up by capacitive coupling with the second control electrode. As a result, a predetermined write-inhibiting potential is applied to the inter-element semiconductor region and, consequently, the adjacent channel formation region. Can be induced.

Conventionally, a non-selected block is alternately connected to a channel forming region and an impurity diffusion layer of the opposite conductivity type at predetermined intervals in the middle of a NAND string, even if it is not connected to a wiring such as a bit line. Since the (source / drain region) is provided, this functions as a source of minority carriers, and the channel is formed at a relatively high speed, although it is slower than the channel formation of the selected block. In addition, the potential difference between successive elements in the channel is reduced, and the absolute value of the potential of the channel formation region of the storage element to be write-protected is set to be larger than the potential of the channel formation region of the adjacent storage element, thereby inhibiting the write protection. It was difficult to ensure.

On the other hand, in the nonvolatile semiconductor memory device of the present invention, there is no impurity diffusion layer acting as such a carrier supply source, and a channel (inversion layer) is formed in a channel formation region adjacent to the impurity diffusion layer. It can be slower than before,
As a result, the write inhibit time becomes longer. That is, the time margin for erroneous writing is increased. Further, the fact that the channel formation can be delayed means that, at a certain time, a voltage margin with respect to a potential difference applied to the tunnel insulating film with respect to a limit value at which erroneous writing occurs increases. Further, a depletion layer is induced between the storage elements and between the storage element and the selection element on the surface of the semiconductor region, and the surface potential can be controlled by the potential of the second control electrode. It is possible to set the absolute value of the surface potential to be large, and it is possible to surely inhibit writing.

In particular, when the charge storage means is discretized in a plane, the voltage margin can be further increased. In the FG type, when the voltage applied to the second control electrode is increased, the potential of the depletion layer (inter-element semiconductor region) increases, but the potential of the charge storage means (floating gate) also increases to some extent due to capacitive coupling. On the other hand, when the charge storage means is discretized in a plane, this is hardly capacitively coupled to the second control electrode, so that the potential difference applied to the tunnel insulating film causing erroneous writing can be rapidly reduced. it can.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to a storage element in which a storage element electrically injects or withdraws electric charge from or to a charge storage means (for example, a floating gate, a charge trap, etc.) by utilizing the capacitive coupling of its control electrode. , And is widely applied to a nonvolatile semiconductor memory device having a cell configuration in which a storage element is connected in series with another storage element or a selection transistor. With such a nonvolatile semiconductor memory device, the type of storage element is not limited, and a normal FG (Float
ing Gate) type and MNOS (Metal-Nitride-Oxide S
emiconductor), MONOS (Metal-Oxide-Nitride-Oxi
de Semiconductor) and further, a nanocrystal type or the like. The memory cell system is not limited to a NAND type, and is applicable to a NOR type (including a layered bit line and a source line, for example, a DINOR type or an AND type) in addition to a NAND type. Hereinafter, MONOS, MNOS type and FG
Embodiments of a nonvolatile semiconductor memory device according to the present invention and a method for manufacturing the same will be described in detail with reference to the drawings, taking a NAND nonvolatile memory device having a type FET as a storage element as an example.

First Embodiment This embodiment relates to a MONOS type. FIG.
1 is a circuit configuration diagram of a memory cell array of a NAND nonvolatile memory device according to the present embodiment. Also, FIG.
FIG. 2 is a sectional structural view of a NAND string (corresponding to a lower left NAND string in FIG. 1) according to the embodiment.

In FIG. 1, each bit line BLa, BLb
Are connected to two transistor rows (strings). The first string connected to the bit line BLa includes a selection transistor S11a connected to the bit line BLa, a selection transistor S12a connected to the source line SL, and n memories connected in series between the selection transistors. It comprises transistors M11a to M1na. The second string connected to the bit line BLa is a select transistor S2 connected to the bit line BLa.
1a and a select transistor S connected to a source line SL.
22a, and n memory transistors M21a... Connected in series between both select transistors. Similarly,
Two strings are also connected to the bit line BLb, and the first string includes a selection transistor S11b connected to the bit line BLb, a selection transistor S12b connected to the source line SL, and a connection between both selection transistors. Memory transistors M11 connected in series to
b to M1nb. The second string connected to the bit line BLb includes a selection transistor S21b connected to the bit line BLb, a selection transistor S22b connected to the source line SL, and n memories connected in series between the selection transistors. The transistors M21b ...

Select transistors S11a and S11b
Are controlled by a bit line selection signal line SG11, and the selection transistors S12a and S12b are both controlled by a source line selection signal line SG12. Similarly,
Select transistors S21a and S21b are both controlled by bit line select signal line SG21, and select transistors S22a and S22b are both controlled by source line select signal line SG22. Further, the memory transistors M11a and M11b, M12a and M12b, M13a
, M13b,..., M1na and M1nb are controlled by word lines WL11, WL12, WL13,. Similarly, the memory transistors M21a and M21b are controlled by the word line WL21.

In each of the interconnected strings, a p-type well (p-well 4) is formed on the surface side of the n-type semiconductor substrate 2, for example, as shown in the cross section of FIG. A transistor row is arranged on the surface side of the p-well.

Memory transistors M11a to M1na
Is formed on the p-well 4 by tunnel insulating film 8 and nitride film 1
0, a top oxide film 12 to form a gate insulating film. Also, a polysilicon layer 1 is formed on the gate insulating film.
6 and word lines WL11 to WL1n formed of a refractory metal silicide layer 18 thereon. This word line corresponds to the “first control electrode” of the present invention. Further, the surface portion of the p-well below the first control electrode comprising the polysilicon layer and the refractory metal silicide layer is the “channel forming region” in the present invention, and the surface portion of the p-well between the first control electrodes is the same in the present invention. It corresponds to an “inter-element semiconductor region”.

The selection transistors S11a, S12a, etc. are constituted by ordinary MOSFETs. Therefore, the gate insulating film 14 is composed only of the silicon oxide film. The gate electrode layers of the selection transistors S11a and S12a form a bit line selection signal line SG11 and a source line selection signal line SG12, respectively.

One of the structural features of the nonvolatile memory according to the present embodiment is that the p-well 4 is formed in the surface region (inter-element semiconductor region) of the p-well 4 between the memory transistors and between the memory transistor and the selection transistor. This means that no impurity region of the opposite conductivity type (source / drain region 6c in FIG. 14 showing a conventional example) is formed. Another impurity region of the opposite conductivity type, that is, a drain impurity region 6a of the opposite conductivity type common to another string adjacent to one side in the bit direction.
And a source impurity region 6b (source line SL) of the opposite conductivity type common to the other adjacent string is provided in the same manner as in the related art.

Another structural feature of the nonvolatile memory according to the present embodiment is that a second control electrode 22 is provided on a transistor row via an interlayer insulating layer 20 made of, for example, silicon oxide. . This second control electrode 22
For example, one plate is formed for each transistor row from above one of the selection transistors to above the other selection transistor. The second control electrode 22 is close to the semiconductor region between the memory transistors or between the memory transistor and the selection transistor via the interlayer insulating layer 20. And the lower p-well 4
In the surface portion (inter-element semiconductor region), the formation of an inter-element channel or a depletion layer and the control of the potential are controlled.

A relatively thick interlayer insulating layer 24 is formed on the entire surface including the second control electrode 22, and a bit contact BC is formed in the interlayer insulating layer 24 on the drain impurity region 6a. The contact hole 24a is formed by embedding a metal plug such as W with an adhesive layer such as Ti / TiN interposed therebetween. In the form of being connected to a transistor row by bit contact BC,
The bit line BLa is wired on the interlayer insulating layer 24.
Although not particularly shown, the bit line BLa is usually, for example, A
It has a three-layer structure in which an upper and lower main wiring layer such as 1 is sandwiched between an antireflection layer (or a protective layer) and a barrier metal.

In the NAND type nonvolatile memory device having such a configuration, there is no impurity region between the memory transistor and another transistor adjacent thereto. Therefore, there is an advantage that erroneous writing is effectively prevented as described later.

Next, the manufacturing method will be described. FIG.
6 to 6 are cross-sectional views showing each manufacturing process of the nonvolatile memory device having the above-described configuration.

Prior to FIG. 3, first, for example, LOCOS is applied to the surface of the prepared substrate (n-type semiconductor substrate 2).
Alternatively, an element isolation region is formed by a trench. Although not appearing in the cross-sectional view, the element isolation region is formed alternately with each transistor column in a parallel stripe shape long in the bit direction, thereby achieving element isolation mainly in the row direction.

Next, as shown in FIG. 3A, a p-well 4 is formed on the surface of the substrate by ion implantation. The p-well 4 has an epitaxial growth layer,
An SOI layer or the like formed on a substrate (other than a semiconductor such as a quartz or sapphire substrate) via an insulating layer can be used. The tunnel insulating film 8 is formed by, for example, thermally oxidizing the surface of the p-well 4. The tunnel insulating film 8 is formed by thermally nitriding thermal silicon oxide in addition to silicon oxide.
The surface portion or all of the thermally oxidized silicon may be silicon nitride oxide. A nitride film 10 made of, for example, silicon nitride is formed on the tunnel insulating film 8 by a CVD method or the like.

Next, as shown in FIG. 4B, a resist pattern RP is formed to cover only the portion where the memory transistor row is to be formed. The nitride film in the portion where is formed is removed. At the time of this etching, it is desirable to leave at least a part of the tunnel insulating film 8 so as not to introduce etching damage to the substrate side.

In FIG. 4C, thermal oxidation is performed. When at least a part of the tunnel insulating film 8 is left in the previous step,
It is desirable to completely remove by a wet treatment such as a pretreatment for thermal oxidation. Due to this thermal oxidation, a thick thermal oxide film serving as the gate insulating film 14 of the select transistor is formed in the select transistor portion where the well 4 is almost exposed, while the top oxide film 12 of the memory transistor is formed on the nitride film 10.
Is formed thinly. At this time, the nitride film 1
The film thickness is reduced by 0 to obtain a final desired nitride film thickness.

In FIG. 5D, the polysilicon layer 1 doped with impurities and made conductive is formed on the thermal oxide films 12 and 14.
6 and the refractory metal silicide layer 18 are laminated by a normal polycide forming method.

In FIG. 5E, the resist pattern R
Using P as a mask, the underlying laminated film is etched to form parallel striped word lines WL11 to WL1n and the like and select signal lines SG11 and SG12 at the same time.
In this figure, all etching is performed until the silicon layer is exposed, but to suppress the introduction of damage to the substrate side,
The lowermost oxide film may be partially left in all regions, and may be removed later by wet etching.

Next, after removing the resist pattern RP,
As shown in FIG. 6F, for example, a first material such as silicon oxide is used.
Is thinly formed on the entire surface. This film is
For example, it is formed by any method of thermal oxidation or CVD. When the word lines and the like are made of polysilicon, a thermal oxidation method can be adopted. If the word line is polycide, CVD
By law. After that, a conductive layer serving as the second control electrode 22 is formed on the entire surface and further so as to bury the space between the gate electrodes.
This is etched using a resist pattern (not shown) as a mask. The second control electrode 2 thus formed
In order to control the formation of an inter-element channel or a depletion layer and the potential, 2 needs to cover at least the space between the electrodes of the memory transistor. The second control electrode may be formed in a buried line shape separated for each space between the transistor electrodes, and may be electrically connected at a location (not shown). With the resist pattern of the second control electrode 22 or a mask for forming the second control electrode 22 attached thereto, ion implantation is performed using the resist pattern as a mask, and a drain impurity region is formed on the surface of the p-well 4 using the first interlayer insulating layer 20 as a through film. 6a
And the source impurity region 6b to be the source line SL is formed at the same time.

Thereafter, as shown in FIG. 2, a thick second interlayer insulating layer 24 is deposited and flattened, and a bit contact hole 24a is opened, a connection plug is buried, and a bit line is wired. The nonvolatile memory device is completed.

Next, the operation of writing, erasing, and reading data of the memory transistor in the NAND nonvolatile memory device having such a configuration will be described. The present invention can be applied to a case where this memory transistor stores multivalued information in addition to binary information. Here, an operation between two states of normally on and normally off will be described. In the case of multi-valued data, the basic operation is the same since the word line voltage or the bit line at the time of programming or reading is shifted stepwise, for example, in the positive direction.

First, in the read operation, the potential of the word line (selected word line) to which the cell to be read (selected cell) is connected and the well are fixed to 0 V, and all the selected transistors and the word lines (non-selected) other than the selected word line are set. A voltage VRG that makes all of the memory transistors connected to the selected word line) conductive is applied to all the selected signal lines and unselected word lines. This voltage V RG can be obtained only by the potential difference from the well.
The size does not allow writing and erasing to the memory transistor. Further, the voltage applied to the second control electrode is:
In a NAND string including cells to be read, a voltage at which a channel between elements is formed is selected. In this state, when a positive voltage is applied only to the bit line (selected bit line) to which the selected cell is connected, all the memory transistors other than the cell from which information is read are in a conductive state. Whether the current flows or does not flow through the selected bit line is determined depending on whether the current is on or normally off. The presence or absence of this current is detected to determine the logical state “1” or “0” of the stored data.

The erasing operation is performed in a block unit or a memory cell array collectively, as in the conventional case. With all the select transistors turned off, 0 is applied to all the word lines in the erasing unit.
V, a high voltage V _PP is applied to all word lines and substrates or wells of a non-selected NAND string. As a result, only the memory transistors in the selected block have holes injected from the substrate side into the nitride film and trap levels (charge traps) existing near the interface between the nitride film and the oxide film, and the threshold voltage of the memory transistor is negative. To a normally-on erased state (the logical state corresponds to, for example, "1").

On the other hand, the data programming operation is performed for the memory transistors connected to the word line at a time in a so-called page unit. Specifically, usually, writing is performed from the page near the source side of the selected block row, but first, with the selection transistor on the source line side turned off,
For example, 0 V is applied to the selected bit line, and a power supply voltage of, for example, about V _DD (for example, about 5 V) is applied to the gate of the selection transistor on the bit line side (bit line selection signal line) and unselected bit lines. Then, a voltage to such an extent that the non-selected cells conduct is applied to the non-selected word lines, and a high program voltage V _PP is applied to the selected word lines. Then, NAN of the selected block
Since the selection transistor connected to the end of the D column is turned on and the bit line potential (for example, 0 V) is supplied, minority carriers are rapidly supplied from the bit line, and the channel of the NAND column of the selected block is Formed quickly. As a result, only the selected memory transistor to be programmed,
Electrons are injected into the trap level existing in the nitride film and near the interface between the nitride film and the oxide film, and the threshold voltage of the selected memory transistor shifts in the positive direction and becomes higher than the erased state, for example, a normally erased state. The writing state is turned off.

On the other hand, in a non-selected block, the select transistor on the bit line side changes from the conductive state to the cut-off state with a slight potential rise obtained by subtracting the threshold voltage of the select gate from the applied voltage of the bit line select signal line. Therefore, although the well itself having the channel forming region on the surface is fixed at the ground potential, the potential of the surface region at the end of the channel forming region is not fixed. There is no drain impurity region and no rapid source of minority carriers. Therefore, the selected NAND to which a predetermined potential (for example, ground potential) is supplied from the bit line
Channel formation is slower than in the column side, and the depleted state is maintained for a long time (constant time). While the depletion layer is formed, the potential of the inter-element semiconductor region of the non-selected NAND string is pulled up by capacitive coupling with the second control electrode 22, and as a result, the inter-element semiconductor region, As a result, a predetermined write-inhibiting potential is induced in the adjacent channel formation region, thereby preventing erroneous writing.

As described above, according to the present embodiment, the inter-element semiconductor region in which the source / drain impurity regions are conventionally formed is self-boosted in a depleted state by capacitive coupling with the second control electrode 22. During this time, there is enough time to complete the application pulse (write pulse) of the program voltage V _PP , that is, the write inhibition time becomes longer. As a result, a time margin for erroneous writing is increased. Further, the fact that the channel formation can be delayed means that, at a certain time, a voltage margin with respect to a potential difference applied to the tunnel insulating film with respect to a limit value at which erroneous writing occurs increases. In particular, in this example, since the charge storage means is discretized in a plane, the voltage margin can be further increased. That is, in the FG type, when the voltage applied to the second control electrode is increased, the potential of the depletion layer (inter-element semiconductor region) increases, but the potential of the charge storage means (floating gate) also increases due to capacitive coupling with the second control electrode. Although this rises to some extent, in this example, since the charge storage means is discretized in a plane, this is hardly capacitively coupled to the second control electrode, so that the potential difference applied to the tunnel insulating film causing erroneous writing is reduced. Can be reduced rapidly.

In a nonvolatile memory device, a program operation is generally performed while repeating a kind of read operation for verifying whether a desired threshold value is obtained by programming with a write pulse. That is, when a desired threshold value is obtained in the verification after programming, the next programming is performed on the memory transistor while setting the write inhibit state by the self-boost operation, and the threshold value is verified again. This is repeated until a desired value is obtained for all the threshold values of the memory transistors connected to the word line.

In the nonvolatile memory device of this embodiment and its writing method, it is possible to make the write pulse width longer than before by making the write inhibit time longer, and in particular, to allow the threshold value to be finally controlled. In a multi-valued memory technology with a narrow width, there is an advantage that the degree of freedom in controlling the write pulse width is increased. Further, even when the programming voltage is lowered and the writing time is delayed because the scaling of the element is not suitable for the lowering of the voltage, erroneous writing can be effectively prevented. Furthermore, if the program voltage tends to be lower and the reduction of the Vth window width cannot keep up with this, in order to turn on all the non-selected memory transistors at the time of reading, it is necessary to lower the pass voltage applied to the gate. However, the fact that channel formation is difficult due to the present invention means that erroneous writing does not easily occur even at a high pass voltage that results in a weak writing state in the related art. Can be prevented.

Second Embodiment This embodiment relates to an MNOS type nonvolatile memory device. In the nonvolatile memory device of the present embodiment, the memory transistor is changed from the MONOS type of the first embodiment to MN.
Except for the change to the OS type, the circuit configuration and operation of the basic cell array shown in FIG. 1 are the same as those of the first embodiment. Therefore, here, only the cross-sectional structure and the manufacturing method of the NAND string will be described, and the others will be omitted. In addition, the same reference numerals are given to the same configuration in the cross-sectional configuration, and the detailed description is not given.

FIG. 7 is a sectional view in the bit direction of a NAND string in the nonvolatile memory device according to the second embodiment of the present invention. Memory transistor M11 of the present embodiment
In a to M1na, the gate insulating film is formed by laminating a tunnel insulating film 30 and a nitride film 32 on the p-well 4. Further, the gate insulating film 34 of the select transistor may be composed of only a silicon oxide film as in the first embodiment, but here is a laminated film of a silicon oxide film and a silicon nitride film. In this case, since the lower silicon oxide film has a relatively large thickness of, for example, about 10 nm, it does not function as a memory element. As in the first embodiment, this NAND type nonvolatile memory device has an advantage that erroneous writing is effectively prevented because there is no impurity region between the memory transistor and another transistor adjacent thereto.

FIGS. 8 to 11 are sectional views showing the steps of manufacturing the nonvolatile memory device having the above-described structure. First, in the same manner as in the first embodiment, an element isolation region and a p-well 4 are formed in a prepared substrate 2, and a relatively thick gate oxide film of about 10 nm is formed by, for example, thermally oxidizing the surface of the p-well 4. 5 is formed (FIG. 8A).

As shown in FIG. 9B, a resist pattern RP is formed on the gate oxide film 5, and the gate oxide film 5 in the memory transistor portion is removed by etching using the resist pattern RP as a mask. In FIG. 9C, the tunnel insulating film 30 of the memory transistor is formed by a thermal oxidation method. At this time, the gate oxide film 5 has a slightly increased oxide film thickness. The tunnel insulating film 30 may be formed by forming a thermally oxidized silicon film and then thermally nitriding at least the surface portion. A nitride film 32 is formed on the tunnel insulating film 30.
Is deposited to a relatively large thickness of several tens nm by, for example, a CVD method.

Thereafter, as in the first embodiment, a polycide composed of the polysilicon layer 16 and the refractory metal silicide layer 18 is formed (FIG. 10D), and this is masked using the resist pattern RP. First, the underlying laminated film is etched to form word lines WL11 to WL1n and the like and select signal lines SG.
11, SG12 and the like are simultaneously formed (FIG. 10E). After removing the resist pattern RP, the first interlayer insulating layer 20 is formed thin (FIG. 11 (f)), and after the second control electrode 22 is formed thereon (FIG. 11 (g)), The non-volatile memory is completed through various processes such as deposition of the second interlayer insulating layer 24, formation of the bit contact BC, and wiring of the bit line BLa.

The nonvolatile memory device of the present embodiment has the same advantages as the first embodiment. That is, since there is no impurity region of the opposite conductivity type on the inner surface side of the p-well in the NAND string as in the related art, the write inhibition time can be lengthened in the write inhibition of the non-selected NAND string by self-boost. For this reason, erroneous writing can be effectively prevented when the writing speed is low due to the lowering of the program voltage or when the reduction of the Vth window width cannot keep up with the lowering of the voltage. Also, the degree of freedom in controlling the write pulse width increases.

Third Embodiment This embodiment relates to an FG type nonvolatile memory device. The non-volatile memory device of the present embodiment has the same circuit configuration and operation of the basic cell array shown in FIG. 1 as the first embodiment, except that the memory transistor is changed from the MONOS type of the first embodiment to FG. .

FIG. 12 is a sectional view in the bit direction of a NAND string in the FG type nonvolatile memory device according to the third embodiment. As shown in FIG. 12, between the tunnel insulating film 8 and the intermediate insulating film 40 (corresponding to the top oxide film of the first embodiment), for example, polysilicon is used instead of the nitride film of the first embodiment. Floating gate 42 is interposed. The intermediate insulating film 40 is made of a silicon oxide or ONO film or the like, like the top oxide film of the first embodiment. Other configurations with the same reference numerals are the same as those in the first embodiment.

The method of manufacturing the FG type nonvolatile memory device having such a structure is similar to that of the first embodiment shown in FIG.
0, a polysilicon film is formed, which is patterned in FIG. 4B, and a top oxide film 1 is formed in FIG.
Forming an intermediate insulating film in the same manner as in FIG.
Except that the intermediate insulating film and the polysilicon film are simultaneously patterned at the time of the electrode processing of (e), it can be performed in the same manner as in FIGS. 3 to 6 showing the manufacturing method of the first embodiment.

The nonvolatile memory device of the present embodiment also has the same advantages as the first embodiment. That is, since there is no impurity diffusion region between the elements as in the prior art, the write inhibition time can be extended in the write inhibition by the self-boost, the erroneous write of the non-selected NAND string can be effectively prevented, and the control of the write pulse width can be controlled. It has a number of advantages such as increased freedom.

[0064]

According to the nonvolatile semiconductor memory device and the writing method of the present invention, erroneous writing due to a decrease in the program voltage can be effectively prevented, and slow writing control, for example, in the case where the writing pulse width is increased. The degree of freedom increases. Therefore, it is possible to provide a nonvolatile semiconductor memory device having excellent reliability and characteristics even when miniaturization and low-voltage writing are promoted, and a writing method thereof.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a memory array of a NAND nonvolatile memory device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view in a bit direction centering on a string located at the lower left of FIG. 1 according to the first embodiment of the present invention;

3 is a cross-sectional view showing each manufacturing process of the NAND-type nonvolatile memory device in FIG. 2, showing up to the formation of a nitride film forming a gate insulating film.

FIG. 4 is a sectional view following FIG. 3, showing the process up to the formation of a top oxide film constituting a gate insulating film;

FIG. 5 is a cross-sectional view subsequent to FIG. 4, showing up to etching of a word line, a selection signal line, and a gate insulating film;

FIG. 6 is a cross-sectional view following FIG. 5, showing up to the formation of a second control electrode.

FIG. 7 is a cross-sectional view in the bit direction centering on a string located at the lower left of FIG. 1 according to the second embodiment of the present invention.

8 is a cross-sectional view showing each manufacturing process of the NAND-type nonvolatile memory device of FIG. 7 and shows up to formation of an oxide film serving as a gate insulating film of a selection transistor.

FIG. 9 is a cross-sectional view subsequent to FIG. 8, showing up to the formation of a nitride film forming a gate insulating film;

FIG. 10 is a sectional view following FIG. 9, showing the processing up to etching of the word line and the selection signal line and the gate insulating film;

FIG. 11 is a cross-sectional view following FIG. 10, showing up to the formation of a second control electrode.

FIG. 12 is a cross-sectional view in the bit direction centering on a string located at the lower left of FIG. 1 according to the third embodiment of the present invention.

FIG. 13 is a circuit diagram showing a configuration of a memory array of a conventional NAND type nonvolatile memory device.

FIG. 14 is a cross-sectional view in the bit direction centering on a string located at the lower left of FIG. 1 according to a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Semiconductor substrate, 4 ... P well, 5 ... Oxide film, 6a-6c ... Impurity area, 8, 30 ...
Tunnel insulating film, 10, 32 nitride film, 12 top oxide film, 14, 34 gate insulating film, 16 polycide layer, 18 refractory metal silicide layer, 20 ... first interlayer insulating layer (insulating film) , 22 ... second control electrode, 24 ... second
, An intermediate insulating film, 42, FG, a floating gate, M11, etc., a memory transistor, ST
11a, ST21a, etc .: selection transistor, CG: control gate, SG11, SG12, etc .: selection signal line,
BLa etc. bit line, WL11 etc. word line, BC ... bit contact.

Claims (14)

[Claims] A voltage is applied to a first control electrode laminated on a semiconductor channel formation region via an insulating film including a charge storage means, and a charge is electrically injected into the charge storage means. A non-volatile semiconductor storage device, comprising: a storage element that stores information by extracting charge from the charge storage means; and an element that transmits a predetermined potential to the channel forming region when the charge is injected or extracted. A second control electrode, which is capacitively coupled to a semiconductor region between the storage element and the element transmitting the predetermined potential and controls the formation of an inter-element channel or a depletion layer and the control of the potential with respect to the semiconductor region; A nonvolatile semiconductor memory device provided over a semiconductor region between a memory element and an element transmitting a predetermined voltage via an insulating film. 2. The semiconductor device according to claim 1, wherein the channel forming region and a semiconductor region between the storage element and the element transmitting the predetermined potential are:
2. The non-volatile semiconductor memory device according to claim 1, wherein the non-volatile semiconductor memory device includes the same impurity-doped region. 3. A memory cell array comprising a plurality of storage elements arranged in rows and columns, wherein the element for transmitting the predetermined potential includes a wiring common to a plurality of storage elements in a row direction or a column direction and the storage element. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is a selection device that controls connection and disconnection with the device. 4. A plurality of storage elements are arranged in a matrix to form a memory cell array, and the element transmitting the predetermined potential is a voltage from a common wiring among a plurality of storage elements in a row direction or a column direction. Is another storage element that conducts when a voltage is applied to the storage element.
3. The nonvolatile semiconductor memory device according to 1. 5. A plurality of selection elements for controlling connection and disconnection of a common wiring and the storage elements between a plurality of storage elements in a row direction or a column direction, and control electrodes of the plurality of selection elements, Controlling an applied voltage to the first control electrode, the second control electrode, and the wiring of the storage element, and forming an inversion layer in the inter-element semiconductor region adjacent to the selected storage element for writing. While supplying the predetermined potential to the inversion layer via a corresponding conductive selection element, an inter-element semiconductor region adjacent to an unselected storage element whose first control electrode is commonly connected to the selected storage element 2. The non-volatile semiconductor device according to claim 1, further comprising: a bias control unit that deactivates the corresponding selection element by turning off the corresponding selection element so as to be electrically floating, thereby inducing a predetermined write blocking potential in the inter-element semiconductor region. Body storage. 6. A memory array is formed by arranging a plurality of storage element columns each having a plurality of storage elements connected in series via a selection element between a bit line and a common potential line, in a matrix. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the second control electrode is provided between each storage element in the storage element row and between storage elements at both ends of the storage element row and a selection element. 3. 7. The plurality of memory elements arranged in a row direction at least in a row direction, wherein the second control electrode has a plate shape that covers the first control electrode and the charge storage means via an insulating film. 7. The non-volatile semiconductor storage device according to claim 6, wherein the non-volatile semiconductor storage device is provided in common between columns. 8. The nonvolatile semiconductor memory device according to claim 1, wherein said charge storage means is discretized at least in a plane facing said channel formation region. 9. The storage element according to claim 1, wherein a tunnel insulating film, a nitride film, and a top oxide film are formed on the channel formation region.
9. The non-volatile semiconductor memory device according to claim 8, wherein the charge storage means is a charge trap formed discretely in the stacked film. 10. The storage element, wherein a tunnel insulating film and a nitride film are laminated on the channel formation region between the storage element and the first control electrode. 9. The nonvolatile semiconductor memory device according to claim 8, wherein the nonvolatile semiconductor memory device is a charge trap formed by discretization. 11. A memory cell array is formed by arranging a plurality of storage elements in a matrix on a semiconductor channel formation region via an insulating film including charge storage means, the control electrodes being arranged in a matrix. A method of electrically injecting charges into said charge storage means by applying a program voltage to said charge storage means or extracting charges from said charge storage means and storing information, wherein said writing is performed. With respect to the storage element, writing is performed by forming an inversion layer using minority carriers in a semiconductor region adjacent to the channel formation region and holding the inversion layer at a predetermined potential at which writing is performed by a potential difference from a potential caused by application of the program voltage. The other storage element, in which the storage element and the control electrode are connected to each other and does not write information, has the channel type Forming a depletion layer in the writing to the semiconductor region adjacent to the region, the writing method of the nonvolatile semiconductor memory device inducing the writing prevention potential. 12. The writing method according to claim 11, wherein said charge storage means is discretized at least in a plane opposed to said channel forming region. 13. The storage element according to claim 13, wherein a tunnel insulating film, a nitride film, and a top oxide film are laminated on the channel formation region between the control electrode and the charge storage means. 13. The method according to claim 12, wherein the charge trap is a charge trap formed discretely. 14. The storage element according to claim 1, wherein a tunnel insulating film and a nitride film are stacked on the channel formation region between the storage electrode and the control electrode. The method according to claim 12, wherein the charge trap is a formed charge trap.