JPH1065028A - Nonvolatile semiconductor memory device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device with low power consumption and improved reliability, in which the bias applied in writing or erasing of data is not so high, and a manufacturing method of the memory device. SOLUTION: A nonvolatile semiconductor memory device comprises a memory cell having source and drain regions 19 formed in a semiconductor substrate 11, a first gate insulating film 13 formed on the semiconductor substrate 11 between the source and drain regions 19, a floating gate 14 as an electric-charge storing layer formed on the first gate insulating film 13, a second gate insulating film 15 formed on the floating gate 14, and a control gate 16 formed on the second gate insulating film 15. In this case, a length w2 in a gate length direction of a gate bird's beak 20b formed in the interface among the second gate insulating film 15, the floating gate 14 and the control gate 16 is equal to or shorter than a length w1 in the gate length direction of a gate bird's beak 20a formed in the interface between the first gate insulating film 13 and the floating gate 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same, and more particularly to a nonvolatile semiconductor memory device capable of electrically writing and erasing data and a method of manufacturing the same.

[0002]

2. Description of the Related Art Demand for a nonvolatile semiconductor memory device has been greatly increased in recent years because it has an advantage that data is not erased even when power is turned off. A flash memory, which is a nonvolatile semiconductor memory device that can be electrically erased in a batch, is different from a byte type nonvolatile semiconductor memory device of a two-transistor type in that the
A memory cell can be formed using a transistor. As a result, it is possible to reduce the size of the memory cell, and it is expected that a magnetic disk having a large capacity will be used as a substitute.

Among such flash memories, a NAND type EEPROM is known as being particularly advantageous for high integration. It has the following structure. That is, a plurality of memory cells are arranged, for example, in the column direction, and the sources and drains of adjacent cells among these cells are sequentially connected in series. With such a connection, a unit cell group (N
AND cells), and these unit cell groups are connected to bit lines as one unit.

[0004] On the other hand, a memory cell has a stacked gate structure in which a floating gate, which normally serves as a charge storage layer, and a control gate are stacked. The memory cells are integrally formed in a matrix in a p-type well formed in a p-type substrate or an n-type substrate. The drain side of the NAND cell is connected to a bit line via a select gate. The source side of the NAND cell is connected to a source line (reference potential wiring) via a selection gate. The control gate of each memory cell is connected to a word line arranged in the row direction.

In writing data to the NAND cell, for example, after all transistors in the NAND cell have their transistor thresholds made negative by an erasing operation, the memory cell located farthest from the bit line is first set. Are performed sequentially. Specifically, a high voltage is applied to the control gate of the selected memory cell, an intermediate potential is applied to the control gate and select gate of the memory cell on the bit line side, and then the write data is applied to the bit line. 0 V or an intermediate potential according to.

That is, when 0 V is applied to the bit line, electrons generated in the channel region between the source and drain regions are injected into the floating gate by the FN tunnel phenomenon. As a result, the threshold value of the transistor of the selected memory cell shifts in the positive direction, and data “0” is written. Conversely, when an intermediate potential is applied to the bit line, electrons are not injected into the floating gate, the threshold value of the transistor remains negative, and the selected memory cell assumes the state of data "1". .

Further, in erasing the data thus written, for example, all the control gates and select gates are set to 0 V, the bit lines and the source lines are floated, and the memory cells are placed on the n-type substrate. When formed in the formed p-type well, a high voltage is applied to the p-type well and the n-type substrate. As a result, electrons in the floating gate of all the memory cells are extracted to the p-type well by the FN tunnel phenomenon, and the threshold value of the transistor of the memory cell shifts in the negative direction. That is, data is erased simultaneously for all memory cells.

In general, in a NAND cell, a high voltage is applied to a control gate or a p-type well and an n-type substrate in order to allow electrons to be sufficiently injected or extracted from a floating gate during data writing and erasing as described above. , It is necessary to supply an effectively high electric field between the floating gate and the substrate. Here, the magnitude of the electric field between the floating gate and the substrate is determined by the ratio of the capacitance of the insulating film between the control gate and the floating gate to the capacitance of the insulating film between the floating gate and the substrate, that is, the cup. It is determined by the ring ratio.

Specifically, a value obtained by multiplying the voltage applied to the control gate by this coupling ratio at the time of writing, and a value obtained by multiplying the voltage applied to the substrate by the coupling ratio at the time of erasing are the difference between the floating gate and the substrate. This is the voltage applied between them. Therefore, in a NAND cell having a coupling ratio of, for example, 0.65 and an insulating film between the floating gate and the substrate made of a silicon oxide film having a thickness of 0.01 μm, electrons are sufficiently supplied to the floating gate by the FN tunnel phenomenon. In order to be implanted or extracted, a high bias of 20 V is applied to the control gate or the p-type well and the n-type substrate, and an electric field of about 13 MV / cm is supplied to the insulating film between the floating gate and the substrate. Required. The relationship between the coupling ratio and the bias at the time of the write or erase operation is determined by the data write operation using substrate hot electrons.
The same is true for OR-type memory cells and the like.

[0010]

In a nonvolatile semiconductor memory device having a stacked gate structure of a floating gate and a control gate as described above, the charge accumulated in the floating gate often leaks to the semiconductor substrate side. It becomes a problem. That is, if the floating gate is simply formed by etching or the like, both ends of the floating gate tend to have an acute angle where electric field concentration tends to occur, and as a result, the charges accumulated in the floating gate are transferred from this portion to the semiconductor substrate. And may leak. Therefore, the threshold value of the transistor of the memory cell fluctuates, which may cause a malfunction when reading data written in the memory cell, inversion of data at the time of storage, and the like, and the reliability of the semiconductor memory device is remarkably increased. Will drop.

On the other hand, if the main surface of the floating gate is oxidized by post-oxidation in the stacked gate structure of the floating gate and the control gate to form a gate bird's beak in a region between the floating gate and the semiconductor substrate, Electric field concentration at both ends of the floating gate is suppressed, and as a result, leakage of accumulated charges to the semiconductor substrate can be prevented, and the reliability of the semiconductor memory device can be improved. Here, FIG. 19 shows a longitudinal sectional view of the stacked gate structure in the semiconductor memory device thus obtained.

As shown, such a semiconductor memory device is provided on a semiconductor substrate 41 such as a p-type silicon semiconductor substrate.
It has a stacked gate structure in which a floating gate 43 mainly composed of polysilicon and a control gate 45 are sequentially stacked via a first gate insulating film 42 and a second gate insulating film 44 made of a silicon oxide film or the like. I have. Also, the semiconductor substrate 41
In FIG. 7, source and drain regions 46 each composed of an n ⁺ type diffusion layer are formed on both sides of such a gate, and a post-oxide film 47 is formed on the semiconductor substrate 41 so as to cover the entire surface thereof. 47a in the figure is a gate bird's beak formed in a region between the floating gate 43 and the semiconductor substrate 41. By forming such a gate bird's beak 47a, both ends of the floating gate 43 are shaped. Dulling and electric field concentration such as when electric charges are accumulated can be avoided.

However, as described above, when an attempt is made to form the gate bird's beak 47a in the region between the floating gate 43 and the semiconductor substrate 41, the floating gate 43 is simultaneously formed in the region between the floating gate 43 and the control gate 45. That the gate bird's beak 47b is formed in a region larger than the region between the semiconductor substrate 41 and the semiconductor substrate 41. That is, in the stacked gate structure as shown in FIG. 19, the floating gate 43 and the control gate 45 are generally connected to each other because the thickness of the second gate insulating film 44 is larger than that of the first gate insulating film. Oxidation proceeds more easily in the region between the two. Anyway,
When the length of the gate bird's beak 47b formed in the region between the floating gate 43 and the control gate 45 increases, the effective thickness of the insulating film interposed between the floating gate 43 and the control gate 45 increases. The effective area is reduced, and the capacitance is reduced. Therefore, the second gate insulating film 4
The value of the coupling ratio, which is the ratio of the capacitance of the capacitor 4 and the capacitance of the first gate insulating film 42, decreases, and the applied voltage required for writing and erasing data in NAND cells and the like increases.

As described above, in a nonvolatile semiconductor memory device having a stacked gate structure of a floating gate and a control gate, a gate bird's beak is formed in a region between the floating gate and the semiconductor substrate and stored in the floating gate. Attempts have been made to prevent the leakage of the accumulated charges to the semiconductor substrate and thereby to increase the reliability of the semiconductor memory device. In this case, however, the applied voltage required for writing or erasing data in the memory cell is reduced. As a result, there is a problem that the design of a high breakdown voltage transistor is indispensable for peripheral circuits and the like, and furthermore, the power consumption is increased. The present invention has been made to solve the above problems, and to provide a nonvolatile semiconductor memory device in which a bias applied when writing or erasing data is not so high, low power consumption and improved reliability, and a method of manufacturing the same. The purpose is.

[0015]

According to the present invention, there is provided a semiconductor device comprising: a source and a drain region formed in a semiconductor substrate; and a first region formed on the semiconductor substrate between the source and the drain region. A gate insulating film and the first
A floating gate serving as a charge storage layer formed on the gate insulating film, a second gate insulating film formed on the floating gate, and a control gate formed on the second gate insulating film. And a gate bird's beak formed at the interface between the second gate insulating film and the floating gate and the control gate, wherein the length in the gate length direction is equal to the first gate insulating film and the floating gate. The length of the gate bird's beak formed at the interface with the gate length in the gate length direction or less. Further, the present invention also provides a first source and drain region formed in a semiconductor substrate, a first gate insulating film formed on the semiconductor substrate between the first source and drain regions, A floating gate serving as a charge storage layer formed on the first gate insulating film, a second gate insulating film formed on the floating gate, and a control gate formed on the second gate insulating film. And a second source and drain region formed in the semiconductor substrate; a third gate insulating film formed on the semiconductor substrate between the second source and drain regions; A MOS transistor forming a part of a peripheral circuit comprising a gate electrode formed on a third gate insulating film;
The length of the gate bird's beak formed at the interface between the gate insulating film and the floating gate and the control gate in the gate length direction is the length of the gate bird's beak formed at the interface between the first gate insulating film and the floating gate. Provided is a nonvolatile semiconductor memory device having a length not more than a length in a gate length direction and not more than a length in a gate length direction of a gate bird's beak formed at an interface between the third gate insulating film and the gate electrode.

That is, the nonvolatile semiconductor memory device of the present invention is characterized in that the length of the gate bird's beak formed on the upper and lower surfaces of the second gate insulating film is suppressed.
In the present invention, the second gate insulating film may be formed of a single layer of a silicon oxide film, or a stacked film of a silicon oxide film, a silicon nitride film and a silicon oxide film, that is, a so-called ONO (Oxide-Nitride). -Oxide) It may be a laminated film.

Here, the nonvolatile semiconductor memory device of the present invention as described above is characterized in that the oxidation rate of the floating gate is higher in the lower layer and lower in the upper layer, if desired. In addition, the oxidation rate of the control gate is lower than the oxidation rate of the lower layer of the floating gate. For this purpose, for example, the floating gate may be formed of polysilicon having a high impurity concentration below the floating gate and a low impurity concentration on the upper layer, and the control gate may have an impurity concentration as low as that of the upper layer of the floating gate. What is necessary is just to form with the polysilicon which has.

That is, source and drain regions formed in a semiconductor substrate, a first gate insulating film formed on the semiconductor substrate between the source and drain regions, and a first gate insulating film formed on the first gate insulating film. A memory cell including a formed floating gate serving as a charge storage layer, a second gate insulating film formed on the floating gate, and a control gate formed on the second gate insulating film; The floating gate is made of doped polysilicon, and the impurity concentration is higher on the lower side of the floating gate and lower on the upper side. And the control gate is made of doped polysilicon.
A nonvolatile semiconductor memory device characterized in that the impurity concentration is lower than the lower layer side of the floating gate. Specifically, the impurity concentration on the lower layer side of the floating gate is a high concentration of 5 × 10 ²⁰ to 1 × 10 ²¹ cm as long as it does not exceed the doping limit (Solid Solubility) of commonly used impurity species such as P.
^-3 , the impurity concentration of the upper layer and the impurity concentration of the control gate are 1 × 10
It is preferably set to about ²⁰ to 4 × 10 ²⁰ cm ⁻³ .

Further, in the case where the nonvolatile semiconductor memory device of the present invention is formed by integrating a large number of memory cells in a matrix on a semiconductor substrate, the gate bird's beak gate described above is applied to each memory cell. It is preferable to make the lengths in the long direction uniform. To this end, the length of the gate bird's beak formed at the interface between the first gate insulating film and the floating gate in the gate length direction is w ₁ , and the second gate insulating film, the floating gate, and the control gate are Assuming that the length of the gate bird's beak formed at the interface of the gate length direction is w ₂ and the gate lengths of the floating gate and the control gate are w, (w−2w ₂ ) / (w
−2w ₁ ) ± 5 throughout all memory cells.
% Is desired. Here, (w−2w ₁ ) and (w−2w ₂ ) represent the gate length of the floating gate on the first gate insulating film side excluding the gate bird's beak portion and the side of the second gate insulating film, respectively. Of the floating gate and the control gate in FIG.

Further, the method for manufacturing a nonvolatile semiconductor memory device according to the present invention comprises the steps of sequentially laminating a first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer on a semiconductor substrate. Patterning the second conductive layer, the second insulating layer, and the first conductive layer to obtain a control gate and a floating gate; and forming an oxide film on a semiconductor substrate surface provided with the control gate and the floating gate. Forming a thin layer, doping an impurity in a semiconductor substrate using the control gate and the floating gate as a mask to obtain source and drain regions, and oxidizing a material on the oxide thin layer after doping the impurity. Depositing, and etching back the obtained oxidation-resistant film to selectively leave the oxidation-resistant film on the side surface of the control gate and the floating gate; and after etching back the oxidation-resistant film, Floating Those comprising the step of advancing the oxidation of over bets. That is, according to such a manufacturing method, since the oxidation of the floating gate proceeds preferentially on the lower surface side, the length of the gate bird's beak formed on the upper and lower surfaces of the second gate insulating film is reduced as described above. It is possible to easily obtain the nonvolatile semiconductor memory device according to the present invention, which is characterized by being suppressed. Here, the oxidation-resistant film left on the side surfaces of the control gate and the floating gate may be removed after the oxidation of the floating gate.

On the other hand, the nonvolatile semiconductor memory device of the present invention
Sequentially stacking a first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer on a semiconductor substrate;
Forming a control gate and a floating gate by patterning the conductive layer, the second insulating layer, and the first conductive layer, and forming an oxide film on a semiconductor substrate surface provided with the control gate and the floating gate. In the method for manufacturing a nonvolatile semiconductor memory device, the method further includes a step of promoting the oxidation of the main surface of the floating gate. The method can also be performed by setting the oxidation rate of the floating gate higher on the lower layer side and lower on the upper layer side. Further, in this case, in order to suppress the length of the gate bird's beak on both the upper surface and the lower surface of the second gate insulating film, the oxidation rate of the control gate is set lower than the oxidation rate of the lower layer of the floating gate. It is preferred that

That is, in the present invention, even in such a manufacturing method, the oxidation of the floating gate proceeds preferentially on the lower surface side, and the formation of gate bird's beaks on the upper and lower surfaces of the second gate insulating film is effectively suppressed. Can be Subsequently, if the control gate and the floating gate are used as masks and the semiconductor substrate is doped with impurities, the source and drain regions can be easily obtained. As a result, the second method can be performed similarly to the above-described manufacturing method. The non-volatile semiconductor memory device according to the present invention, wherein the length of the gate bird's beak formed on the upper surface and the lower surface of the gate insulating film is reduced.

[0023]

Embodiments of the present invention will be described below in detail with reference to the drawings. First, FIGS. 1A and 1B show a plan view and a circuit diagram of one NAND cell when a nonvolatile semiconductor memory device of the present invention is applied to a NAND type EEPROM. FIG. 2 is a sectional view of such a NAND cell taken along the line AA ′ of FIG. 1A, and FIG.
FIG. 2 is a circuit diagram of a memory cell of a D-type EEPROM. As shown, here it constitutes the eight memory cells M ₁ ~M ₈ are connected in series one NAND cell.

That is, in each memory cell, the floating gate 14 (14 ₁ , 14 ₂ ,..., 14 ₈ ) serving as a charge storage layer and the control gate 16 are formed on the p-type silicon semiconductor substrate 11.
(16 ₁ , 16 ₂ ,..., 16 ₈ ). Further, each n-type diffusion layer 19 is commonly used as a source on one side and a drain on the other side of two adjacent memory cells, whereby each memory cell is connected in series.

On the other hand, the select gate 1 formed by the same process as the floating gate 14 and the control gate 16 of the memory cell are provided on the drain side and the source side of the NAND cell, respectively.
4 _9, 16 ₉ and 14 _10, 16 ₁₀ are provided. The selection gate 14 _9, 16 ₉ and 14 _10, 16 _10,
Both are electrically connected between the first layer and the second layer at desired portions not shown. The upper part of the p-type silicon semiconductor substrate 11 on which the element is formed is covered with the interlayer insulating film 17. The bit line 18 is formed on the interlayer insulating film 17.
The bit line 18 is in contact with the drain-side n-type diffusion layer 19 at one end of the NAND cell.

Further, the control gates 14 in the same row of a plurality of NAND cells arranged in the row direction are connected in common and arranged as control gate lines CG ₁ , CG ₂ ,..., CG ₈ running in the row direction. These control gate lines are so-called word lines. Also, select gate 14 _9, 16 ₉ and 14 _10, 16 _10, it is arranged as the selection gate lines SG _1, SG _2, each running in the row direction.

FIG. 4 is a longitudinal sectional view of one stacked gate structure in the NAND cell as described above. As shown, the first gate insulating film 13 made of a silicon oxide film, the silicon oxide film 15 ₁ , the silicon nitride film 1
5 ₂ and through the silicon oxide film 15 ₃ of the multilayer film a second gate insulating film 15 made of (ONO layered film), a floating gate mainly comprising polysilicon 14 and the control gate 16
Are sequentially laminated to form a laminated gate structure on the semiconductor substrate 11. Further, the entire surface of the stacked gate structure thus formed is covered with the post-oxide film 20.

At this time, in the nonvolatile semiconductor memory device of the present invention, the gate birds at the interface between the second gate insulating film 15 and the floating gate 14 and the control gate 16 in the vertical section of the stacked gate structure shown in FIG. beaks 20b length w _2, is suppressed to less than the length w ₁ of the gate bird's beak 20a at the interface between the first gate insulating film 13 and the floating gate 14. That is, the floating gate 14 and the control gate 1
In the area between 6 and 6, the gate birds beak 20b
Is suppressed, while a gate bird's beak 20a is sufficiently formed in a region between the floating gate 14 and the semiconductor substrate 11. Therefore, the applied voltage at the time of writing or erasing data due to the decrease in the coupling ratio as described above does not significantly increase,
Electric field concentration at both ends of the floating gate 14 can be avoided, and leakage of charges accumulated in the floating gate 14 to the semiconductor substrate 11 can be effectively prevented.

FIG. 5 shows the gate bird's beak 20.
FIG. 9 is a characteristic diagram illustrating a relationship between the lengths of a and 20b and a write voltage. However, the horizontal axis in the drawing indicates the gate length of the floating gate 14 facing the first gate insulating film 13 excluding the gate bird's beak 20a as shown in FIG. 4 by L ₁ (= w−
2w ₁ ), gate bird's beak 20 b of the floating gate 14 and the control gate 16 facing the second gate insulating film 15
When the gate length excluding the portion was _{L 2 (= w-2w 2} ), it represents the value L ₂ / L ₁ ratio of L ₁ with respect to L _2. The write voltage V _pp of the vertical axis in the figure, to the control gate 16 is shifted by a predetermined amount threshold of the transistor for a predetermined time (80 [mu] sec) memory cells by applying a bias (-
(2V → 2V). In the present invention, as shown in FIG. _{5, L 2 / L 1 ≧} 1 range, the relationship between the length w ₂ of length w ₁ and the gate bird's beak 20b of gate bird's beak 20a in other words w ₂ ≦ w ₁
In, when the length of the gate bird's beak 20b w ₂ is suppressed to less than the length w ₁ of the gate bird's beak 20a, it can be seen that the write voltage V _pp is reduced to 18V or less.

In the present invention, it is desired that the variation in the value of L ₂ / L ₁ be kept within ± 5% throughout all the memory cells. This is because when the variation in the value of L ₂ / L ₁ exceeds 5%, the difference between the easiness of writing and erasing data for each memory cell is large, and thus the threshold voltage of the transistor for all memory cells. This is because the verify operation for converging the distribution tends to be complicated.

Further, according to the present invention, the semiconductor device is provided in the same semiconductor substrate 11 as the stacked gate structure shown in FIG.
Also for the gate insulating film of the MOS transistor forming a part of the peripheral circuit for the AND cell, it is possible to form a gate bird's beak to the same extent as the interface between the first gate insulating film 13 and the floating gate 14 on the side of the stacked gate structure. preferable. FIG. 6 is a longitudinal sectional view showing a MOS transistor having such a gate bird's beak together with a stacked gate structure.

That is, when injecting or extracting electrons from or to the floating gate 14 in a NAND cell or the like, it is usually necessary to apply a high voltage to the control gate 16 or the semiconductor substrate 11 or the like. Accordingly, since a specific peripheral circuit inevitably operates at a high voltage, it is desired to increase the junction withstand voltage of a MOS transistor forming a part of such a peripheral circuit, particularly in a drain region.

In FIG. 6, a gate bird's beak 20c is formed at the interface between the third gate insulating film 23 and the gate electrode 24 in the MOS transistor provided in the same semiconductor substrate 11 as the stacked gate structure. . Here, the length w ₃ of the gate bird's beak 20c in FIG. 6 is preferably the gate bird's beak 20a on the side of the stacked gate structure.
Is set to be approximately the same as or greater than the length w ₁ .
As a result, the effective thickness of the third gate insulating film 23 increases, so that a practically sufficient junction breakdown voltage can be secured even in the n-type diffusion layer 19 on the drain side of the MOS transistor. In addition, the method of forming the gate bird's beak 20c in the present invention is the simplest method in which the gate bird's beak 20a is formed by the same process as the gate bird's beak 20a, but is not particularly limited thereto.

The above is a case where the non-volatile semiconductor memory device of the present invention is applied to a NAND type EEPROM. However, the present invention is not limited to this, but is applied to a NOR type, a DINOR type, and an A type.
The present invention can be widely applied to a nonvolatile semiconductor memory device having a stacked gate structure such as an ND type. Next, these NOR type, DI
Circuit diagrams of NOR-type and AND-type memory cells will be described with reference to FIGS.

FIGS. 7A and 7B are circuit diagrams of a memory cell of a NOR type EEPROM. FIG. 7A is a circuit diagram without a selection gate, and FIG. 7B is a circuit diagram with a selection gate. As shown in FIG. 7A, in a NOR type EEPROM, one memory cell is connected in series between a bit line BL and a source line VS orthogonal to the bit line BL. Alternatively, as shown in FIG. 7B, a bit line side selection gate and one memory cell are connected in series between the bit line BL and a source line VS orthogonal to the bit line BL.

FIGS. 8A and 8B are circuit diagrams of memory cells of another NOR type EEPROM called a ground array type, and FIG. 8B is a circuit diagram of an alternate ground array type. Ground array type NO as shown
In an R-type EEPROM, bit lines BL and bit lines BL
One memory cell is connected in series between the source lines VS in parallel with. In FIG. 8A, the bit line BL and the source line VS are fixed, but in the alternate ground array type shown in FIG.
And the source line VS can be switched.

FIG. 9 is a circuit diagram of a memory cell of a DINOR type EEPROM. DIN as shown in FIG.
In an OR type EEPROM, one sub-bit line S
A memory cell is connected in parallel between BL and the plurality of source lines VS, and the sub-bit line SBL is connected to the bit line BL via a bit-line-side selection gate.

FIG. 10 is a circuit diagram of a memory cell of the AND type EEPROM. As shown, in the AND type EEPROM, a bit line side select gate, a memory cell group connected in parallel with each other, and a source line side select gate are connected in series between a bit line BL and a source line VS.

Next, a method for manufacturing the nonvolatile semiconductor memory device of the present invention will be described in detail. 11 to 14 are vertical sectional views showing steps of a first method for manufacturing a nonvolatile semiconductor memory device according to the present invention. In the drawing, reference numeral 50 denotes a memory cell region in which a large number of memory cells having the above-described stacked gate structure are integrated and formed in a matrix, and reference numeral 51 denotes a peripheral circuit region in which a peripheral circuit for such a memory cell is formed.

In the first manufacturing method, first, a p-type impurity is implanted into the element isolation region of the p-type silicon semiconductor substrate 11 as necessary, and then a field oxide film (not shown) is formed by, for example, a selective oxidation method. I do. Next, a thermal oxide film serving as the first gate insulating film 13 and the like is formed on the entire surface of the semiconductor substrate 11, and a first polysilicon layer is deposited thereon. However, the first polysilicon layer here is, for example, POCl ₃
Is used to dope P by about 1 × 10 ²⁰ to 4 × 10 ²⁰ cm ⁻³ to lower the resistance.

Further, the silicon oxide film 15 is formed by a CVD method or the like.
₁ and were sequentially laminated silicon nitride film 15 _2, selects etching the desired resist pattern formed on the by photolithography as an etch mask.
Here, the silicon nitride film 15 ₂ and the silicon oxide film 15 ₁
At the same time, the first polysilicon layer is etched away in the etching mask opening, and the upper surface of the field oxide film forming the element isolation region and the surface of the thermal oxide film of the semiconductor substrate 11 corresponding to the peripheral circuit region 51 are exposed.

Subsequently, after removing the resist pattern,
Thermal oxidation method or CVD method, a silicon oxide film 15 ₃ silicon nitride film 15 ₂ and on the exposed semiconductor substrate 11 surface Choice formed by. At this time, the first silicon Similarly, the side surface of the polysilicon layer oxide film 15 ₃ patterned above is formed.

Next, on the semiconductor substrate 11, P etc. is set to 1 × 10 ²⁰ to 4 × 10 ²⁰ as in the case of the first polysilicon layer.
After depositing a second polysilicon layer doped at about cm ^-3 , selective etching is performed by photolithography using a desired resist pattern formed thereon as an etching mask. Here, the second polysilicon layer, a silicon oxide film 15 _3, the silicon nitride film 15 _2, the silicon oxide film 15 ₁ and the first polysilicon layer is etched in the memory cell region 50, the floating gate in the stacked gate structure 14, a second gate insulating film 15 and a control gate 16 are obtained. In this manner, the drain side and source side select gates (not shown) as shown in FIG. 2 are also formed.

Next, after removing the resist pattern, a desired resist pattern is formed in exactly the same manner, and using this as an etching mask, the second polysilicon layer is etched in the peripheral circuit region 51 to form a part of the peripheral circuit. Forming M
The gate electrode 24 of the OS transistor is obtained. In this manner, as shown in FIG. 11, in the memory cell region 50 on the semiconductor substrate 11, an array having a stacked gate structure in which the floating gate 14 and the control gate 16 are stacked, and in the peripheral circuit region 51, the gate electrode 24 of the MOS transistor is formed. It is formed.

Next, as shown in FIG. 12, a thin oxide film layer 21 is formed on the entire surface of the semiconductor substrate 11 by a thermal oxidation method or the like.
At this time, in the first method for manufacturing the nonvolatile semiconductor memory device of the present invention, the region between the floating gate 14 and the control gate 16 and the region between the floating gate 14 and the gate electrode 24 and the semiconductor substrate 11 are formed. It is important to control the oxidation conditions so that the formation of the gate bird's beak is not remarkable. Specifically, the oxidation may be performed until the oxide film thickness on the main surface of the semiconductor substrate 11 becomes 10 to 30 nm, preferably about 20 nm. If the oxidation here is insufficient, damage to the semiconductor substrate 11 due to ion implantation or the like during the formation of source and drain regions in a later step is likely to be large. Conversely, if the oxidation is too large, the floating gate 14 Region between control gate 16 and floating gate 1
4 or in a region between the gate electrode 24 and the semiconductor substrate 11,
The formation of the gate bird's beak tends to proceed extremely.

Subsequently, using the control gate 16 and the floating gate 14 in the memory cell region 50 and the gate electrode 24 in the peripheral circuit region 51 as masks, n, such as P, As, etc. are formed in the semiconductor substrate 11 by ion implantation or the like. An n-type diffusion layer 19, which is doped with a type impurity and is a source and a drain region of a MOS transistor forming a part of a memory cell transistor or a peripheral circuit, is provided. Next, an oxidation resistant material such as silicon nitride is deposited on the oxide thin film layer 21 formed over the entire surface of the semiconductor substrate 11 to a thickness of about 50 to 150 nm, and then etched back using an anisotropic etching technique. As shown in FIG. 13, the oxidation resistant film 25 is selectively left on the side surfaces of the control gate 16 and the floating gate 14 and the side surface of the gate electrode 24. Here, the reason why the deposition amount of the oxidation-resistant material is set to 50 to 150 nm is that 50 to 150 nm.
If it is less than 150 nm, it is difficult to sufficiently suppress the formation of the gate bird's beak 20 b in the region between the floating gate 14 and the control gate 16. If it exceeds 150 nm, the oxide film immediately below it during the etch back as described above. It becomes difficult to stop the etching at the thin layer 21 and, consequently, the MOS forming the transistor of the memory cell or part of the peripheral circuit
This is because the source and drain regions of the transistor are etched, which may cause a decrease in transistor performance.

Next, as shown in FIG. 14, oxidation of the floating gate 14 and the gate electrode 24 is advanced by a thermal oxidation method or the like.
Gate bird's beaks 20a, 20b, 20c are formed. At this time, in the region between the floating gate 14 or the gate electrode 24 and the semiconductor substrate 11, oxygen is supplied through the oxide film portion 12a immediately below the oxidation-resistant film 25, whereas the floating gate 14 and the control gate 16 Since the oxidation-resistant film 25 almost completely shuts off the supply of oxygen, the oxidation of the floating gate 14 proceeds preferentially on the lower surface side. Therefore, the formation of the gate bird's beak 20b at the interface between the second gate insulating film 15 and the floating gate 14 and the control gate 16 is suppressed while the first gate insulating film 1 is formed.
3 and the floating gate 14 and the third gate insulating film 23.
The gate bird's beak 20
a, 20c can be effectively formed.

The gate bird's beaks 20a, 20b,
In forming the layer 20c, a thick post-oxide film 20 is formed on the gate electrode 24 and the surface of the semiconductor substrate 11 where the oxidation-resistant material has been removed by etching.
Note that the oxidation conditions here are such that the oxide film thickness on the surface of the semiconductor substrate 11 is 10 times more than that of the oxide film thin layer 21 as described above.
It is preferable to control the thickness to about 30 nm, preferably about 20 nm. That is, if the oxidation here is insufficient, the first gate insulating film 13 and the floating gate 14
Gate bird's beaks 20a and 20c are hardly formed sufficiently at the interface between the gate electrode and the third gate insulating film 23 and the gate electrode 24. Conversely, if the oxidation is excessively advanced, the gate bird's beak will be generated every memory cell. The variation in the length of 20a in the gate length direction becomes large.

Next, although not particularly shown, the semiconductor substrate 11
An interlayer insulating film made of a silicon oxide film is deposited on the entire surface by a CVD method or the like, and a specific n-type diffusion layer 19 is formed on the obtained interlayer insulating film.
After opening a contact hole for contact with the n-type diffusion layer 19, a wiring such as a bit line electrically connected to the n-type diffusion layer 19 is formed through the contact hole. Thus, for example, FIG.
In addition, a nonvolatile semiconductor device including the NAND cell as shown in FIG. 2 is manufactured.

In the first method of manufacturing the nonvolatile semiconductor memory device of the present invention as described above, the oxidation of the floating gate 14 and the gate electrode 24 in FIG. 14 is advanced, and the gate bird's beaks 20a, 20b, 20c are formed. After the formation, it is desirable to remove the oxidation-resistant film 25 on the side surfaces of the control gate 16 and the floating gate 14 and the side surfaces of the gate electrode 24. If the oxidation resistant film 25 is left,
There is a tendency that the data retention in the memory cell is reduced, and the peripheral circuit side has, for example, a MOS transistor having an LDD structure.
When a transistor is formed, performance degradation of the transistor due to hot carrier traps becomes a problem.
Further, particularly when the relatively thick oxidation-resistant film 25 is formed, if the oxidation-resistant film 25 is not removed, the space between the memory cells is narrow when depositing the interlayer insulating film, and a hole is generated here. There is also a risk. In the present invention, the method of removing the oxidation-resistant film 25 is not particularly limited, and for example, the oxidation-resistant film 25 made of silicon nitride is removed.
, A wet etching technique using hot phosphoric acid (H ₃ PO ₄ ) may be used.

FIGS. 15 to 18 are vertical sectional views showing steps of a second method for manufacturing a nonvolatile semiconductor memory device according to the present invention. In the second manufacturing method, first, as in the first manufacturing method described above, a p-type impurity is implanted into the element isolation region of the p-type silicon semiconductor substrate 11 as necessary, and then, for example, a selection is performed. A field oxide film (not shown) is formed by an oxidation method. Next, as shown in FIG. 15, a thermal oxide film 30 is formed on the entire surface of the semiconductor substrate 11, and a first polysilicon layer 31 is deposited thereon.

However, here, the first polysilicon layer 3
1 is doped with P or the like, the lower layer 31a side and the upper layer 31
The doping amount is controlled so as to be different from that on the b side. Specifically, the impurity concentration on the lower layer 31a side is 5 × 10 ²⁰ to 1 × 1.
0 ²¹ cm ^{-3 and} the impurity concentration on the upper layer 31b side is 1 × 10
It is set to about ²⁰ to 4 × 10 ²⁰ cm ⁻³ . In FIG. 15, although the impurity concentration in the first polysilicon layer 31 changes stepwise, the impurity concentration near the lower surface of the first polysilicon layer 31 is 5 × 10 ²⁰ to 1 × 10
^{About 21} cm ^-3 , impurity concentration near the upper surface is 1 × 10 ^{20 -4}
If it is controlled to be about × 10 ²⁰ cm ⁻³ , the impurity concentration in the first polysilicon layer 31 may be continuously changed.

Further, the silicon oxide film 15 is formed by a CVD method or the like.
₁ and were sequentially laminated silicon nitride film 15 _2, selects etching the desired resist pattern formed on the by photolithography as an etch mask.
Here, the silicon nitride film 15 ₂ and the silicon oxide film 15 ₁
At the same time, the first polysilicon layer 31 is etched away at the etching mask opening (not shown), and the field oxide film forming the element isolation region is exposed.

Subsequently, after removing the resist pattern,
Forming a silicon oxide film 15 ₃ on the semiconductor substrate 11 by a thermal oxidation method or CVD method, or the like. At this time, the first silicon Similarly, the sides of the polysilicon layer 31 oxide film 15 ₃ patterned above is formed. Furthermore, a resist pattern formed by photolithography as an etching mask, the silicon oxide film 15 ₃ in the peripheral circuit region 51, the silicon nitride film 15 ₂ and the silicon oxide film 15 _1, is removed by etching as shown in FIG. 16.

Then, P and the like are formed on the semiconductor substrate 11 at 1 × 10 ²⁰ to 4 × 10 ²⁰ cm ⁻³ as in the case of the first manufacturing method.
After depositing a lightly doped second polysilicon layer, selective etching is performed by photolithography using a desired resist pattern formed thereon as an etching mask. That is, the second polysilicon layer, a silicon oxide film 15 _3, the silicon nitride film 15 _2, the silicon oxide film 15 ₁ and the first polysilicon layer 31 is etched in the memory cell region 50 and the peripheral circuit region 51. Thus, as shown in FIG. 17, the floating gate 14, the second gate insulating film 15, the control gate 16, the drain side and source side select gates (not shown) in the stacked gate structure, and a part of the peripheral circuit The gate electrode 24 of the MOS transistor is formed. The gate electrode 24 obtained here is a lower layer 31a and an upper layer 31b of the first polysilicon layer 31 in FIGS. 15 and 16, and a lower layer corresponding to the second polysilicon layer formed thereon. 24a, an upper layer 24b, and an uppermost layer 24c.

Next, as shown in FIG. 18, an oxide film 33 is formed on the entire surface of the semiconductor substrate 11 by a thermal oxidation method or the like. At this time, in the second method of manufacturing the nonvolatile semiconductor memory device of the present invention, the region between the floating gate 14 and the control gate 16 and the floating gate 14, the gate electrode 24 and the semiconductor substrate Unlike the first manufacturing method in which the formation of the gate bird's beak is suppressed in any of the regions between the floating gate 14 and the gate electrode 24, only the region between the semiconductor substrate 11 and the gate bird's beak is suppressed. The beaks 20a and 20c are selectively formed.

That is, here, the impurity concentrations of the lower layer 14a of the floating gate 14 and the lower layer 24a of the gate electrode 24 are set higher than those of the upper layer 14b and the control gate 16 of the floating gate 14.
4 and the floating gate 1 compared to the control layer 16
4 and the lower layer 24a of the gate electrode 24 have a specifically high oxidation rate. Therefore, oxidation can proceed preferentially on the lower layer 14a of the floating gate 14 and the lower layer 24a of the gate electrode 24. As a result, the interface between the first gate insulating film 13 and the floating gate 14, the third The gate bird's beaks 20a and 20c can be sufficiently formed at the interface between the gate insulating film 23 and the gate electrode 24.

In this case, however, the gate bird's beak 20 in the region between the floating gate 14 and the control gate 16
From the viewpoint of suppressing the formation of b, it is necessary to control the oxidation conditions. Specifically, the oxidation may be performed until the oxide film thickness on the main surface of the semiconductor substrate 11 becomes 10 to 30 nm, preferably about 20 nm. If the oxidation here is insufficient, the gate bird's beak 20
It is difficult to form a and 20c sufficiently, and damage to the semiconductor substrate 11 due to ion implantation or the like is likely to increase when forming source and drain regions in a later step. On the other hand, if the oxidation is too large, the formation of the gate bird's beak tends to proceed extremely in the region between the floating gate 14 and the control gate 16, and furthermore, the source and the source are formed by ion implantation in a later step. It becomes difficult to form a drain region.

Next, although not particularly shown, the memory cell area 5
0, the semiconductor substrate 11 is doped with an n-type impurity such as P or As by ion implantation using the control gate 16 and the floating gate 14 as masks, and the gate electrode 24 in the peripheral circuit region 51 as a mask. An n-type diffusion layer 19 serving as source and drain regions of a MOS transistor forming a part of a transistor or a peripheral circuit is provided. Thereafter, if necessary, the oxidation of the floating gate 14 and the gate electrode 24 may be further advanced by a thermal oxidation method or the like to promote the formation of the gate bird's beaks 20a and 20c. Next, as in the first manufacturing method, an interlayer insulating film made of a silicon oxide film is deposited on the entire surface of the semiconductor substrate 11 by a CVD method or the like, and a contact for contact with a specific n-type diffusion layer 19 is formed on the obtained interlayer insulating film. After the opening of the hole, if a wiring such as a bit line electrically connected to the n-type diffusion layer 19 through the contact hole is formed, the nonvolatile semiconductor device of the present invention is manufactured.

In the present invention, the MOS transistor forming a part of the peripheral circuit as described above is not particularly limited to the N-channel type shown in FIG.
It may be formed in a well of the opposite conductivity type or the same conductivity type as the semiconductor substrate. Further, for example, the n-type diffusion layer may have an LDD structure having an n ⁻ region in the vicinity of the channel, or the third gate insulating film may be formed thicker than the first gate insulating film on the side of the stacked gate structure. It does not matter. Further, within the scope that does not change the gist of the present invention,
In addition, the present invention can be implemented by being appropriately modified.

[0061]

As described above in detail, according to the present invention, a nonvolatile semiconductor memory device having a low bias applied at the time of writing or erasing data, low power consumption, and high reliability, and a method of manufacturing the same. Can be provided.

[Brief description of the drawings]

FIG. 1A illustrates a NAND according to an embodiment of the present invention.
FIG. 3B is a plan view of the cell, and FIG.

FIG. 2 is a cross-sectional view taken along line AA ′ of the NAND cell shown in FIG.

FIG. 3 is a circuit diagram of a memory cell of a NAND type EEPROM.

FIG. 4 is a longitudinal sectional view of one stacked gate structure in a NAND cell.

FIG. 5 is a characteristic diagram showing a relationship between a gate bird's beak length and a write voltage.

FIG. 6 is a longitudinal sectional view showing a MOS transistor in which a gate bird's beak is formed together with a stacked gate structure.

7A and 7B are circuit diagrams of a memory cell of a NOR type EEPROM, in which FIG. 7A is a circuit diagram without a selection gate, and FIG. 7B is a circuit diagram with a selection gate.

FIGS. 8A and 8B are diagrams showing another NOR type EEPROM;
3 is a circuit diagram of the memory cell of FIG.

FIG. 9 is a circuit diagram of a memory cell of a DINOR type EEPROM.

FIG. 10 is a circuit diagram of a memory cell of an AND type EEPROM.

FIG. 11 is a longitudinal sectional view showing steps of a first method for manufacturing a nonvolatile semiconductor memory device of the present invention.

FIG. 12 is a vertical sectional view showing steps of a first method for manufacturing a nonvolatile semiconductor memory device of the present invention.

FIG. 13 is a vertical sectional view showing steps of a first method for manufacturing a nonvolatile semiconductor memory device of the present invention.

FIG. 14 is a longitudinal sectional view showing steps of a first method for manufacturing a nonvolatile semiconductor memory device of the present invention.

FIG. 15 is a longitudinal sectional view showing steps of a second method for manufacturing a nonvolatile semiconductor memory device of the present invention.

FIG. 16 is a longitudinal sectional view showing steps of a second method for manufacturing a nonvolatile semiconductor memory device of the present invention.

FIG. 17 is a longitudinal sectional view showing a step of the second method for manufacturing the nonvolatile semiconductor memory device of the present invention.

FIG. 18 is a vertical sectional view showing steps of a second method for manufacturing a nonvolatile semiconductor memory device according to the present invention.

FIG. 19 is a longitudinal sectional view of a laminated gate structure in a semiconductor memory device in which a gate bird's beak is formed in a region between a floating gate and a semiconductor substrate.

[Explanation of symbols]

11: semiconductor substrate, 13: first gate insulating film, 14 ...
Floating gate, 15: second gate insulating film, 16: control gate, 17: interlayer insulating film, 19: n-type diffusion layer, 20: post-oxide film, 20a, 20b, 20c: gate bird's beak, 23: third Gate insulating film, 24 ... gate electrode, 2
5: oxidation resistant film, 30: thermal oxide film, 31: first polysilicon layer, 33: oxide film, 50: memory cell region, 51
... peripheral circuit area.

Claims (20)

[Claims] A source and drain region formed in the semiconductor substrate; a first gate insulating film formed on the semiconductor substrate between the source and drain regions; and a first gate insulating film formed on the first gate insulating film. A memory cell including a formed floating gate serving as a charge storage layer, a second gate insulating film formed on the floating gate, and a control gate formed on the second gate insulating film; The length of the gate bird's beak formed in the interface between the second gate insulating film and the floating gate and the control gate in the gate length direction is:
A nonvolatile semiconductor memory device, wherein a length of a gate bird's beak formed at an interface between the first gate insulating film and the floating gate is equal to or less than a length in a gate length direction. A first source and drain region formed in the semiconductor substrate; a first gate insulating film formed on the semiconductor substrate between the first source and drain regions; A floating gate serving as a charge storage layer formed on the gate insulating film, a second gate insulating film formed on the floating gate, and a control gate formed on the second gate insulating film. A second source and drain region formed in the semiconductor substrate; a third gate insulating film formed on the semiconductor substrate between the second source and drain regions; 3
A MOS transistor forming a part of a peripheral circuit including a gate electrode formed on the gate insulating film of
The length of the gate bird's beak formed at the interface between the second gate insulating film and the floating gate and the control gate in the gate length direction is the gate formed at the interface between the first gate insulating film and the floating gate. A length of the bird's beak which is equal to or less than a length in a gate length direction, and a length which is equal to or less than a length of a gate bird's beak formed in an interface between the third gate insulating film and the gate electrode in a gate length direction. Semiconductor memory device. 3. The nonvolatile semiconductor memory device according to claim 1, wherein said second gate insulating film is a stacked film of a silicon oxide film, a silicon nitride film and a silicon oxide film. 4. The nonvolatile semiconductor memory device according to claim 1, wherein an oxidation rate of said floating gate is higher on a lower layer side and lower on an upper layer side. 5. The nonvolatile semiconductor memory device according to claim 4, wherein an oxidation rate of said control gate is lower than an oxidation rate of a lower layer of said floating gate. 6. The nonvolatile semiconductor memory device according to claim 4, wherein said floating gate is made of polysilicon doped with an impurity, and the impurity concentration is higher at a lower layer side of said floating gate and lower at an upper layer side. 7. The nonvolatile semiconductor memory device according to claim 6, wherein said control gate is made of polysilicon doped with an impurity, and has an impurity concentration lower than that of a lower layer of said floating gate. 8. The semiconductor device according to claim 1, wherein a plurality of said memory cells are integrated and formed in a matrix on said semiconductor substrate.
The length of the gate bird's beak formed at the interface between the gate insulating film and the floating gate in the gate length direction is defined as w ₁ ,
When the length in the gate length direction of the gate bird's beak formed at the interface between the gate insulating film and the floating gate and the control gate is w ₂ , and the gate length of the floating gate and the control gate is w, (W-2w ₂ ) / (w-2w
3. The nonvolatile semiconductor memory device according to claim 1, wherein the variation in the value of ₁ ) is within a range of ± 5% across all the memory cells. 4. 9. A semiconductor device comprising: a source and drain region formed in a semiconductor substrate; a first gate insulating film formed on the semiconductor substrate between the source and drain regions; A memory cell including a formed floating gate serving as a charge storage layer, a second gate insulating film formed on the floating gate, and a control gate formed on the second gate insulating film; A nonvolatile semiconductor memory device according to claim 1, wherein said floating gate is made of polysilicon doped with an impurity, and an impurity concentration is high on a lower layer side and low on an upper layer side. 10. The impurity concentration of the lower layer of the floating gate is 5 × 10 ²⁰ to 1 × 10 ²¹ cm ⁻³ , and the impurity concentration of the upper layer is 1 × 10 ²⁰ to 4 × 10 ²⁰ cm ⁻³ . The nonvolatile semiconductor memory device according to claim 9, wherein: 11. The nonvolatile semiconductor memory according to claim 9, wherein said control gate is made of polysilicon doped with an impurity, and has an impurity concentration lower than that of a lower layer of said floating gate. apparatus. 12. An impurity concentration of said control gate is 1 × 10
Claim 1, which is a ^{20 ~4} × 10 ²⁰ cm ^-3
2. The nonvolatile semiconductor memory device according to 1. 13. The nonvolatile semiconductor memory device according to claim 9, wherein said floating gate and said control gate are made of polysilicon doped with P as an impurity. 14. A step of sequentially laminating a first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer on a semiconductor substrate; Patterning a layer and a first conductive layer to obtain a control gate and a floating gate; forming an oxide thin layer on a semiconductor substrate surface provided with the control gate and the floating gate; Doping impurities into the semiconductor substrate using the floating gate as a mask to obtain source and drain regions;
Depositing an oxidation-resistant material on the oxide thin layer after doping the impurity, and etching back the obtained oxidation-resistant film to selectively form an oxidation-resistant film on the side surfaces of the control gate and the floating gate. And a step of promoting the oxidation of the floating gate after etching back the oxidation-resistant film. 15. The method of manufacturing a nonvolatile semiconductor memory device according to claim 14, wherein oxidation of said floating gate is preferentially advanced on a lower layer side. 16. The nonvolatile semiconductor memory according to claim 14, wherein after oxidizing the floating gate, an oxidation-resistant film remaining on side surfaces of the control gate and the floating gate is removed. Device manufacturing method. 17. A step of sequentially laminating a first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer on a semiconductor substrate; Patterning a layer and a first conductive layer to obtain a control gate and a floating gate, forming an oxide film on a semiconductor substrate surface provided with the control gate and the floating gate, and oxidizing a main surface of the floating gate. Wherein the oxidation rate of the floating gate is set higher on the lower layer side and lower on the upper layer side. Manufacturing method. 18. The method for manufacturing a nonvolatile semiconductor memory device according to claim 17, wherein oxidation of said floating gate proceeds preferentially on a lower layer side. 19. The method according to claim 17, wherein an oxidation rate of the control gate is set lower than an oxidation rate of a lower layer of the floating gate. 20. The semiconductor device according to claim 17, wherein after the main surface of the floating gate is oxidized, impurities are doped in the semiconductor substrate using the control gate and the floating gate as a mask to obtain source and drain regions. 13. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1.