JP2002373947A - Method for manufacturing nonvolatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the need for heat treatment over a long time in the impurity diffusion process while protecting a tunnel insulation film against damage due to implantation of impurity ions using a gate electrode as a mask. SOLUTION: A silicon oxide film of 10-50 nm thick is deposited on the entire surface of a semiconductor substrate 11 and subjected to anisotropic etching to form an ion implantation regulating film 18 of silicon oxide on the side face of a gate structure 17. Subsequently, a first resist pattern 51 is formed to expose a source forming region on the side of the gate structure 17 of a P-type well 11a and the ion implantation regulating film 18 on the side face on the source forming region side, and N-type impurity ions are implanted into the P-type well 11a using the exposed part of the first resist pattern 51, the gate structure 17, and the ion implantation regulating film 18 as a mask, thus forming a first N type implantation layer 20A.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device such as a large-capacity EPROM device, an EEPROM device or a flash memory device capable of electrically erasing data. The present invention relates to a device manufacturing method.

[0002]

2. Description of the Related Art A conventional method for manufacturing a nonvolatile semiconductor memory device is disclosed in Japanese Patent Application Laid-Open No. 5-251712 (hereinafter referred to as a first conventional example) or Japanese Patent No. 2515715 (hereinafter referred to as a second conventional example). ).

Hereinafter, a method for manufacturing a conventional nonvolatile semiconductor memory device will be described with reference to the drawings.

FIGS. 7A to 7C and FIG. 8 show cross-sectional structures in the order of steps of a method for manufacturing a conventional nonvolatile semiconductor memory device.

First, as shown in FIG. 7A, a P-type well 101a is formed on a semiconductor substrate 101 made of P-type silicon, and then an element isolation insulating film 102 is selectively formed. Then, in the element formation region on the semiconductor substrate 101,
Tunnel oxide film 103, first polysilicon film 104
A, a capacitor insulating film 105 and a second polysilicon film 106A having a thickness of about 300 nm are sequentially deposited.

Next, as shown in FIG. 7B, the second polysilicon film 106A, the capacitor insulating film 105, the first polysilicon film 104A and the tunnel insulating film 103 are patterned to form a first polysilicon film. A floating gate electrode 104B is formed from the film 104A, and a second polysilicon film 106 is formed.
A control gate electrode 106B is formed from A to obtain a plurality of gate structures 107.

Next, as shown in FIG. 7C, a thermal oxidation method is applied to the entire surface of the semiconductor substrate 101 including the element isolation insulating film 102 and the gate structure 107 by thermal oxidation.
Form 10 Subsequently, a silicon oxide film is deposited on the entire surface of the thermal silicon oxide film 110 by a CVD method, and the deposited silicon oxide film is subjected to anisotropic etching to form a silicon oxide film on the side surface of the gate structure 107. The insulating sidewall spacer 111 is formed. Here, in the first conventional example, the thickness of the insulating sidewall spacer 111 in the direction parallel to the substrate surface is not shown, but ions implanted into the floating gate electrode 104B by implantation of arsenic ions in a later process are not shown. In order to prevent the intrusion of light, the film thickness must be at least about 60 nm. In the second conventional example, the thickness of the insulating sidewall spacer is set to 500 nm.

Subsequently, the acceleration energy for the P-type well 101a is set to 70 keV or more using each of the insulating sidewall spacers 111 and each of the gate structures 107 as a mask.
By implanting arsenic ions at a dose of about 1 × 10 ¹⁶ cm ^{−2 at} 90 keV, an ion implanted layer 112A is formed.

Next, as shown in FIG.
1 is subjected to a heat treatment to spread the arsenic ions of the ion implantation layer 112A to the lower part of the side surface of the gate structure 107, that is, to the end of the channel region, thereby forming the source diffusion layer 112B and the drain diffusion layer 112C.

As described above, according to the first conventional example and the second conventional example, a portion on the side surface and a side portion of the gate structure 107 in the thermally oxidized silicon film 110 has a relatively large insulating thickness. Since it is covered with the sidewall spacer 111, arsenic ions hardly reach the portion on the side surface of the floating gate electrode 104B in the thermal silicon oxide film 110 in particular. As a result, the thermally oxidized silicon film 11
Since the insulating property of the portion on the side surface of the 0 does not decrease, the data retention characteristics of the memory cell can be improved.

[0011]

However, according to the above-described conventional method for manufacturing a nonvolatile semiconductor memory device, the thickness of the insulating side wall spacer 111 is limited to the gate structure 107.
If the ion implantation layer 112 is relatively large compared to
Since the distance between the end of A and the channel region becomes large, it is necessary to perform heat treatment for diffusing implanted ions for a long time.

The heat treatment for a long time is performed when a MOS type semiconductor device for controlling a nonvolatile semiconductor memory device and a MOS type semiconductor device for a microcontroller or a microprocessor requiring a high-speed operation are mixedly mounted. Adversely affects the concentration of various impurities such as channel impurities of the MOS transistor.

More specifically, a dual gate or a polycide gate is often used as a gate electrode of a MOS transistor constituting the microcontroller or the microprocessor. Therefore, if a long-time heat treatment is performed on the dual gate or the polycide gate, boron (B) ions leak from the P ⁺ -type polysilicon constituting the gate, the silicide is peeled off, and the MOS transistor is not subjected to the heat treatment. Or the short channel effect becomes apparent. Accordingly, in recent CMOS technology which requires high performance and miniaturization, the thermal history tends to be reduced as much as possible. In this case, a high performance and miniaturized CMOS circuit and the like and a nonvolatile semiconductor memory device are not used. There is a problem that it becomes difficult to combine the two.

Although not shown, the semiconductor substrate 1
On the side surface of the element isolation insulating film 102 whose step portion is smaller than that of the gate structure 107 on the surface 01, the insulating side wall spacer 111 is not formed with a sufficient film thickness. For this reason, the implanted impurity ions diffuse from both sides of the element isolation insulating film 102 to below the element isolation insulating film 102 due to the long-time thermal diffusion treatment. As a result, the insulation characteristics of the element isolation insulating film 102 are reduced, Element isolation insulating film 10
2 cannot be miniaturized.

On the other hand, the insulating side wall spacer 11
1 is formed on the element isolation insulating film 102 so as to have a sufficient film thickness.
, The gate width must be increased, and in this case also, it is difficult to reduce the size of the element isolation insulating film 102.

When the interval between the gate structures 107 is reduced in order to achieve high integration of the nonvolatile semiconductor memory device, the insulating side wall spacer 111 having a film thickness of half or more of this interval is formed. It cannot be provided.

If the thickness of the insulating side wall spacer 111 is too small in the conventional manufacturing method,
There is a problem that the implanted arsenic ions damage the upper portion and the side portion of the thermal oxide film 110 on the side surface of the gate structure 107.

The present invention has been made in view of the above-mentioned conventional problems, and has as its object to damage a tunnel insulating film due to implantation of impurity ions when forming a source diffusion layer and a drain diffusion layer located on a side of a gate structure. While suppressing heat treatment for a long time in the impurity diffusion step.

[0019]

In order to achieve the above object, the present invention has a structure in which an insulating film for ion implantation adjustment is formed on at least a side surface of a gate structure. This insulating film for adjusting ion implantation can prevent impurity ions from being injected into the tunnel insulating film, and can diffuse impurity ions to the lower portion of the floating gate electrode for a short time by diffusion of the impurity ions by scattering to the semiconductor substrate. The thickness can be reached by heat treatment.

More specifically, a method of manufacturing a nonvolatile semiconductor memory device according to the present invention comprises the steps of: forming a tunnel insulating film in contact with a semiconductor substrate; a floating gate electrode in contact with the tunnel insulating film; A first step of forming a gate structure comprising a floating gate electrode and a control gate electrode opposed to the film, and an ion implantation adjusting film comprising an insulating film on at least a side surface of the floating gate electrode and in contact with the floating gate electrode A third step of implanting impurity ions into the active region on the side of the gate structure in the semiconductor substrate using the gate structure and the ion implantation adjusting film as a mask; And a fourth step of thermally diffusing the implanted impurity ions by performing the heat treatment. In the second step, the ion implantation adjusting film is formed by:
Impurity ions can be prevented from being injected into the tunnel insulating film, and the impurity ions can reach the lower portion of the side end of the floating gate electrode in the active region due to diffusion of the impurity ions by scattering into the semiconductor substrate. Set to film thickness.

According to the method of manufacturing a nonvolatile semiconductor memory device of the present invention, the ion implantation adjusting film made of an insulating film formed at least on the side surface of the floating gate electrode and in contact with the floating gate electrode is formed by tunnel insulating of impurity ions. Since the thickness is set so as to prevent the implantation into the film, the tunnel insulating film is not damaged by the ion implantation. Further, the thickness is set so that the impurity ions can reach the lower part of the floating gate electrode in the active region by diffusion of the implanted impurity ions by scattering into the semiconductor substrate. Thermal diffusion treatment of impurity ions can be completed in a short time. as a result,
It is possible to mount the semiconductor device together with a semiconductor device having a high-performance and miniaturized CMOS circuit.

Furthermore, since the thickness of the impurity ions reaches the lower portion of the floating gate electrode in the active region due to the diffusion of the impurity ions by scattering into the semiconductor substrate, the acceleration energy during ion implantation is relatively small. Since the size can be reduced, it is possible to suppress a decrease in the isolation characteristics of the element.

In the method of manufacturing a nonvolatile semiconductor memory device according to the present invention, it is preferable that the fourth step is performed by performing a heat treatment in an oxidizing atmosphere.

In the method for manufacturing a nonvolatile semiconductor memory device according to the present invention, it is preferable that the thickness of the ion implantation adjusting film is 50 nm or less.

In the method of manufacturing a nonvolatile semiconductor memory device according to the present invention, the ion implantation adjusting film is made of a material having oxygen permeability, and the fourth step is to oxidize the upper part of the active region and to pass through the ion implantation adjusting film. It is preferable to include a step of oxidizing a part of the floating gate electrode with the oxygen.

In the method for manufacturing a nonvolatile semiconductor memory device according to the present invention, it is preferable that the fourth step performs the heat treatment at a temperature of 850 ° C. or higher.

In the method for manufacturing a nonvolatile semiconductor memory device according to the present invention, the second step is a step of depositing an ion implantation adjusting film over the entire surface including the gate structure on the semiconductor substrate; Exposing the active region by anisotropic etching.

In the method of manufacturing a nonvolatile semiconductor memory device according to the present invention, the second step includes a step of forming an ion implantation adjusting film over the entire surface including the gate structure on the semiconductor substrate by a thermal oxidation method. Exposing the upper surface of the active region by performing anisotropic etching on the ion implantation adjusting film.

In the method of manufacturing a nonvolatile semiconductor memory device according to the present invention, the third step is a first ion implantation step performed on one side of the gate structure in the active region, and a gate structure in the active region. A second ion implantation step performed on the other side of the body.

In this case, it is preferable that the first ion implantation step or the second ion implantation step includes a step of implanting at least two types of impurity ions having a conductivity type opposite to the conductivity type of the semiconductor substrate.

Further, in this case, the first ion implantation step or the second ion implantation step includes the step of forming impurity ions of the same conductivity type as the conductivity type of the semiconductor substrate and of a conductivity type opposite to the conductivity type of the semiconductor substrate. It is preferable to include a step of implanting impurity ions.

In the method of manufacturing a nonvolatile semiconductor memory device according to the present invention, the second step is a step of masking one side portion of the gate structure in the ion implantation adjusting film and exposing the other side portion. And a step of performing anisotropic etching on the other exposed side portion of the ion implantation adjusting film.

In this case, it is preferable that the second step includes a step of adjusting the thickness of the ion implantation adjusting film by etching after the anisotropic etching.

In the method for manufacturing a nonvolatile semiconductor memory device according to the present invention, it is preferable that the first step includes a step of forming a protective insulating film on the control gate electrode.

In the method of manufacturing a nonvolatile semiconductor memory device according to the present invention, after the fourth step, a fifth step of forming an insulating sidewall spacer on the side surface of the gate structure via an ion implantation adjusting film. , The gate structure, the ion implantation adjustment film and the insulating sidewall spacers as a mask,
A sixth step of implanting impurity ions of a conductivity type opposite to the conductivity type of the semiconductor substrate.

In the method for manufacturing a nonvolatile semiconductor memory device according to the present invention, it is preferable that the second step includes a step of forming an ion implantation adjusting film from silicon nitride.

In the method of manufacturing a nonvolatile semiconductor memory device according to the present invention, the second step includes the step of forming a first step made of silicon oxide.
It is preferable to form the ion implantation adjustment film by the step of forming the adjustment film and the step of forming the second adjustment film made of silicon nitride on the first adjustment film.

In this case, it is preferable that the second step includes a step of removing the lower end of the second adjustment film after forming the second adjustment film.

[0039]

BEST MODE FOR CARRYING OUT THE INVENTION The present inventors have found that a tunnel insulating film formed by implanting impurity ions into a semiconductor substrate when a source diffusion layer and a drain diffusion layer in a nonvolatile semiconductor memory device are formed by ion implantation and thereafter heat treatment. As a result of various investigations on methods for shortening the heat treatment time for impurity diffusion while preventing damage to the semiconductor, the following findings have been obtained.

That is, a tunnel insulating film, a floating gate electrode, a capacitor insulating film, and a control gate electrode are sequentially stacked on a semiconductor substrate, and a gate structure including the tunnel insulating film, the floating gate electrode, the capacitor insulating film, and the control gate electrode is formed. After the body is formed, the heat treatment time for impurity diffusion can be reduced by providing an ion implantation adjusting film made of an insulating film having a smaller thickness than the conventional insulating sidewall spacer on the side surface of the gate structure. That is.

The thickness of the ion implantation adjusting film on the side surface of the gate structure is not less than 7.5 nm and not more than 50 nm,
Even with such an ion implantation adjustment film having a relatively small thickness, impurity ions are implanted into the semiconductor substrate using acceleration energy low enough not to damage the tunnel insulating film. Thereafter, by performing a heat treatment, particularly a thermal oxidation treatment in an oxidizing atmosphere, even if the tunnel insulating film is damaged, the damaged portion is recovered, and the implanted impurity ions are transferred to the lower channel of the gate structure. Spread to the area.

Further, in order for the ion implantation adjusting film to exert a masking effect from the impurity ions on the tunnel insulating film, it is desirable that the implantation of the impurity ions is also parallel to the side surface of the gate structure. It is preferable that the upper portion of the side surface of the gate structure is also perpendicular to the substrate surface. However, in practice, it is generally the case that the side surface of the gate structure is not perpendicular to the substrate surface due to process variations, and the portion of the ion implantation adjustment film on the side surface of the gate structure is also located on the substrate surface. It is unlikely to be perpendicular to it.

Therefore, the impurity ions incident on the ion implantation adjusting film are also scattered inside the ion implantation adjusting film and thus diffuse in the direction parallel to the substrate surface. It is necessary that the ions have at least a film thickness that does not reach the floating gate electrode.
Specifically, the film thickness of the ion implantation adjusting film needs to be a value which is at least twice the standard deviation ΔRp of the rest position of the impurity ions with respect to the insulating film constituting the ion implantation adjusting film.

On the other hand, unless the ion implantation adjusting film is provided on the active region where the source diffusion layer and the drain diffusion layer are formed, the acceleration energy of impurity ions is relatively low as in the conventional method of manufacturing a nonvolatile semiconductor memory device. Low energy is required.

That is, in order to introduce impurity ions into the inside of the semiconductor substrate, for example, even in the case of phosphorus (P) ions having the smallest mass among N-type impurity ions, acceleration energy of at least 5 keV is required. The value that is twice the standard deviation ΔRp is 7.5 nm.
Therefore, in order for the ion implantation adjusting film to be a mask of the tunnel insulating film, the thickness of the ion implantation adjusting film needs to be at least 7.5 nm.

Similarly, the impurity ions implanted into the semiconductor substrate are also scattered inside the semiconductor substrate and thus diffuse in the direction parallel to the substrate surface. For example, if the average range Rp of the implanted impurity ions is 50 nm, the standard deviation ΔRp when the acceleration energy is 40 keV is 16 nm in the case of phosphorus ions. In the case of arsenic (As) ions, the standard deviation ΔRp when the acceleration energy is 80 keV is 10 nm. In addition, antimony (S
b) In the case of ions, the acceleration energy is 120 keV
In this case, the standard deviation ΔRp is 8 nm.

Therefore, the thickness of the ion implantation adjusting film may be set to a value equal to or less than the sum of the diffusion in the direction parallel to the substrate surface and the thermal diffusion.

Further, in consideration of reducing the thermal history, which is the object of the present invention, the thickness of the ion implantation adjusting film may be equal to or less than the diffusion length of the implanted impurity ions in the direction parallel to the substrate surface. Required.

For example, in a nonvolatile semiconductor memory device using silicon (Si) for the semiconductor substrate, the concentration peak of impurity ions in the source diffusion layer and the drain diffusion layer is usually 1 × 10 ²⁰ cm ⁻³ or more. Since the impurity concentration is usually about 1 × 10 ¹⁷ cm ⁻³ , 1/1000 of the impurity ion concentration peak is defined as the diffusion length in the direction parallel to the substrate surface.

Since the value of the ratio between the impurity ion concentration peak and the impurity concentration of the semiconductor substrate is 1/1000, about three times the standard deviation ΔRp corresponds to a concentration of about 1/1000. For this reason, taking the most diffused phosphorus ion as an example, the standard deviation ΔRp at an acceleration energy of 40 keV at which the average range Rp becomes 50 nm is 16 nm, and the thickness of the ion implantation adjustment film is What is necessary is just to make it about 50 nm or less which is three times.

Further, even if the acceleration energy is reduced,
Heat treatment is preferably performed because the implanted impurity ions may damage the tunnel insulating film. Since the ion implantation adjusting film according to the present invention can easily transmit oxygen, the damaged portion of the tunnel insulating film can be recovered. As an example, when the ion implantation adjustment film is formed of an oxide film by a low pressure CVD method,
When the film thickness is reduced, the amount of transmission of oxygen increases. For example, when the temperature is 850 ° C. or higher, for example, in a dry oxidizing atmosphere of about 900 ° C., oxygen is applied to a case where an oxide film having a thickness of 50 nm In about one third of the time.

From these findings, in the diffusion step of the implanted impurity ions, if the tunnel insulating film is damaged, the diffusion of the impurity ions in the direction parallel to the substrate surface is oxidized in order to recover the damaged portion. This can be compensated for by performing enhanced diffusion by a thermal oxidation treatment using a neutral atmosphere. For example, in the case of phosphorus ions, even in a heat treatment at a temperature of 900 ° C., the phosphorus ions diffuse over a distance of about 50 nm in about 15 minutes. Since the heat is diffused in a shorter time than the heat treatment using the atmosphere, the heat history can be further reduced.

As described above, the present invention provides a source diffusion layer and a drain diffusion layer by providing an insulating ion implantation adjusting film having a thickness of 7.5 nm or more and 50 nm or less on at least the side surface of a floating gate electrode. Since the tunnel insulating film can be masked from impurity ions implanted in the layer, damage to the tunnel insulating film can be suppressed. In addition, the implanted impurity ions diffuse to the vicinity of the channel region due to scattering inside the semiconductor substrate. Further, by using a thermal oxidation method that is completed in a shorter time to recover the damaged portion of the tunnel insulating film, the thermal history of each component of the semiconductor device can be further reduced. In addition, since impurity ions can be implanted with low acceleration energy, deterioration of element isolation characteristics can be suppressed.

(First Embodiment) Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

FIGS. 1 (a) to 1 (c) and 2 (a),
FIG. 2B shows a cross-sectional configuration in a process order of the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

First, as shown in FIG. 1A, for example,
A P-type well 11 is formed on a semiconductor substrate 11 made of P-type silicon.
Then, an element isolation insulating film 12 such as a trench isolation is selectively formed. Thereafter, a tunnel insulating film 13 made of silicon oxide, a floating gate electrode 14 made of polysilicon, a capacitive insulating film 15 made of silicon oxide or silicon nitride, and a film thickness of, for example, about 300 nm are formed on the element formation region on the semiconductor substrate 11. A control gate electrode 16 made of polysilicon is sequentially formed, and a plurality of stacked gate structures 17 each formed of a tunnel insulating film 13, a floating gate electrode 14, a capacitor insulating film 15, and a control gate electrode 16 are selectively formed. I do.

Next, as shown in FIG. 1B, the film thickness is 10 nm to 50 nm over the entire surface including the respective gate structures 17 on the semiconductor substrate 11 by, for example, low pressure CVD.
A silicon oxide film is deposited on the silicon oxide film, and then anisotropic dry etching is performed on the silicon oxide film to form an ion implantation adjusting film made of silicon oxide on the side surface of each gate structure 17 on the gate length direction side. 18 are formed.

Subsequently, a source forming region of the active region located on the side of each gate structure 17 of the P-type well 11a and an ion implantation adjusting film on the side surface of each gate structure 17 on the side of the source forming region. A first resist pattern 51 is formed so as to expose 18. Thereafter, using the first resist pattern 51 and the exposed portions of the gate structure 17 and the ion implantation adjusting film 18 as a mask, the P-type well 11a is formed.
A first N-type implanted layer 20A is formed by injecting N-type impurity ions into the substrate. Here, arsenic (As) ions and phosphorus (P) ions are separately implanted under an implantation condition of an acceleration energy of about 10 keV and a dose of about 1 × 10 ¹⁵ cm ⁻² . As is known, arsenic ions reduce the contact resistance of the source electrode, and phosphorus ions increase the junction breakdown voltage.

Next, as shown in FIG. 1C, after removing the first resist pattern 51, the drain formation region of the active region of the P-type well 11a and the drain formation of each gate structure 17 are formed. A second resist pattern 52 is formed so as to expose the ion implantation adjusting film 18 on the side surface on the region side. Subsequently, N-type impurity ions and P-type impurity ions are sequentially implanted into the P-type well 11a using the second resist pattern 52 and the exposed portions of the gate structure 17 and the ion implantation adjusting film 18 as a mask.

Specifically, as the N-type impurity ions, for example, the acceleration energy is about 10 keV and the dose is 2 ×
A first implantation step using arsenic ions of about 10 ¹⁴ cm ⁻² , an acceleration energy of about 10 keV and a dose of 1 ×
A second N-type implanted layer 21A is formed by performing a second implantation step using phosphorus ions of about 10 ¹⁴ cm ^-2 . Subsequently, as P-type impurity ions, for example, the acceleration energy is about 10 keV and the dose is 4 × 10 ¹³ cm ^−2.
The P-type implanted layer 22A is formed by a third implantation step using a small amount of boron (B) ions. The order of the first to third implantation steps is arbitrary.

Although the ion implantation for the source formation region is performed before the ion implantation for the drain formation region, the ion implantation for the drain formation region may be performed before.

Next, as shown in FIG. 2A, after removing the second resist pattern 52, the first N-type implanted layer 2 is removed.
0A, the semiconductor substrate 11 on which the second N-type injection layer 21A and the P-type injection layer 22A are formed, for example, at a temperature of about 9
By performing thermal oxidation in a dry oxidation atmosphere at 00 ° C. for about 5 minutes, each impurity ion contained in the first N-type implantation layer 20A, the second N-type implantation layer 21A and the P-type implantation layer 22A increases. Spreads quickly. Due to this accelerated diffusion, the first
Each end of the N-type injection layer 20A and the second N-type injection layer 21A surely reaches the channel region located below the gate structure 17 in the P-type well 11a.
As a result, the first N-type injection layer 20A is
0B is formed, and a drain diffusion layer 21B is formed from the second N-type injection layer 21A. The P-type diffusion layer 22B formed from the P-type injection layer 22A has an impurity concentration of P
Since the impurity concentration is higher than the impurity concentration of the mold well 11a, the junction potential increases in the channel region of the PN junction surface between the P-type diffusion layer 22B and the drain diffusion layer 21B.
Hot electron generation efficiency is improved.

By the dry thermal oxidation at this time, the upper portion of the active region in the semiconductor substrate 11 and each gate structure 1 are formed.
7, a thermal oxide film 25 is formed.

Next, for example, as shown in FIG.
Each gate structure 1 is formed on a semiconductor substrate 11 by CVD.
7 is 100 nm to 200 n
m silicon oxide film
To perform anisotropic dry etching on
The ion implantation adjusting film is formed on the side surface of each gate structure 17.
Insulating sidewall made of silicon oxide through 18
The spacer 23 is formed. Next, the formed edge rhino
The wall spacer 23, the ion implantation adjusting film 18 and the gate
Using the gate structure 17 as a mask, the source diffusion layer 20B and the
The acceleration energy is about
The dose is 5 × 10 at 40 keV¹⁵cm ^-2Degree of injection strip
In this case, arsenic ions are implanted. Subsequently, the implanted arsenic
By performing heat treatment to the extent that ions are activated,
Exposed portions of source diffusion layer 20B and drain diffusion layer 21B
N in a minute⁺ A diffusion layer 24 is formed. After that, it is not shown
Formed and formed an interlayer insulating film on the semiconductor substrate 11
The source diffusion layer 20B or the drain diffusion layer 2
The contact electrically connected to 1B is formed. Further
And aluminum connected to the contact on the interlayer insulating film
A metal wiring made of a metal or the like is formed.

As described above, in the first embodiment, the side surfaces of the floating gate electrode 14 and the control gate electrode 16 are covered with the ion implantation adjusting film 18 having a thickness of about 10 nm to 50 nm, while the semiconductor is covered with the semiconductor. The active region of the substrate 11 is exposed. Therefore, even with a relatively small acceleration energy of about 10 keV, arsenic ions and phosphorus ions to be implanted reach a predetermined position on the semiconductor substrate 11, but hardly penetrate the ion implantation adjusting film 18. Damage to the tunnel insulating film 13 can be substantially prevented as in the conventional method.

As described above, since the ion implantation adjusting film 18 according to the first embodiment has a small thickness of about 10 nm to 50 nm unlike the conventional insulating side wall spacer, the arsenic implanted into the semiconductor substrate 11 is not required. The ions or phosphorus ions are scattered and diffused in a direction parallel to the substrate surface, and can reach the channel region below the gate structure 17 in the P-type well 11a.

The ion implantation adjusting film 18 has such a thickness that the impurity ions can reach the lower portion of the gate structure 17 in the active region by diffusion of the impurity ions into the semiconductor substrate 11 by scattering. Therefore, the acceleration energy at the time of ion implantation can be made relatively small, so that a decrease in the isolation characteristics of the element can be suppressed.

Further, since the ion implantation adjusting film 18 has a thickness through which oxygen is sufficiently transmitted even in a thermal oxidation treatment for about 5 minutes in a dry oxidation atmosphere at a temperature of about 900 ° C. Even if the tunnel insulating film 13 is damaged by a plurality of times of ion implantation, the damage can be recovered. In addition, since heat treatment in an oxidizing atmosphere is performed, the accelerated diffusion of arsenic ions or phosphorus ions in the semiconductor substrate 11 is further accelerated by oxygen, so that the ion implantation adjusting film 18 has a small thickness. Arsenic ions or phosphorus ions reach the channel region below the gate structure 17 in a shorter time.

Since the heat diffusion processing time can be shortened as compared with the conventional case, it is easy to mount the heat diffusion processing together with a microprocessor including a CMOS circuit or the like.

The first embodiment is different from the conventional example in a flash memory in which data is written by channel hot electrons.
This is a so-called asymmetric implantation in which the implantation ion species and the dose of the O.sub.B and the drain diffusion layer 21B are different from each other.

When asymmetric implantation is performed in the conventional example, the drain diffusion layer formed by implanting arsenic ions having a small dose and hardly diffusing requires high-temperature and long-time heat treatment. The source diffusion layer into which the easily diffused phosphorus ions are implanted diffuses even with a slight heat treatment, and as a result, the short channel effect is increased. Therefore, it is difficult to form the source diffusion layer by one heat treatment.

On the other hand, in the first embodiment, since the thickness of the ion implantation adjusting film 18 is small, the drain diffusion layer 2
Since the diffusion amount of 1B is small, the source diffusion layer 20B
Even if asymmetric implantation is performed on the source diffusion layer 20B and the drain diffusion layer 21B, the impurity concentration and the controllability of the junction surface for the source diffusion layer 20B and the drain diffusion layer 21B are improved.

Further, in the first embodiment, the source diffusion layer 20B and the drain diffusion layer 21B are formed using the ion implantation adjusting film 18 having a relatively small thickness as a mask, and thereafter, the thickness is about 100 to 200 nm. Using the insulating side wall spacers 23 as a mask, arsenic ions are accelerated at an acceleration energy of about 40 keV and 5 × 10 ¹⁵ c
The implantation is performed at a dose of about m ⁻² . Subsequently, a relatively weak heat treatment for activating the implanted arsenic ions is performed to form the N ⁺ diffusion layer 24, thereby reducing the resistance of the source diffusion layer 20B and the drain diffusion layer 21B. .

In the first embodiment, it is assumed that data is written in the nonvolatile semiconductor memory device by channel hot electrons. However, in the nonvolatile semiconductor memory device, data is written by Fowler-Nordheim (FN) current. Semiconductor memory device. In this case, the source diffusion layer 20B and the drain diffusion layer 21
Ion implantation for forming B differs from this embodiment in the ion species and dose.

The source diffusion layer 20B and the drain diffusion layer 21B do not necessarily have to be asymmetrically implanted.
So-called symmetrical and self-aligned implantation may be performed without using either the first resist pattern 51 or the second resist pattern 52 and using each gate structure 17 and each ion implantation adjustment film 18 as a mask. .

Although silicon oxide is used for the ion implantation adjusting film 18, silicon nitride may be used instead of silicon oxide.

(Modification of First Embodiment) Hereinafter, a modification of the first embodiment of the present invention will be described with reference to the drawings.

FIGS. 3A to 3C show cross-sectional structures in the order of steps of a method for manufacturing a nonvolatile semiconductor memory device according to a modification of the first embodiment. 3 (a) to 3
In (c), the same components as those shown in FIGS. 1A to 1C are denoted by the same reference numerals.

First, as shown in FIG. 3A, a P-type well 11a and an element isolation insulating film 12 are sequentially formed on a semiconductor substrate 11. Subsequently, a tunnel insulating film forming film 13 made of silicon oxide is formed on the entire surface of the semiconductor substrate 11.
A, Floating gate electrode forming film 14 made of polysilicon
A, a capacitor insulating film forming film 15A made of silicon oxide or silicon nitride, and a control gate electrode forming film 16A made of polysilicon having a thickness of about 70 nm are sequentially deposited. Further, the control gate electrode forming film 16 is formed by, for example, a CVD method.
A protective insulating film 26A made of silicon oxide or silicon nitride having a thickness of about 150 nm is deposited on A.

Next, as shown in FIG. 3B, a hard mask 26 having a gate structure pattern is formed from the protective insulating film 26A by selectively etching the protective insulating film 26A. Subsequently, anisotropic dry etching using the formed hard mask 26 is performed to remove the control gate electrode 1 from the control gate electrode formation film 16A.
6 from the capacitor insulating film forming film 15A to the capacitor insulating film 15;
From the floating gate electrode forming film 14A to the floating gate electrode 14
And a plurality of stacked gate structures each including a tunnel insulating film 13, a floating gate electrode 14, a capacitor insulating film 15, and a control gate electrode 16 by forming a tunnel insulating film 13 from the tunnel insulating film forming film 13A. 17 is formed.

Next, as shown in FIG. 3C, a silicon oxide film having a thickness of about 10 nm to 50 nm is deposited on the entire surface including the respective gate structures 17 on the semiconductor substrate 11 by the CVD method. Thereafter, by performing anisotropic dry etching on the silicon oxide film, an ion implantation adjusting film 18 made of silicon oxide is formed on the side surface on the gate length direction side of each gate structure 17.

Thereafter, as in the first embodiment, asymmetric implantation of impurity ions is performed into the source formation region and the drain formation region, and a thermal oxidation process is performed in a dry oxidation atmosphere to form the source diffusion layer and the drain. A diffusion layer is formed.

As described above, according to the present modification, even when the thickness of the control gate electrode 16 is smaller than that of the first embodiment, the protective insulating film 26 is provided on the control gate electrode 16. Therefore, the end surface of the capacitance insulating film 15 can be sufficiently covered with the ion implantation adjusting film 18,
Even if the anisotropic etching is over-etched when the ion implantation adjusting film 18 is formed, damage due to ion implantation into the capacitance insulating film 15 can be prevented.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIGS. 4 (a) to 4 (c) and FIG. 5 show cross-sectional structures in the order of steps of a method for manufacturing a nonvolatile semiconductor memory device according to the second embodiment of the present invention. Again, FIG.
4 (a) to 4 (c) and FIG. 5, the same components as those shown in FIGS. 1 (a) to 1 (c), 2 (a) and 2 (b) are the same. Signs are attached.

First, as shown in FIG. 4A, a P-type well 11a is formed on a semiconductor substrate 11 made of P-type silicon, and then an element isolation insulating film 12 such as a trench isolation is formed. Thereafter, a tunnel insulating film 13 made of silicon oxide, a floating gate electrode 14 made of polysilicon, a capacitive insulating film 15 made of silicon oxide or silicon nitride, and a film thickness of about 30 are formed on the element formation region on the semiconductor substrate 11.
A control gate electrode 16 made of 0 nm polysilicon is sequentially formed, and a plurality of stacked gate structures 17 each consisting of a tunnel insulating film 13, a floating gate electrode 14, a capacitor insulating film 15, and a control gate electrode 16 are selectively formed. Formed. Subsequently, over the entire surface including the respective gate structures 17 on the semiconductor substrate 11 by, for example, a low-pressure CVD method.
An ion implantation adjusting film forming film 18A made of silicon oxide having a thickness of about 10 nm to 50 nm is deposited.

Next, as shown in FIG. 4B, a first resist pattern 51 exposing a source forming region portion of the ion implantation adjusting film forming film 18A and a source forming region side portion of each gate structure 17 is formed. Form. Subsequently, anisotropic dry etching is performed on the ion implantation adjustment film forming film 18A using the formed first resist pattern 51 as a mask to form an ion implantation adjustment film on one side surface of the gate structure 17. Film 18A to ion implantation adjusting film 1
8 is formed. Thereafter, using the first resist pattern 51 and the exposed portions of the gate structure 17 and the ion implantation adjusting film 18 as a mask, N-type impurity ions are implanted into the P-type well 11a to form the first N-type implantation layer 20A. Form. Here, arsenic ions and phosphorus ions are separately implanted under the conditions of an acceleration energy of about 10 keV and a dose of about 1 × 10 ¹⁵ cm ⁻² . afterwards,
After removing the first resist pattern 51, the ion implantation adjusting film forming film 18A is subjected to, for example, wet etching with hydrofluoric acid to reduce the film thickness by about 2 nm to optimize the film.

Next, as shown in FIG. 4C, the drain formation region portion of the ion implantation adjustment film formation film 18A having the optimized film thickness and the drain formation region side portion of each gate structure 17 are exposed. A second resist pattern 52 is formed. Thereafter, anisotropic dry etching is performed on the ion implantation adjustment film forming film 18A using the second resist pattern 51 as a mask to form a thin film on the other side surface of the gate structure 17 from the ion implantation adjustment film forming film 18A. An ion implantation adjusting film 18a is formed. Subsequently, using the second resist pattern 52, the gate structure 17, and the exposed portion of the thinned ion implantation adjusting film 18a as a mask, N-type impurity ions and P-type impurities are added to the P-type well 11a.
Type impurity ions are sequentially implanted.

That is, as the N-type impurity ions, for example, the acceleration energy is about 10 keV and the dose is 2 × 1.
0 ¹⁴ cm ^-2 and the first implantation step using the degree of arsenic ions and a dose of about 10keV acceleration energy of 1 ×
A second N-type implantation layer 21A is formed by a second implantation step using phosphorus ions of about 10 ¹⁴ cm ^-2 . Then, P
For example, the acceleration energy is 10 k
A P-type implanted layer 22A is formed by a third implantation step using boron ions of about eV and a dose of about 4 × 10 ¹³ cm ⁻² . Here, the order of the first to third implantation steps is also arbitrary. Further, the order of ion implantation into the source formation region and ion implantation into the drain formation region is not limited.

Also, a thin ion implantation adjusting film 1 which becomes a part of a mask when implanting ions into the drain formation region.
The wet etching for obtaining 8a is not necessarily required, but is effective when it is desired to change the thickness and the value of the ion implantation adjusting film 18 which is a part of the mask at the time of ion implantation into the source forming region. . If the ion implantation into the drain formation region is performed first, the thickness of the ion implantation adjustment film 18 on the source formation region side is made smaller than the thickness of the thinned ion implantation adjustment film 18a on the drain formation region side. be able to.

Next, as shown in FIG. 5, after removing the second resist pattern 52, the first N-type implanted layer 20A,
The temperature of the semiconductor substrate 11 on which the second N-type injection layer 21A and the P-type injection layer 22A are formed is, for example, about 900 ° C.
By performing thermal oxidation in a dry oxidation atmosphere for about 5 minutes, the first N-type injection layer 20A and the second N-type
Each impurity ion contained in the A and P-type implanted layers 22A is diffused at an enhanced rate. Due to this enhanced diffusion, each end of the first N-type injection layer 20A and the second N-type injection layer 21A
It surely reaches the channel region located at the lower part of each gate structure 17 in the mold well 11a. As a result, a source diffusion layer 20B is formed from the first N-type injection layer 20A, and a drain diffusion layer 21B is formed from the second N-type injection layer 21A. Further, the P-type diffusion layer 22B formed from the P-type injection layer 22A has an impurity concentration higher than that of the P-type well 11a.
Since the junction potential increases in the channel region of the PN junction surface between 2B and the drain diffusion layer 21B, the generation efficiency of hot electrons is improved. By the dry thermal oxidation at this time, a thermal oxide film 25 is formed on the active region in the semiconductor substrate 11 and on each gate structure 17.

Thereafter, similarly to the first embodiment, ion implantation adjusting films 18 and 18 are formed on the side surfaces of each gate structure 17.
An insulating sidewall spacer made of silicon oxide is formed through the gate electrode 17a, and the source insulating layer 20B and the drain diffusion layer 21B are formed using the insulating sidewall spacer, the ion implantation adjusting films 18, 18a, and the gate structure 17 as a mask. Is implanted with arsenic ions. Thereafter, heat treatment is performed to activate the implanted arsenic ions, thereby forming an N ⁺ diffusion layer in the exposed portions of the source diffusion layer 20B and the drain diffusion layer 21B.

As described above, in the second embodiment, when performing anisotropic etching on the ion implantation adjusting film 18, the region such as the element isolation insulating film 12 is masked by the resist film. Since the isolation insulating film 12 is not exposed to the etchant, the number of masking steps is the same as in the first embodiment, but the element isolation characteristics do not deteriorate.

In the second embodiment, FIG.
As shown in FIG. 4B and FIG. 4C, anisotropic etching was performed on the ion implantation adjustment film forming film 18A in both the source forming region side and the drain forming region side.
The anisotropic etching may be performed only on one of the source forming region side and the drain forming region side.

Although silicon oxide is used for the ion implantation adjusting film 18, silicon nitride may be used instead of silicon oxide.

(Modification of Second Embodiment) Hereinafter, a modification of the second embodiment of the present invention will be described with reference to the drawings.

FIGS. 6A to 6C show cross-sectional structures in the order of steps of a method for manufacturing a nonvolatile semiconductor memory device according to a modification of the second embodiment. Here, focusing on one gate structure and an ion implantation adjusting film, an outline of a manufacturing method thereof will be described. 6 (a) to 6 (c), the same components as those shown in FIGS. 4 (a) to 4 (c) are denoted by the same reference numerals.

The present modification is characterized in that the ion implantation adjusting film has a laminated structure of silicon oxide and silicon nitride sequentially formed from the gate structure side.

First, as shown in FIG. 6A, a P-type well 11a is formed on a semiconductor substrate 11 made of P-type silicon, and a tunnel insulating film 13, a floating gate electrode 14, and a P-type well 11a are formed on the P-type well 11a. A gate structure 17 composed of the capacitance insulating film 15 and the control gate electrode 16 is selectively formed.

Next, as shown in FIG.
By a method D, a first adjustment film 31 made of silicon oxide having a thickness of about 5 nm and a thickness of about 15 n are formed on the entire surface including the upper surface and side surfaces of the gate structure 17 on the semiconductor substrate 11.
The second adjustment film 32 made of silicon nitride of m is sequentially deposited to form an ion adjustment film forming film 18A made of the first adjustment film 31 and the second adjustment film 32.

Next, as shown in FIG. 6C, anisotropic dry etching is performed on the ion implantation adjustment film forming film 18A to form an ion implantation adjustment film on the side surface of the gate structure 17. The ion implantation adjusting film 18 is formed from the film 18A. At this time, similarly to the second embodiment, the ion implantation adjusting film 18 may be formed by separately etching the source forming region side and the drain forming region side. Thereafter, N-type impurity ions are implanted into the P-type well 11a, and thereafter, the source diffusion layer 20B and the drain diffusion layer are increased by performing thermal diffusion at a temperature of about 850 ° C. for about 20 minutes. 21B is formed. Here, the thermal oxide film formed on the semiconductor substrate 11 and the gate structure 17 is omitted.

As described above, according to the present modification, the ion implantation adjusting film 18 is constituted by the first adjusting film 31 made of silicon oxide and the second adjusting film 32 made of silicon nitride on the side surface of the gate structure 17. Therefore, various effects as described below can be obtained. (1) Since silicon nitride has a denser film quality than silicon oxide, the permeability of implanted ions is low. As a result, the thickness of the ion implantation adjusting film 18 can be made smaller, so that the implanted ions can easily reach the lower side of the side end of the floating gate electrode 14, and the heat treatment time for activating the implanted ions can be reduced. It can be shorter. (2) As shown in FIG. 6C, the ion implantation adjusting film 18
Has a two-layer structure, so that the lower end of the first ion adjustment film 31 has an L-shaped cross section. As a result, the first adjustment film 31 made of silicon oxide is exposed from the lower end of the second adjustment film 32 made of silicon nitride. Accordingly, oxygen during the thermal oxidation process can enter the tunnel insulating film 13 from the exposed portion of the first adjustment film 31, so that the thickness of the side end portion of the tunnel insulating film 13 tends to increase. on the other hand,
Since the side end of the capacitance insulating film 15 is covered with the ion implantation adjusting film 18 containing silicon nitride, the capacitance insulating film 1
The side end of 5 does not enlarge. Therefore, it is possible to suppress a decrease in the value of the capacitance coupling ratio of the gate structure 17. Here, the capacitance coupling ratio refers to the floating gate electrode 1
4 and the ratio of the capacitance between the control gate electrode 16 to the total capacitance. The total capacitance means the capacitance between the floating gate electrode 14 and the control gate electrode 16, and the floating gate electrode 14 and the semiconductor substrate 11 (the P-type well 11).
a, the sum of the capacitance between the source diffusion layer 20B and the drain diffusion layer 21B). (3) The second adjustment film 32 made of silicon nitride having a larger stress during film formation than silicon oxide is formed on the gate structure 1.
7 without being directly provided on the side wall of
Since the second adjustment film 32 is provided via the adjustment film 31, the stress applied to the gate structure 17 by the second adjustment film 32 is reduced. Further, since the first adjustment film enters between the lower end of the second adjustment film 32 and the semiconductor substrate 11, the stress of the second adjustment film 32 on the gate structure 17 is further reduced.

Although the silicon oxide formed by the low-pressure CVD method is used for the first adjustment film 31, a thermal oxidation method may be used.

The first adjustment film 3 made of silicon oxide
The ion implantation adjustment film 18 composed of the first and second adjustment films 32 made of silicon nitride can be applied to the first embodiment and its modifications.

In the first and second embodiments and the modifications thereof described above, the stack type gate is used for the gate structure 17. However, the present invention is not limited to this, and the control gate electrode 16 and the floating gate electrode 14 may be used. Is on the semiconductor substrate 1
1 are arranged side by side with a tunnel insulating film 13 interposed therebetween, and sandwich a capacitive insulating film 15 between adjacent side surfaces.
A so-called split type gate structure may be used.

The low pressure CVD is applied to the ion implantation adjusting film 18.
Although silicon oxide by the method is used, a thermal oxidation method may be used. However, since silicon oxide formed by the thermal oxidation method has a dense film quality, oxygen permeability is slightly reduced.

[0107]

According to the method of manufacturing a nonvolatile semiconductor memory device of the present invention, after forming a gate structure having a tunnel insulating film, a source diffusion layer and a drain diffusion layer are formed by ion implantation and subsequent heat treatment. In this case, the heat history exerted on each component can be reduced. Moreover,
Since damage to the tunnel insulating film due to implantation of impurity ions using the gate structure as a mask can be suppressed and recovered, the reliability of data retention characteristics and the like can be improved.

[Brief description of the drawings]

FIGS. 1A to 1C are cross-sectional views in the order of steps showing a method for manufacturing a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIGS. 2A and 2B are cross-sectional views illustrating a method of manufacturing the nonvolatile semiconductor memory device according to the first embodiment of the present invention in the order of steps.

FIGS. 3A to 3C are cross-sectional views in a process order illustrating a method for manufacturing a nonvolatile semiconductor memory device according to a modification of the first embodiment of the present invention.

FIGS. 4A to 4C are cross-sectional views in the order of steps showing a method for manufacturing a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

FIG. 5 is a sectional view illustrating a method of manufacturing a nonvolatile semiconductor memory device according to a second embodiment of the present invention in the order of steps.

FIGS. 6A to 6C are schematic cross-sectional views illustrating a method of manufacturing a nonvolatile semiconductor memory device according to a modification of the second embodiment;

FIGS. 7A to 7C are cross-sectional views in the order of steps showing a method for manufacturing a conventional nonvolatile semiconductor memory device.

FIG. 8 is a cross-sectional view illustrating a method of manufacturing a conventional nonvolatile semiconductor memory device in the order of steps.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 Semiconductor substrate 11a P-type well 12 Element isolation insulating film 13 Tunnel insulating film 13A Tunnel insulating film forming film 14 Floating gate electrode 14A Floating gate electrode forming film 15 Capacitive insulating film 15A Capacitive insulating film forming film 16 Control gate electrode 16A Control gate electrode Forming film 17 Gate structure 18 Ion implantation adjusting film 18A Ion implantation adjusting film forming film 18a Thinned ion implantation adjusting film 20A First N-type implantation layer 20B Source diffusion layer 21A Second N-type implantation layer 21B Drain diffusion Layer 22A P-type injection layer 22B P-type diffusion layer 23 Insulating sidewall spacer 24 N ⁺ diffusion layer 25 Thermal oxide film 26A Protective insulating film 26 Hard mask 31 First adjustment film 32 Second adjustment film 51 First resist pattern 52 Second resist pattern

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Takahiko Hashizume 1006 Kadoma, Kazuma, Osaka Matsushita Electric Industrial Co., Ltd. F-term (reference) 5F083 EP02 EP23 EP24 EP41 EP60 EP64 ER03 ER09 JA36 NA01 PR10 PR21 PR34 PR36 5F101 BA01 BA23 BB04 BB05 BC02 BC11 BD09 BD36 BH02 BH08 BH09

Claims (17)

[Claims] 1. A semiconductor device comprising: a semiconductor substrate; a tunnel insulating film in contact with the semiconductor substrate; a floating gate electrode in contact with the tunnel insulating film; and a control gate electrode facing the floating gate electrode via a capacitor insulating film. A second step of forming an ion implantation adjusting film made of an insulating film in contact with the floating gate electrode on at least a side surface of the floating gate electrode; A third step of implanting impurity ions into the active region on the side of the gate structure in the semiconductor substrate using the ion implantation adjusting film as a mask; And a fourth step of thermally diffusing the ions, wherein in the second step, the ion implantation adjusting film is provided with the impurity ions in the tunnel insulating film. And a diffusion layer that prevents diffusion of the impurity ions into the semiconductor substrate and allows the impurity ions to reach a lower portion of a side end of the floating gate electrode in the active region. A method for manufacturing a nonvolatile semiconductor memory device, wherein the thickness is set to a thickness. 2. The method according to claim 1, wherein in the fourth step, the heat treatment is performed in an oxidizing atmosphere. 3. The ion implantation adjusting film has a thickness of 50 nm.
3. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein: 4. The ion implantation adjusting film is made of a material having oxygen permeability. In the fourth step, an upper portion of the active region is oxidized, and the floating is performed by oxygen transmitted through the ion implantation adjusting film. 4. The method according to claim 2, further comprising the step of oxidizing a part of the gate electrode. 5. The method according to claim 4, wherein the heat treatment is performed at 850.
The method according to any one of claims 2 to 4, wherein the method is performed at a temperature of not less than ° C. 6. The second step includes: depositing the ion implantation adjustment film over the entire surface including the gate structure on the semiconductor substrate; and anisotropically with respect to the deposited ion implantation adjustment film. The method of manufacturing a nonvolatile semiconductor memory device according to claim 1, further comprising: exposing the active region by performing etching. 7. The second step includes: forming the ion implantation adjustment film over the entire surface including the gate structure on the semiconductor substrate by a thermal oxidation method; Exposing the upper surface of the active region by performing anisotropic etching by using an etching method. 6. The method of manufacturing a nonvolatile semiconductor memory device according to claim 1, further comprising: . 8. The method according to claim 1, wherein the third step is a first ion implantation step performed on one side of the gate structure in the active region, and the other side of the gate structure in the active region. 8. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, further comprising: a second ion implantation step performed on said non-volatile semiconductor memory device. 9. The first ion implantation step or the second ion implantation step.
9. The method of manufacturing a nonvolatile semiconductor memory device according to claim 8, wherein said ion implantation step includes a step of implanting at least two types of impurity ions having a conductivity type opposite to a conductivity type of said semiconductor substrate. . 10. The method according to claim 1, wherein the first ion implantation step or the second ion implantation step includes the step of forming an impurity ion having the same conductivity type as the conductivity type of the semiconductor substrate and a conductivity type opposite to the conductivity type of the semiconductor substrate. 9. The method according to claim 8, further comprising a step of implanting impurity ions. 11. The second step comprises: masking one side portion of the gate structure in the ion implantation adjustment film and exposing the other side portion; 11. The method of manufacturing a nonvolatile semiconductor memory device according to claim 1, further comprising: performing anisotropic etching on the exposed other side portion. 12. The method according to claim 11, wherein the second step includes, after the anisotropic etching, adjusting a thickness of the ion implantation adjustment film by etching.
3. The method for manufacturing a nonvolatile semiconductor memory device according to 1. 13. The nonvolatile memory according to claim 1, wherein said first step includes a step of forming a protective insulating film on said control gate electrode. A method for manufacturing a semiconductor storage device. 14. A fifth step of forming an insulating sidewall spacer on the side surface of the gate structure via the ion implantation adjusting film after the fourth step; A step of implanting impurity ions of a conductivity type opposite to the conductivity type of the semiconductor substrate using the adjustment film and the insulating sidewall spacers as a mask.
3. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1. 15. The method according to claim 1, wherein in the second step, the ion implantation adjustment film is formed of silicon nitride. Method. 16. The second step, comprising: forming a first adjustment film made of silicon oxide; and forming a second adjustment film made of silicon nitride on the first adjustment film, The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein an ion implantation adjusting film is formed. 17. The method according to claim 16, wherein the second step includes a step of removing a lower end of the second adjustment film after forming the second adjustment film.
13. The method for manufacturing a nonvolatile semiconductor memory device according to item 10.