JPH10116988A - Semiconductor device and fabrication thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure a reliable transistor operation even for a very long gate length by forming a gate electrode through a gate insulation layer on a channel region between source and drain regions and forming an insulator layer between source and channel regions and between drain and channel regions. SOLUTION: An insulation barrier layer 17 is formed between a source region 14 and a drain region 15 abutting on a channel region 11a. The insulation barrier layer 17 blocks formation of a current path in the vicinity of the deepest part in source and drain regions upon occurrence of short channel effect. Consequently, electrical conduction in the vicinity of the deepest part in source and drain regions is retarded significantly and short channel effect is suppressed. According to the arrangement, leak current of transistor is controlled without increasing the impurity concentration of channel and short channel effect is suppressed while preventing deterioration of breakdown strength thus ensuring normal transistor operation while breaking through the limit of fine patterning.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a MOSFET (Meta
l Oxide Semiconductor Field Effect Transistor),
EPROM (Erasable and Programmable Read Only Me)
mory), EEPROM (electrically erasable progra)
mmable read only memory) and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 13 is a schematic view showing the structure of a conventional general MOSFET. General MOSF as shown
ET is provided with a gate electrode 3 via a gate insulating film 2 formed on the surface of a silicon substrate 1, and has a source region 4 and a drain region 5 on both sides of a channel region 6 of the substrate 1 immediately below the gate electrode 3. Is arranged.

Conventionally, the miniaturization of semiconductor devices has been advanced, and in the most common MOSFET as a MIS type semiconductor device, particularly, the gate electrode 3
Of the width (gate length L) is being advanced. However, when the gate length L is reduced to about 50 nm or less as in the relationship between the gate length and the threshold voltage shown in FIG. 14, the short channel effect becomes remarkable, and it becomes difficult to control the threshold voltage. Are known. Therefore, in order to suppress the short channel effect, it is necessary to increase the channel impurity concentration.

For example, when the gate length is reduced to 50 nm or less, in order to suppress the short channel effect, the relationship between the gate length and the channel impurity concentration required for suppressing the short channel shown in FIG. , The impurity concentration of the channel must be increased to about 1 × 10 ¹⁹ cm ⁻³ or more. However, when the impurity concentration of the channel is also increased to about 7 × 10 ¹⁸ cm ⁻³ or more, P
Tunnel current (leakage current) between N junctions cannot be ignored. As a result, there is a problem that the breakdown voltage between the drain and the substrate is deteriorated, and the transistor operation becomes impossible.

[0005]

As described above, the conventional M
In the OSFET, particularly, the channel length has been miniaturized. However, as the channel length is reduced, a short channel effect occurs. In order to suppress the short channel effect, it is necessary to increase the channel impurity concentration.
However, the range in which channel impurities can be increased is limited in terms of suppressing breakdown voltage degradation, and cannot be increased beyond a certain value.

That is, a MOSFET having a conventional structure
Since there is a physical limit such as a short channel effect and a decrease in breakdown voltage, there is a limit in performing miniaturization. Therefore, an object of the present invention is to provide a semiconductor device capable of normal transistor operation even with a very short gate length, and a method of manufacturing the same.

[0007]

In order to achieve the above object, in a semiconductor device according to the present invention, a source region and a drain region formed in a semiconductor substrate and a channel region between the source region and the drain region are provided. A gate electrode formed thereon with a gate insulating film interposed therebetween, and an insulator layer formed between the source region and the channel region and between the drain region and the channel region.

In the method of manufacturing a semiconductor device according to the present invention for manufacturing the semiconductor device, a step of forming a gate electrode on a semiconductor substrate via a gate insulating film;
Forming a side wall insulating film on the side surface of the gate electrode, selectively removing the gate insulating film using the gate electrode and the side wall insulating film as a mask, exposing a surface of the semiconductor substrate; A step of isotropically etching the surface of the semiconductor substrate to form a recess, a step of forming an insulator layer on the surface of the recess, and a step of selectively removing the insulator layer using the sidewall insulating film as a mask. Forming a diffusion layer by selectively growing a semiconductor layer in the concave portion.

A step of forming a gate electrode on the semiconductor substrate via a gate insulating film, a step of selectively removing the gate insulating film using the gate electrode as a mask, and exposing a surface of the semiconductor substrate; Anisotropically etching the exposed surface of the semiconductor substrate to form a recess for forming a diffusion layer; forming an insulator layer on the surface of the recess; and forming a recess on the bottom of the recess. A step of removing the insulator layer; and a step of forming a diffusion layer by selectively growing a semiconductor layer in the recess.

As described above, according to the semiconductor device and the method of manufacturing the same of the present invention, when the gate length of the gate electrode is very short, the leakage current of the transistor is controlled without increasing the channel impurity concentration, and the breakdown voltage is reduced. Can be suppressed and the short channel effect can be suppressed. Further, while having the above-described effects, a sufficient ON current can be obtained, and normal transistor operation can be performed.
That is, the limit of miniaturization due to the increase in the channel impurity concentration can be overcome.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings. FIG. 1 is a schematic sectional view of a MOSFET according to the present invention.

This MOSFET has a gate insulating film 12 formed in a P-type well region 22 on the surface of an N-type semiconductor silicon substrate 11, a gate electrode 13 formed on the substrate 11 through the gate insulating film 12, Source region 1 formed on the left and right of channel region 11a immediately below electrode 13
4 and a drain region 15, and a gate sidewall insulating film 16 formed on the side surface of the gate electrode 13. Further, the substrate 11
A thin insulating barrier layer 17 corresponding to the width of the gate sidewall insulating film 16 is provided at each portion where the channel region 11a and the source region 14 and the drain region 15 are in contact with each other.

According to the N-type MOSFET having the above structure,
An insulating barrier layer 17 is formed between the source region 14 and the drain region 15 that are in contact with the channel region 11a. Thus, when the short channel effect occurs, the formation of the current path formed near the deepest part of the source and drain regions is prevented by the insulating barrier layer 17. Therefore, electric conduction in the vicinity of the deepest portions of the source and drain regions is significantly inhibited, so that the short channel effect can be suppressed.

On the other hand, immediately below the gate electrode 13, although the insulating barrier layer 17 is present, the channel length is short, and the insulating barrier layer is formed to be thin enough to cause a resonance tunnel effect. A sufficient on-current can be obtained between the drain regions.

Therefore, even when the gate length of the gate electrode 13 is very short, for example, 50 nm or less,
By controlling the leakage current of the transistor, it is possible to suppress the occurrence of the short channel effect while suppressing the deterioration of the breakdown voltage. Further, a sufficient on-current can be obtained while having the above effects.

Next, a manufacturing method for manufacturing the MOSFET having the above structure will be described with reference to the drawings. First, a first embodiment of a method of manufacturing a semiconductor device according to the present invention will be described below with reference to process schematic diagrams of FIGS.

First, as shown in FIG. 2, an L-type semiconductor silicon substrate (hereinafter, simply referred to as a substrate) 11 has
OCOS (Local Oxidation of Silicon) method or ST
The field oxide film 21 is formed by an I (Shallow Trench Isolation) method. In this structure, the field oxide film 21 has a thickness of 150 nm to 300
The active element portion is formed with a thickness of about 20 nm or less.

Subsequently, as shown in FIG. 3, boron ions, which are P-type impurities, are deposited on the entire surface of the substrate 11 at an acceleration energy of 35%.
Ion implantation at 0 KeV and a dose of 2 × 10 ¹³ cm ⁻² ,
A P-type well region 22 is formed. Next, boron ions, which are P-type impurities, are implanted into the channel formation region of the MOSFET at an acceleration energy of 60 KeV and a dose of 1 × 10 ¹³ c.
By ion implantation at m ^-2 , a channel region 11a for controlling the threshold value of the MOSFET is formed.

Subsequently, as shown in FIG. 4, after the field oxide film 21 of the active element portion is selectively removed, thermal oxidation or LP-CVD (Low Pressure-Chemical Vapor Depo) is performed.
The gate insulating film 12 having a thickness of about 10 nm to 30 nm is formed by the (sition) method. As the gate insulating film 12, a thermal oxide film, a nitride film, or a nitrided oxide film or the like is used if the reliability of the withstand voltage is further improved.
Next, a film thickness of 30 nm to 100 nm is formed on the entire surface of the gate insulating film 12.
An N-type doped polysilicon film 13a of about nm is formed. Next, on the surface of the polysilicon film 13a, a high melting point metal film or a high melting point metal silicide film 13b made of, for example, tungsten or tungsten silicide is formed with a thickness of about 30 nm to 60 nm in order to reduce the resistance of the gate electrode. Side gate structure or polysilicon-
A stacked structure of tungsten is used. If necessary, the refractory metal film 13b has a thickness of 30
The SiN film 23 having a thickness of about 60 nm to 60 nm may be formed. Next, a resist mask (not shown) is formed, and using this as a mask, the SiN film 23, the refractory metal 13b, and the polysilicon film 13a are anisotropically etched by RIE to form the gate electrode 13. The gate length of the gate electrode formed here is 50 nm or less.

Incidentally, in order to pattern the gate electrode with a thickness of 50 nm or less, an electron beam exposure method is employed in forming a resist mask. Also, by employing an RIE method using a halogen-based reaction gas for etching, the gate electrode 13 has a high selectivity with respect to the gate insulating film 12 and has a high selectivity.
Can be etched.

Subsequently, as shown in FIG. 5, a silicon nitride film or a silicon oxide film having a thickness of about 10 nm to 30 nm is formed on the entire surface of the substrate 11 by LP-CVD or the like. Next, the gate electrode 13 and SiN are etched by anisotropically etching the formed silicon nitride film and the like by RIE.
A gate sidewall insulating film 16 is formed along the side surface of the film 23.

Subsequently, as shown in FIG.
2 is selectively removed to expose the surface of the silicon substrate 11. Note that when the gate insulating film 12 is formed by a thermal oxidation method, the gate insulating film 12 can be removed by wet etching using a hydrofluoric acid-based etchant. After removing the gate insulating film 12, the surface of the substrate 11 is isotropically etched to form a concave portion 24 for forming each of the source and drain regions. The etching amount in this etching is, for example, approximately equal to the width of the gate side wall insulating film 16. That is, in the present embodiment,
Since the gate sidewall insulating film 16 is formed to have a thickness of about 10 nm to 30 nm, the depth of the recess 24 is about 10 nm to 30 nm. This also allows the substrate 11 to be etched to just below the vicinity of the boundary between the gate electrode 13 and the gate sidewall insulating film 16. The substrate 11 is isotropically etched by, for example, using a chemical dry etching method using a fluorine atom and an oxygen atom generated from a mixed gas of CF ₄ and O ₂ by a discharge in a microwave resonator. Is possible. In the case of this etching method, the crystal can be isotropically etched without disorder of the crystal on the surface of the concave portion 24.

Subsequently, as shown in FIG.
An insulating barrier layer 17 having a thickness of about 0.5 nm to 2 nm is formed on the surface of the concave portion 24. This insulating barrier layer 17
Is a thermal oxide film formed in an oxygen atmosphere at about 1000 degrees Celsius, for example. In addition, a nitride film, a nitrided oxide film, or the like can be used as the insulating barrier layer.
Next, the insulating barrier layer 17 immediately below the portions to be the source and drain regions is selectively removed by, for example, reactive ion etching. In this case, the gate sidewall insulating film 16 functions as a mask material, and the insulating barrier layer 17 formed immediately below the gate sidewall insulating film 16 remains without being etched. Next, by selectively filling the recesses 24 by an epitaxial method, respectively, the source region 14 is formed.
And a drain region 15 are formed.

When the solid phase epitaxial method is used, the source region 14 and the drain region 15 are simultaneously doped with impurities when the epitaxial layer is selectively grown. Therefore, the concentration of impurities in the source region 14 and the drain region 15 formed can be controlled by the concentration of gas used in the epitaxial method and the like.

Subsequent steps are the same as those of a normal MOSFET manufacturing process. For example, various steps such as lamination of an interlayer insulating film, opening of a contact hole in the interlayer insulating film, and formation of a metal wiring by a metallization method are performed. .

Through the above steps, the channel region 11a
Contact with the source region 14 and the drain region 15 respectively.
N-type MOSF with an insulating barrier layer 17 formed between
ET is completed.

A case in which a salicide layer is formed in order to reduce the contact resistance in addition to the above steps will be described with reference to FIG. After the process described with reference to FIG. 7, as shown in FIG.
Further, a side wall insulating film 25 is formed on the surface with a silicon nitride film or the like. The side wall insulating film 25 is provided for forming a salicide layer with a sufficient margin with respect to the gate electrode 13 in consideration of the withstand voltage. Therefore, if the region where the salicide layer is formed has a sufficient margin with respect to the gate electrode 13 in advance, the side wall insulating film 2
5 need not be formed. Next, a resist mask (not shown) is formed, and the resist mask, the gate electrode 13, the gate sidewall insulating film 16, the sidewall insulating film 25, and the like are used as masks.
Diffusion layers 26 and 27 are formed by ion implantation of arsenic or phosphorus. Next, a high melting point metal such as Ti and TiN or a high melting point metal silicide is formed by a sputtering method.
Next, RTA (Rapid Thermal Anneal) is performed in a nitrogen atmosphere to remove unreacted Ti, TiN, and the like, and form silicide layers 28 on the surfaces of the source region 14 and the drain region 15, respectively. By performing the above steps in addition to the steps up to FIG. 7, the source region 14, the drain region 1
The contact 5 can be reduced in resistance.

In the present invention, a thin insulating barrier layer is formed between the source region and the drain region, which are in contact with the channel region of the MOSFET. This prevents the formation of a current path near the deepest portions of the source region and the drain region formed when the short channel effect occurs,
Electric conduction in the vicinity of the deepest portions of the source region and the drain region is significantly inhibited, and the short channel effect can be suppressed.

On the other hand, although the insulating barrier layer 17 exists immediately below the gate electrode, the channel length is formed short, and the insulating barrier layer is formed to have a thickness enough to cause a resonance tunnel effect. It is possible to sufficiently extract ON current.

Therefore, even when the gate length of the gate electrode 13 is formed to be very short, for example, 50 nm or less, without increasing the channel impurity concentration,
The short channel effect can be suppressed while controlling the leakage current of the transistor and suppressing the deterioration of the breakdown voltage. Further, while having the above-described effects, a sufficient ON current can be obtained, and normal transistor operation can be performed. That is, the limit of miniaturization due to the increase in the channel impurity concentration can be overcome.

In the first embodiment of the present invention, the insulating barrier layer 17 is formed by leaving only the thermal oxide film immediately below the gate electrode using the gate sidewall insulating film 16 as an etching mask. The case where it does is explained. However, the present invention is not limited to this. For example, it is also possible to form an insulating barrier layer immediately below the gate electrode between the source region and the drain region that are in contact with the channel region without forming the gate sidewall insulating film.

FIGS. 9 and 10 show a manufacturing method in this case as a second embodiment of the semiconductor device manufacturing method of the present invention.
This will be described below with reference to FIG. In the second embodiment, since the steps up to the step shown in FIG. 4 of the first embodiment are the same, the description is omitted. The same components as those of the first embodiment are denoted by the same reference numerals. Unless otherwise specified, the manufacturing method, the film thicknesses, and the like are the same as in the first embodiment.

That is, in the step shown in FIG. 4, following the state up to the etching of the gate electrode, the gate insulating film 12 is removed by wet etching to expose the surface of the substrate 11 as shown in FIG. Next, the recess 24 is formed by anisotropically etching the surface of the silicon substrate 11 by reactive etching. The depth of the convex portion 24 is 10 nm to 30 nm similarly to the first embodiment.
Degree. Next, a thermal oxide film 31 having a thickness of about 0.5 nm to 2 nm is formed on the surface of the concave portion 24 by a thermal oxidation method.

Subsequently, as shown in FIG. 10, only the thermal oxide film 31 on the flat portion (bottom surface) of the concave portion 24 is removed by reactive ion etching. Next, similarly to the first embodiment, an epitaxial layer is selectively grown in the concave portion 24 by an epitaxial method to form the source region 14 and the drain region 15. Thereby, the source region 14
Further, an N-type MOSFET in which the insulating barrier layer 17 is formed between the drain region 15 and the channel region 11a can be manufactured. Of course, in the subsequent steps, a step of forming a salicide layer can be additionally performed as described in the first embodiment. The manufacturing process at that time is the same as that of the first embodiment, and the description thereof is omitted.

Next, a third embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. This third embodiment is a modification of the first embodiment of the present invention shown in FIG. That is, in the third embodiment, the insulating barrier layer 17 is formed to be thinnest at a portion in contact with the channel region 11a and gradually thicker along the depth direction of the channel region 11a. Thereby, the effect of suppressing the short channel effect in the vicinity of the deepest portions of the source region 14 and the drain region 15 can be further enhanced.

The present invention can be applied to, for example, an EPROM or an EEPROM having a charge storage layer. This will be described as a fourth embodiment with reference to FIG. FIG. 12 is a schematic view of an EEPROM of the present invention having a floating gate electrode as a charge storage layer. The N-type source region 72 and the drain region 73
It is formed on the surface of the semiconductor substrate 71 of the mold. A floating gate electrode 75 is formed above a channel region between the source region 72 and the drain region 73 via a gate insulating film (tunnel insulating film) 74. Further, a control electrode 76 is formed on the floating gate electrode 75 via the intermediate insulating film 77. An insulating barrier layer 78 is formed between the source region 72 and the channel region and between the drain region and the channel region.

In a write operation (programming) in the above-described memory cell, a low voltage of, for example, about 0 V is applied to the source region 72 and the semiconductor substrate 71,
For example, a high voltage of about 12 V is applied to the control electrode 76 and the drain region 73. At this time, an ON current flows between the source and drain regions, hot electrons are generated around the drain region, injected into the floating gate electrode through the gate insulating film 74, and the threshold value of the transistor increases.

On the other hand, when erasing data, a high voltage is applied to the source region and a low voltage is applied to the control gate electrode. The drain electrode 73 is in a floating state. In this case, a tunnel current flows through the gate insulating film 74, charges are extracted from the floating gate electrode 75, and the threshold value of the transistor decreases.

The memory cell configured as described above can of course be applied to a memory cell array such as a NOR type or a NAND type. Even in the memory cell having the floating gate electrode described in the fourth embodiment, the leakage current of the transistor is controlled without increasing the channel impurity concentration, and the short channel effect is suppressed while suppressing the deterioration of the breakdown voltage. can do. Such an effect is particularly effective for a memory element that uses the on-state current when programming the element.

The present invention is not limited to the N-type MOSFET,
The same can be applied to a P-type MOSFET. In addition, as long as the gist of the present invention is not changed,
Needless to say, various modifications can be made.

[0041]

According to the present invention, when the gate length of the gate electrode of a transistor is very short, for example, 50
Even in the case where the thickness is less than or equal to nm, the short channel effect can be suppressed without increasing the channel impurity concentration, controlling the leakage current of the transistor, and suppressing the deterioration of the breakdown voltage. Further, while having this effect, a sufficient ON current can be obtained, and a normal transistor operation can be performed, and the limit of miniaturization due to an increase in the channel impurity concentration can be overcome.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a schematic view illustrating a method for manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 3 is a schematic diagram illustrating a method for manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 4 is a schematic view illustrating a method for manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 5 is a schematic view illustrating a method for manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 6 is a schematic view illustrating a method for manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 7 is a schematic view illustrating a method for manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 8 is a schematic view of a semiconductor device according to a modified example of the first embodiment of the present invention.

FIG. 9 is a schematic diagram illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 10 is a schematic diagram illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 11 is a schematic view of a semiconductor device according to a third embodiment of the present invention.

FIG. 12 is a schematic view of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 13 is a schematic view of a conventional general MOSFET.

FIG. 14 is an explanatory diagram showing a relationship between a gate length and a threshold voltage of a conventional MOSFET.

FIG. 15 is an explanatory diagram showing a relationship between a gate length of a conventional MOSFET and a channel impurity concentration necessary for suppressing a short channel.

[Explanation of symbols]

 11, 71 N-type semiconductor silicon substrate 11a Channel region 12, 74 Gate insulating film 13, 75 Gate electrode 13a Polysilicon film 13b Refractory metal silicide film 14, 72 Source region 15, 73 Drain region 16, 25 Gate sidewall insulating film 17 , 78 Insulating barrier layer 21 Field insulating film 22 P-type well region 23 SiN film 24 Depression 26, 27 Diffusion layer 28 Silicide layer 76 Control electrode 77 Intermediate insulating film

Claims (18)

[Claims] A source region and a drain region formed in a semiconductor substrate; a gate electrode formed on a channel region between the source region and the drain region with a gate insulating film interposed therebetween; A semiconductor device having an insulator layer formed between regions and between the drain region and the channel region. 2. The semiconductor device according to claim 1, wherein a gate length of said gate electrode is 50 nm or less. 3. The semiconductor device according to claim 1, wherein said insulating layer has a thickness of 2 nm or less. 4. The semiconductor device according to claim 1, wherein said insulator layer is made of one of a thermal oxide film, a nitride film, and a nitrided oxide film. 5. The semiconductor device according to claim 1, wherein the insulator layer gradually increases in a depth direction of the semiconductor substrate. 6. A semiconductor device, comprising: a source region and a drain region formed in a semiconductor substrate so as to face each other; a gate electrode formed on the semiconductor substrate between the source region and the drain region via a gate insulating film; A semiconductor device, comprising: an insulator layer formed on a part or the whole of a facing surface of a source region and a drain region. 7. The semiconductor device according to claim 1, wherein said insulator layer gradually becomes thicker in a depth direction of said semiconductor substrate. 8. A step of forming a gate electrode on a semiconductor substrate via a gate insulating film, a step of forming a side wall insulating film on a side surface of the gate electrode, and the step of forming the gate by using the gate electrode and the side wall insulating film as a mask. Selectively removing an insulating film to expose the surface of the semiconductor substrate, isotropically etching the exposed surface of the semiconductor substrate to form a recess, and forming an insulator layer on the surface of the recess. And selectively removing the insulator layer using the sidewall insulating film as a mask; and selectively growing a semiconductor layer in the recess to form a diffusion layer. Semiconductor device manufacturing method. 9. A step of forming a gate electrode on a semiconductor substrate via a gate insulating film, a step of selectively removing the gate insulating film using the gate electrode as a mask, and exposing a surface of the semiconductor substrate; Forming a recess for forming a diffusion layer by anisotropically etching the exposed surface of the semiconductor substrate; forming an insulator layer on the surface of the recess; and forming a recess on the bottom of the recess. A method for manufacturing a semiconductor device, comprising: a step of removing the insulator layer; and a step of forming a diffusion layer by selectively growing a semiconductor layer in the recess. 10. The method according to claim 8, wherein the gate electrode has a gate length of 50 nm or less. 11. The semiconductor device according to claim 8, wherein said insulating layer is formed to a thickness at which a tunnel effect occurs between said diffusion layers.
The manufacturing method of the semiconductor device described in the above. 12. The method according to claim 11, wherein the insulator layer is formed to have a thickness of 2 nm or less. 13. The semiconductor device according to claim 9, wherein the insulating layer is formed to a thickness that causes a tunnel effect between the diffusion layers.
The manufacturing method of the semiconductor device described in the above. 14. The method according to claim 13, wherein said insulator layer is formed to have a thickness of 2 nm or less. 15. The method according to claim 8, wherein said insulator layer is an oxide film formed by thermal oxidation. 16. The method of manufacturing a semiconductor device according to claim 8, wherein said recess is formed at a depth substantially equal to a thickness of said sidewall insulating film. 17. The method according to claim 8, wherein the insulating layer is formed of any one of a thermal oxide film, a nitride film, and a nitrided oxide film. 18. The method according to claim 8, wherein the step of forming the diffusion layer is performed by an epitaxial method.
The manufacturing method of the semiconductor device described in the above.