KR101131956B1 - Non volatile memory device and method for manufacturing the same - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention provides a nonvolatile memory device and a method of manufacturing the same, which can prevent the operating characteristics of the device from deteriorating due to metal ions in the spacers that exist on both sides of the floating gate of the nonvolatile memory device. The present invention provides a nonvolatile memory device including a gate structure formed on an upper surface of the substrate, and an ion blocking layer formed in the gate structure at a predetermined distance from both edges of the gate structure.

Nonvolatile Memory Devices, Metal-Based Ions, Spacers, Floating Gates, Ion Blockers, Tunneling Blocks

Description

Nonvolatile memory device and manufacturing method thereof {NON VOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME}

1 is a cross-sectional view showing a flash memory device according to the prior art.

2 is a cross-sectional view illustrating a nonvolatile memory device in accordance with an embodiment of the present invention.

3A through 3E are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention illustrated in FIG. 2.

<Explanation of symbols for the main parts of the drawings>

10, 110: substrate 111: gate insulating film

12, 112: floating gate 13, 113: dielectric film

14, 114: control gate 115: gate structure

116: O ₂ ion implantation process 117: thermal process

118A: ion barrier 118B: tunneling prevention membrane

119: reoxidation film 120: oxide film for spacer

15, 121: spacer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor device manufacturing technology, and more particularly, to a nonvolatile memory device manufacturing method, and more particularly to a flash memory device and a method of manufacturing the same.

In general, in a semiconductor production plant that produces semiconductor devices, such as sodium ions (Na ⁺ ), zinc ions (Zn ⁺ ) and iron ions (Fe ⁺ ) in the atmosphere due to the sweat of the worker or various substances present in the equipment Metal ions are present, and these metal ions are frequently trapped in a semiconductor structure, for example, an oxide-based insulating film, during the manufacturing process of a semiconductor device.

As the metal-based ions trapped in the oxide-based insulating film do not have a great influence on the device characteristics, it has not been a big issue for semiconductor manufacturers so far. However, electrons are injected into the floating gates or electrons are extracted from the floating gates. This is a major issue in nonvolatile memory devices such as NAND flash memory devices in which program and erase operations are performed.

The reason is that when the metal-based ions are present in the oxide-based spacers that exist on both sides of the floating gate, the widely spread metal-based ions are attracted to the vicinity of the floating gate by heat generated during repeated program and erase operations. Flocked metal-based ions attract electrons injected into the floating gate, which interferes with normal program and erase operations. Hereinafter, the deterioration of operating characteristics of the nonvolatile memory device due to the metal ions will be described with reference to FIG. 1.

1 is a cross-sectional view showing a flash memory device according to the prior art.

As shown in FIG. 1, a flash memory device according to the related art includes a floating gate 12 and a dielectric film formed on the floating gate 12 that are electrically separated from the substrate 10 through a tunnel oxide film 11. 13) and a gate structure including a control gate 14 formed on the dielectric film 13, and a spacer 15 formed on both side walls of the gate structure.

However, as described above, metal ions (+) such as sodium ions (Na ⁺ ), zinc ions (Zn ⁺ ), iron ions (Fe ⁺ ), and the like penetrate into the spacer 15, which is an oxide-based insulating film, and thus the spacer 15. ), And when the program operation proceeds, electrons injected into the floating gate 12 (see arrow 'A' direction) attract metal-based ions (+) present in the spacer 15 to perform a subsequent erase operation. Part of the substrate 10 is not drawn out and remains.

Therefore, according to the flash memory device manufacturing method according to the prior art, there is a problem that the cycling and retention characteristics, which are program and erase operation characteristics of the flash memory device, are deteriorated because a normal erase operation is not performed. .

Accordingly, the present invention has been proposed to solve the above-mentioned problems of the prior art, and is a non-volatile memory device capable of preventing the operation characteristics of the device from deteriorating due to metal-based ions in the spacers that exist on both sides of the floating gate. It is an object of the present invention to provide a volatile memory device and a method of manufacturing the same.

According to an aspect of the present invention, there is provided a nonvolatile memory device including a gate structure formed on an upper surface of the substrate, and an ion blocking layer spaced apart from both edges of the gate structure and formed in the gate structure.

In addition, the present invention according to another aspect to achieve the above object, comprising the steps of forming a gate structure on top of the substrate, and forming an ion blocking film in the gate structure spaced apart from both edges of the gate structure; A method of manufacturing a nonvolatile memory device is provided.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, parts denoted by the same reference numerals (reference numbers) throughout the specification represent the same components.

Example

2 is a cross-sectional view illustrating a nonvolatile memory device according to an embodiment of the present invention. Here, as an example, a NAND-type flash memory device will be described.

As shown in FIG. 2, the nonvolatile memory device according to an exemplary embodiment of the present invention may be spaced apart from a gate structure 115 formed on the substrate 110 and both edges of the gate structure 115 by a predetermined distance. An ion blocking film 118A formed in the 115 and spacers 121 formed on both sidewalls of the gate structure 115 are included. In this case, the gate structure 115 has a stacked structure of the gate insulating layer 111, the floating gate 112, the dielectric layer 113, and the control gate 114.

That is, in the nonvolatile memory device according to the embodiment of the present invention, electrons injected into the floating gate 112 during the program operation through the ion blocking layer 118A are affected by the metal-based ions captured by the spacer 121. You can block. That is, the ion blocking layer 118A blocks electrons injected into the floating gate 112 from reacting with metal-based ions present in the spacer 121 during the program operation. As a result, in the erase operation, all the electrons in the floating gate 112 may normally escape to the substrate 110.

Accordingly, the nonvolatile memory device according to the embodiment of the present invention does not have a risk of degrading the cycling characteristics of the device even during repeated program and erase operations. In addition, the retention characteristics of the nonvolatile memory device can be improved.

At this time, since the electrons are hardly injected into the floating gate 112 existing between the ion blocking layer 118A and the spacer 121 even during a program operation, there is no problem. Since the area of the dielectric film 113 present in the region between the ion blocking film 118A and the spacer 121 is very small, the coupling ratio is almost close to '0'. This is because the voltage applied to 114 hardly affects the floating gate 112.

In addition, the nonvolatile memory device according to the embodiment of the present invention may include a tunneling prevention film formed in the substrate 110 at the bottom of the gate structure 115 so as to overlap the gate structure 115 between the spacer 121 and the ion blocking layer 118A. 118B).

Here, the tunneling prevention layer 118B completely blocks FN tunneling from occurring through the floating gate 112 existing between the ion blocking layer 118A and the spacer 121. That is, the floating gate 112 existing between the ion blocking film 118A and the spacer 121 is formed by the tunneling prevention film 118B formed to overlap the floating gate 112 between the ion blocking film 118A and the spacer 121. In the program operation, electrons can hardly be injected. Accordingly, the floating gate 112 between the ion blocking layer 118A and the spacer 121 soon serves as one depletion layer.

Accordingly, the floating gate 112 existing between the ion blocking film 118A and the spacer 121 has no influence on the cycling characteristics of the device during program and erase operations, while the floating gate 112 exists between the neighboring ion blocking film 118A. Only floating gate 112 affects the cycling characteristics of the device.

For reference, FN tunneling refers to an operation principle in which program and erase operations of a NAND flash memory device are performed. For example, during a program operation, when a high voltage of about 18 to 20V is applied to the control gate 114 and a voltage of 0V is applied to the substrate 110, electrons existing in the substrate 110 pass through the gate insulating layer 111. It is injected into the floating gate 112. On the contrary, when the voltage of OV is applied to the control gate 114 and the high voltage of about 19 to 21 V is applied to the substrate 110 during the erase operation, the electrons injected into the floating gate 112 during the program operation are transferred to the substrate 110. ) Will be withdrawn.

Here, the ion blocking film 118A, the tunneling prevention film 118B, and the spacer 121 are all formed of an oxide film. In this case, the spacer 121 may have a laminated structure of the reoxidation film 119 and the oxide film 120 for the spacer. .

Hereinafter, a method of manufacturing a nonvolatile memory device according to an exemplary embodiment of the present invention shown in FIG. 2 will be described with reference to FIGS. 3A to 3E.

First, as shown in FIG. 3A, a gate structure 115 having a structure in which a gate insulating layer 111, a floating gate 112, a dielectric layer 113, and a control gate 114 are sequentially stacked on a substrate 110. ). For example, the gate structure 115 is formed as follows.

First, the gate insulating film 111 is formed by performing a dry, wet, or radical oxidation process, and then a first conductive film (not shown) for the floating gate and the dielectric film 113 on the gate insulating film 111. And a second conductive film (not shown) for a control gate are sequentially deposited. In this case, the first and second conductive films are formed of a doped or undoped polysilicon film, and the dielectric film 113 is formed of an oxide / nitride / oxide structure. It is desirable to.

Subsequently, the gate structure 115 is completed by etching the second conductive layer, the dielectric layer 113, the first conductive layer, and the gate insulating layer 111 to expose a portion of the substrate 110 through a mask process and an etching process.

Then, the injection of the O ₂ ions in the gate structure (115), O ₂ ions to carry out the implantation process 116, as shown in Figure 3b. In particular, the O ₂ ion implantation step 116 is performed to have a constant ion implantation inclination angle.

In addition, during the O ₂ ion implantation process 116, the ion blocking layer 118A (see FIG. 3C) to be subsequently formed is proportional to the distance (D, see FIG. 3C) from both edges of the gate structure 115. To regulate its energy. For example, as the ion blocking layer 118A is formed far from both edges of the gate structure 115, the ion implantation energy should be increased during the O ₂ ion implantation process 116.

Subsequently, as illustrated in FIG. 3C, a thermal process 117 is performed to form an ion blocking layer 118A in the gate structure 115. In particular, it is important to form the ion blocking layer 118A so as to be spaced apart from each other by a predetermined distance D from both edges of the gate structure 115. This is to prevent metal-based ions in the spacer 121 (refer to FIG. 3E) to be formed on both sidewalls of the gate structure 115 through the subsequent process to be directly transferred to the ion blocking layer 118A.

In addition, when the ion blocking layer 118A is formed, the tunneling prevention layer 118B may be simultaneously formed in the substrate 110 at the bottom of the gate insulating layer 111. In this case, the tunneling prevention layer 118B performs the thermal process 117 while a part of the O ₂ ions implanted during the O ₂ ion implantation process 116 is injected into the substrate 110 through the gate insulating layer 111. It is possible to form. In particular, O ₂ ion implantation process 116, when there floating gate film 112, the ion implantation energy is significantly less tunneling of O ₂ ions passing through the gate insulating film 111 than the ion implantation energy of the O ₂ ions passing through the (118B ) May be formed adjacent to both sidewalls of the floating gate 112.

In this case, the tunneling prevention film 118B is formed to overlap the floating gate 112 existing between the ion blocking film 118A and the reoxidation film 119 (see FIG. 3D). As a result, the FN tunneling may be completely blocked through the floating gate 112 existing between the ion blocking layer 118A and the reoxidation layer 119.

Subsequently, as shown in FIG. 3D, a reoxidation process is performed to form an reoxidization film 119 along the stepped top surface of the substrate 110 including the gate structure 115. Here, the reoxidation film 119 is to compensate for the etch damage of the gate structure 115 generated during the etching process for forming the gate structure 115, it can be omitted.

Subsequently, as shown in FIG. 3E, an oxide film 120 for a spacer is formed along the step of the upper surface of the reoxidized film 119.

Subsequently, an etch-back process is performed to etch the spacer oxide layer 120 and the reoxidation layer 119 so that a portion of the substrate 110 is exposed. As a result, spacers 121 are formed on both sidewalls of the gate structure 115.

As described above, when the semiconductor manufacturing process is performed, metal ions such as sodium ions (Na ⁺ ), zinc ions (Zn ⁺ ), and iron ions (Fe ⁺ ) present in the atmosphere may be formed of an insulating layer based on an oxide film ( 121) It penetrates inside. Therefore, in the exemplary embodiment of the present invention, the ion blocking layer 118A is formed in the floating gate 112 at a distance spaced apart from the spacer 121 to form an ion blocking layer during the program operation by the metal-based ions trapped in the spacer 121. Electrons injected into the floating gate 112 between the 118A may be prevented from moving toward the spacer 121.

Through this, the normal operation of the device can be enabled. That is, since the electrons injected into the floating gate 112 can escape to the substrate 110 during the erase operation, there is no fear of deterioration of the cycling characteristics and repeated retention during repeated program and erase operations. There is no.

In addition, the tunneling prevention film 118B is formed at the bottom of the gate insulating film 111 in the region overlapping the floating gate 112 between the ion blocking film 118A and the spacer 121, thereby forming the ion blocking film 118A and the spacer 121. The floating gate 112 between) serves as a perfect depletion layer. Through this, the reliability of the device can be further improved.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described implementation is for the purpose of description and not of limitation. In particular, in the exemplary embodiment of the present invention, a stack type nonvolatile memory device has been described, but the present invention is not limited thereto and may be applied to devices having a silicon oxide nitride oxide silicon (SONOS) structure. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the following effects are obtained.

First, an ion blocking layer is formed in the floating gate at a distance from the spacers on both sides of the floating gate, and the electrons injected into the floating gate are affected by the metal-based ions trapped in the spacer during the program operation. You can block. Through this, the normal erasing operation of the device can be performed to improve operating characteristics of the device, such as cycling characteristics and retention characteristics.

Second, by forming a tunneling prevention film at the bottom of the gate insulating film in the region overlapping the floating gate between the ion blocking film and the spacer, the floating gate between the ion blocking film and the spacer serves as a perfect depletion layer, further improving the reliability of the device Can be.

Claims (17)

A gate structure formed on the substrate; And An ion blocking layer formed in the gate structure spaced apart from both edges of the gate structure Nonvolatile memory device comprising a. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, And a tunneling prevention layer formed in the substrate under the gate structure between the both edges and the ion blocking layer. Claim 3 was abandoned when the setup registration fee was paid. The method of claim 1, The gate structure, A gate insulating film formed on the substrate; A floating gate formed on the gate insulating film; A dielectric film formed on the floating gate; And A control gate formed on the dielectric layer Nonvolatile memory device consisting of. Claim 4 was abandoned when the registration fee was paid. The method of claim 1, The ion blocking membrane is a nonvolatile memory device consisting of an oxide film. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 2, The tunneling prevention film is a nonvolatile memory device made of an oxide film. Claim 6 was abandoned when the registration fee was paid. The method of claim 1, And a spacer formed on both sidewalls of the gate structure. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 6, The spacer is a nonvolatile memory device made of an oxide film. Forming a gate structure over the substrate; And Forming an ion blocking layer in the gate structure spaced apart from both edges of the gate structure Nonvolatile memory device manufacturing method comprising a. Claim 9 was abandoned upon payment of a set-up fee. The method of claim 8, Forming the ion blocking membrane, And simultaneously forming a tunneling prevention layer in the substrate under the gate structure between the both edges and the ion blocking layer. Claim 10 was abandoned upon payment of a setup registration fee. The method of claim 9, Forming the ion blocking film and the tunneling prevention film, Performing an O ₂ ion implantation process; And Steps to perform thermal process Nonvolatile memory device manufacturing method comprising a. delete Claim 12 was abandoned upon payment of a registration fee. 11. The method of claim 10, The O ₂ ion implantation process controls the ion implantation energy in proportion to the distance that the ion barrier layer is spaced apart from both sidewalls of the gate structure. Claim 13 was abandoned upon payment of a registration fee. The method of claim 8, Forming the gate structure, Forming a gate insulating film on the substrate; Sequentially forming a floating gate first conductive film, a dielectric film, and a control gate second conductive film on the gate insulating film; And Etching portions of the second conductive layer, the dielectric layer, the first conductive layer, and the gate insulating layer to expose the substrate. Nonvolatile memory device manufacturing method comprising a. Claim 14 was abandoned when the registration fee was paid. The method of claim 8, The ion blocking film is a non-volatile memory device manufacturing method of forming an oxide film. Claim 15 was abandoned upon payment of a registration fee. The method of claim 9, The tunneling prevention film is a non-volatile memory device manufacturing method formed of an oxide film. Claim 16 has been abandoned due to the setting registration fee. The method of claim 8, After forming the ion barrier film, And forming spacers on both sidewalls of the gate structure. Claim 17 has been abandoned due to the setting registration fee. The method of claim 16, The spacer is formed of an oxide film.

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