JP2008112784A - Semiconductor storage and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage that can provide a memory mixedly mounted logic LSI at low cost, allows a charge holding film to capture an electron easily in write operation, and can perform the write operation speedily, and to provide a method of manufacturing the semiconductor storage. <P>SOLUTION: A portion 105a of the charge holding film 105 is arranged at the lower portion of both the ends of a gate electrode 103. A lower region 105a-1 of the portion 105a in the charge holding film 105 is positioned at a side lower than the surface of a semiconductor substrate 101 directly below the center of the gate electrode 103. In the semiconductor storage, simply by adding one mask for covering a non-oxidizable film to a region other than a memory region to a logic process, a memory element can be mixedly mounted on the logic memory, thus providing the memory mixedly mounted logic LSI at low cost. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device. More specifically, the present invention relates to a memory element structure for improving a writing speed and a semiconductor memory device capable of mounting the memory element on a logic LSI (Large Scale Integrated circuit) at low cost.

  Conventionally, a non-volatile memory capable of storing 2 bits on both sides of a gate electrode (Patent Document 1: Japanese Patent Application Laid-Open No. 2003-258128) has been proposed. FIG. 9 shows the structure of the nonvolatile memory disclosed in Patent Document 1. In FIG. 9, 201 is a semiconductor substrate, 202 is a first diffusion layer (source electrode), 203 is a second diffusion layer (drain electrode), 204 is a silicon oxide film, 205 is a silicon nitride film (charge holding film), and 206 is A silicon oxide film, 207 is a gate insulating film, and 208 is a gate electrode.

This memory cell differs from a conventional MONOS (Metal Oxide Nitride Oxide Semiconductor) structure in that an ONO (Oxide Nitride Oxide) film formed by laminating the silicon oxide film 204, the silicon nitride film 205 and the silicon oxide film 206 is used as a gate electrode. It is located only at both ends of 208. As a result, it is possible to increase the rewriting speed while securing the data retention time of 10 years.
JP 2003-258128 A

  However, in the method of forming the memory element of the above-mentioned known document 1, in order to form the ONO film composed of the silicon oxide film 204, the silicon nitride film 205, and the silicon oxide film 206 in a self-aligned manner with respect to the gate electrode 208, The formation process is complicated, and there is a problem that the process cost is high. In particular, the use of a chemical mechanical polishing (CMP) method to form the gate electrode 208 has also been a factor in raising the process cost. Further, since the formation process is very different from the process of forming a logic LSI, it is inappropriate as a memory element mixed with a logic element.

  The present invention has been made in view of the above problems, and it is an object of the present invention to provide a semiconductor memory device that can be embedded in a logic LSI at a low cost.

In order to solve the above problems, a semiconductor memory device of the present invention provides:
A semiconductor layer;
A gate electrode formed on the semiconductor layer via a gate insulating film;
A channel region of a first conductivity type disposed under the gate electrode;
A source diffusion region and a drain diffusion region of a second conductivity type disposed on both sides of the channel region;
A charge holding film having a portion located below both ends of the gate electrode and having a function of holding charges;
A region at least below the portion of the charge retention film is located below the surface of the semiconductor layer immediately below the center of the gate electrode.

  Here, the first conductivity type means P-type or N-type, and the second conductivity type means N-type when the first conductivity type is P-type. When it is N-type, it means P-type.

  According to the above configuration, at least the lower region of the portion of the charge retention film located below both ends of the gate electrode is formed below the surface of the semiconductor layer immediately below the central portion of the gate electrode. ing. For this reason, the structure is such that electrons are easily captured by the charge holding film during the write operation. Therefore, the write operation can be performed at high speed.

  In addition, the semiconductor memory device having the above structure does not require a chemical mechanical polishing method to form a gate electrode, and can be manufactured at a low cost, and can be manufactured by a process having a high affinity with a process for forming a logic LSI. Thus, it can be mixedly mounted on the logic LSI.

  In one embodiment, the film thickness of the portion of the charge retention film with respect to the surface of the semiconductor layer gradually increases from the center side to the both end sides of the gate electrode.

  According to the embodiment, the thickness of the charge retention film from the surface of the semiconductor layer is increased from the center side to both end sides of the gate electrode. For this reason, the structure has a large capture area of electrons flowing from the channel region to the drain diffusion region in the charge holding film during the write operation. Therefore, since the electron injection efficiency is high, the write operation can be performed at high speed.

  In one embodiment, the source diffusion region and the drain diffusion region are separated from the gate insulating film.

  According to the above embodiment, since the source diffusion region and the drain diffusion region are separated from the gate insulating film, the gate insulating film breaks even when a high voltage is applied to the gate electrode during the write and erase operations. It will not be destroyed by down. In addition, since the channel region is formed directly below a partial region of the charge retention film, the rewrite operation can be performed by injecting the minimum necessary number of electrons, so that the write operation can be performed at high speed. .

  In one embodiment, each of the source diffusion region and the drain diffusion region has an LDD (Lightly Doped Drain) region.

  According to the above embodiment, since the LDD structure is provided, the short channel effect can be effectively suppressed even when the memory element is miniaturized and the gate length is reduced.

  In one embodiment, the LDD region is covered with a halo region containing a first conductivity type impurity having a concentration higher than the concentration of the first conductivity type impurity in the channel region.

  According to the embodiment, since the halo region is formed so as to surround the LDD region, the PN junction between the LDD region and the halo region has a steep structure. Therefore, the write operation can be performed at high speed. In addition, the short channel effect can be suppressed by the presence of the halo region.

  In one embodiment, the halo region is separated from the gate insulating film.

  According to the above embodiment, since the halo region is separated from the gate electrode, the threshold voltage of the channel region immediately below the gate insulating film can be kept low. Therefore, the write operation can be performed at high speed.

Also, a method for manufacturing a semiconductor memory device according to the present invention includes:
In a manufacturing method of a semiconductor memory device in which a logic element and a memory element are integrated,
Forming a gate insulating film on the semiconductor layer;
Forming a gate electrode at a desired position on the gate insulating film;
Covering an area other than the memory area where the memory element exists with an oxidation-resistant film;
Forming a recess in the semiconductor layer below both ends of the gate electrode of the memory region;
And a step of burying a part of the charge holding film in the recess.

  According to the above invention, the memory element can be mixedly mounted on the logic LSI only by adding one mask for covering the oxidation-resistant film in the region other than the memory region in the logic process. Therefore, a memory-embedded logic LSI can be provided at a low cost.

  In one embodiment, the step of forming the recess includes forming a silicon oxide film on the semiconductor layer below both ends of the gate electrode by a thermal oxidation method, and removing the silicon oxide film. Process.

  In the above embodiment, the recess is formed by forming a silicon oxide film using a thermal oxidation method. Therefore, the semiconductor memory device of the present invention can be manufactured without using a special semiconductor manufacturing apparatus. Therefore, the semiconductor memory device of the present invention can be formed without increasing the process cost.

  In one embodiment, the step of forming the silicon oxide film forms the silicon oxide film by an ISSG (In-Situ Steam Generation) oxidation method.

  According to the above embodiment, since the silicon oxide film is formed by the ISSG oxidation method, the bird's beak of the gate insulating film is reduced as compared with the case of using the normal thermal oxidation method typified by the dry oxidation method. Can be suppressed. Therefore, the writing speed can be increased without reducing the driving force of the memory element.

  In one embodiment, the step of forming a recess in the semiconductor layer forms the recess by chemical dry etching.

  In the above embodiment, the recess is formed only by the chemical dry etching process. For this reason, since the number of steps can be reduced as compared with the case of using the thermal oxidation method, the process cost can be reduced. Further, bird's beaks are not formed at both ends of the gate insulating film. Therefore, the writing speed can be increased without reducing the driving force of the memory element.

  As is clear from the above, according to the semiconductor memory device of the present invention, the charge holding film portion is disposed below both ends of the gate electrode, and at least the lower region of the charge holding film portion is formed on the gate electrode. It is located below the surface of the semiconductor layer directly under the center. For this reason, the structure is such that electrons are easily captured by the charge retention film during the write operation. Therefore, the write operation can be performed at high speed.

  In addition, according to the method for manufacturing a semiconductor memory device of the present invention, a memory element is mixedly mounted on a logic element by adding only one mask for covering an oxidation resistant film in an area other than the memory area to the logic process. be able to. Therefore, a memory-embedded logic LSI can be provided at a low cost.

  Hereinafter, the memory device of the present invention will be described in more detail than the illustrated embodiment.

(Embodiment 1)
FIG. 1 shows a cross-sectional structure of an example of a memory element. In the memory element 1, a P-type well region as a first conductivity type is formed on the surface side of a semiconductor substrate 101 as an example of a semiconductor layer (not shown). A gate electrode 103 is formed on the P-type well region via a gate insulating film 102. A P-type channel region is formed below the gate electrode 103. A source diffusion region 107 and a drain diffusion region 108 which are N-type diffusion regions are formed on both sides of the channel region, that is, in the semiconductor substrate 101 on both sides of the gate electrode 103.

  A recess is formed below both ends of the gate electrode 103, and a part 105 a of the charge holding film 105 is embedded in the recess via the insulating film 104. A region 105 a-1 below the part 105 a of the charge retention film 105 is located below the surface of the semiconductor substrate 101 immediately below the center of the gate electrode 103.

  A part of the memory function body 150 including the insulating film 104 and the charge holding film 105 also functions as a gate electrode side wall insulating film. It has a role of forming in a consistent manner and a role of preventing the gate electrode 103 from being electrically short-circuited with the source diffusion region 107 and the drain diffusion region 108.

In the first embodiment, the charge holding film 105 is a silicon nitride film. However, the charge holding film 105 is not limited to this as long as it is an insulating film having a trap level for holding charges, and is not limited thereto. HfO ₂ , HfAlO ₂ , aluminum oxide A high dielectric film such as may be used.

  The gate electrode 103 overlaps the source diffusion region 107 and the drain diffusion region 108. Therefore, charges (electrons in the write operation and holes in the erase operation) generated in the PN junction region between the drain diffusion region 108 and the channel region during the rewrite operation are efficiently transferred to the charge holding film 105. Can be injected. Therefore, the writing and erasing speed can be increased.

  The source diffusion region 107 and the drain diffusion region 108 are separated from the gate insulating film 102, that is, a part 105 a of the charge holding film 105 exists on the channel region. For this reason, the resistance of the channel region immediately below the charge holding film 105 can be efficiently increased by the electrons trapped in the charge holding film 105, so that the writing speed can be increased and the memory window can be enlarged. it can. In addition, since a part 105a of the charge holding film 105 exists between the source diffusion region 107 and the drain diffusion region 108 and the gate insulating film 102, a high voltage is applied to the gate electrode 103 during the write and erase operations. Even if it is applied, the gate insulating film 102 is not broken down and destroyed. Therefore, a large operating voltage margin can be obtained.

  In the portion 105 a of the charge retention film 105 located immediately below both ends of the gate electrode 103, the film thickness from the surface of the semiconductor substrate 101 gradually increases from the central portion side of the gate electrode 103 toward both ends. For this reason, the writing speed can be increased. The reason for this will be described in detail below. 2A and 2B are enlarged views of the shapes of the portions 305a and 105a of the charge holding films 305 and 105 located immediately below the end portion of the gate electrode 103 in the vicinity of the drain diffusion region 108. FIG. FIG. 2A shows the case where the film thickness of the portion 305 a of the charge retention film 305 from the surface of the semiconductor substrate 101 is distributed with a uniform film thickness from the center of the gate electrode 103 toward the drain diffusion region 108. FIG. 2B shows the case where the thickness of the portion 105a of the charge retention film 105 gradually increases from the central portion of the gate electrode 103 toward the drain diffusion region 108. FIG. (B) and (b) respectively show examples of the present invention. Note that the charge retention films 305 and 105 are different in only the shapes of the portions 305a and 105a located immediately below the end of the gate electrode 103, and the other shapes are the same. 120 in the figure indicates electrons flowing in the channel region toward the drain diffusion region 108. Reference numerals 335 and 135 indicated by dotted lines in FIGS. 2A and 2B indicate distributions of electrons injected into the charge holding films 305 and 105. Compared with the case of FIG. 2A in which the thickness of the portion 305a of the charge holding film 305 is uniformly distributed, the thickness of the portion 105a of the charge holding film 105 is gradually increased as shown in FIG. In some cases, the electron distribution 135 in the charge retention film 105 is widely distributed in the lateral direction. Therefore, the resistance can be increased (threshold voltage is increased) over a wide channel region. Therefore, the writing speed can be increased. In addition, since the region where electrons are distributed in the charge holding film 105 is wide, the punch through resistance is enhanced even when the electric field strength between the source and the drain is increased. Therefore, it is possible to provide a memory element that can increase the operating voltage margin and increase the degree of freedom in device design. Furthermore, the portion of the charge holding film 105 in the vicinity of the gate insulating film 102 is thinner than in the case of FIG. For this reason, the electric field strength from the gate electrode 103 can be increased. Therefore, the write operation and the erase operation can be speeded up.

  Next, a procedure for forming the memory element 1 according to the first embodiment will be described. First, although not shown, an element isolation region and a P-type well region are formed at a desired position of the semiconductor substrate 101 using a known process technique. Next, the gate insulating film 102 and the gate electrode 103 are sequentially formed using a known process technique. Next, a thermal oxide film of 5 nm to 30 nm is formed by a thermal oxidation method. Thereafter, when the thermal oxide film is removed with hydrofluoric acid, the above-described recesses are formed immediately below both ends of the gate electrode 103. Next, a silicon oxide film 104 is formed by thermal oxidation, and a silicon nitride film 105 is formed by low pressure chemical vapor deposition (LPCVD). The thickness of the silicon oxide film 104 is 3 nm to 10 nm, and the thickness of the silicon nitride film is 5 nm to 100 nm. At this time, the thermal oxide film for forming the recess is preferably formed by an ISSG (In-Situ Steam Generation) method. This method uses hydrogen and oxygen. The reaction chamber is of a lamp heating type, and is a method in which steam is oxidized by generating water vapor on the wafer surface by introducing hydrogen under the condition of heating to a temperature of 950 ° C. or higher and flowing oxygen. The pressure was 100 Torr and the temperature was 1000 ° C. Since the ISSG method is a steam oxidation at a high temperature, the oxidation rate is higher than the oxidation using a general furnace. For this reason, since the oxygen diffusion distribution in the lateral direction during oxidation is not discrete but steep, bird's beaks at both ends of the gate insulating film 102 can be suppressed as much as possible. Accordingly, since the driving force of the memory element can be maintained largely, the writing operation speed can be increased. Further, since the memory window can be enlarged, a highly reliable memory element can be realized.

Next, when the charge retention film 105 and the silicon oxide film 104 are etched by anisotropic dry etching until the surface of the semiconductor substrate 101 and the surface of the gate electrode 103 are exposed, a memory function body (gate electrode sidewall insulating film) 150 is formed. The Next, when an annealing process is performed by implanting N-type impurity ions, the source diffusion region 107 and the drain diffusion region 108 are formed. At this time, since the impurity is simultaneously implanted also into the polycrystalline silicon film which is the gate electrode 103, the resistance of the gate electrode 103 is also reduced. As an N-type impurity, arsenic was implanted by a known ion implantation method with an energy of 5 keV to 50 keV and an implantation amount of 2 × 10 ¹⁵ / cm ² to 1 × 10 ¹⁶ / cm ² . The annealing treatment was performed by a rapid thermal treatment (RTA) method at a temperature of 1010 ° C. to 1100 ° C. and a time of 1 to 20 seconds.

  Next, although not shown, a refractory metal silicide film is formed by a well-known technique in a region where the silicon surface of the source diffusion region 107, the drain diffusion region 108, and the gate electrode 103 is exposed. Films, contact plugs, and metal wiring are formed to complete the semiconductor memory device.

  As described above, this formation procedure can form the memory element 1 of the present embodiment without using a special semiconductor manufacturing apparatus. Therefore, a low-cost semiconductor memory device can be provided.

(Embodiment 2)
FIG. 3 shows a cross-sectional structure of an example of the memory element. Since this memory element 2 is different from the memory element 1 of the first embodiment only in the configuration of the memory function body 151, this will be described and the rest will be omitted. In FIG. 3, the same components as those of the first embodiment in FIG. 1 are denoted by the same reference numerals as those in FIG. The memory element 2 of the second embodiment further has an effect resulting from the difference in the structure of the memory function body 151 in addition to the effect of the memory element 1 of the first embodiment. This will be described below.

  The memory function body 151 is composed of three layers: an insulating film 104, a charge holding film 115, and an insulating film 106. Specifically, the charge retention film 115 includes a horizontal portion 115a substantially parallel to the surface of the semiconductor substrate 101 and a vertical portion 115b substantially perpendicular to the horizontal portion 115a. The charge retention film of the first embodiment shown in FIG. The upper part of the outer part 105 is cut off. The film thickness from the surface of the semiconductor substrate 101 of the portion of the horizontal portion 115 a located immediately below both ends of the gate electrode 103 gradually increases from the center of the gate electrode 103 toward the source diffusion region 107 and the drain diffusion region 108. It is thick. The insulating film 106 is located outside the vertical portion 115b of the charge holding film 115 and above the outer end portion of the horizontal portion 115a. Compared with the memory element 1 of the first embodiment, the cross-sectional area of the charge retention film 115 is smaller by the insulating film 106. For this reason, charge transfer in the charge retention film 115 can be suppressed. Therefore, since a bake shift due to charge movement in the charge holding film 115 can be suppressed, a memory element having a large memory window can be provided.

  Further, as described in the first embodiment, the charge holding film 115 is a high dielectric film such as a silicon nitride film. Since such a high dielectric film has a high dielectric constant, if the ratio of the charge holding film 115 in the memory function body 151 is large, the capacitance between the gate electrode 103 and the drain diffusion region 108 becomes large, causing a wiring delay. However, in the memory function body 151 of the second embodiment, the area occupied by the charge retention film 115 having a high dielectric constant is smaller than that of the memory element 1 of the first embodiment. Accordingly, the capacitance between the gate electrode 103 and the drain diffusion region 108 can be reduced.

  Next, a procedure for forming the memory element 2 according to the second embodiment will be described. The formation procedure of the memory element 2 is different from the formation procedure of the memory element 1 of the first embodiment only in the formation procedure of the memory function body 151. Therefore, only this will be described, and other formation procedures will be omitted. First, after forming recesses directly under both ends of the gate electrode 103, the silicon oxide film 104 is formed by a thermal oxidation method, the charge holding film (silicon nitride film) 115 and the silicon oxide film are formed by a low pressure chemical vapor deposition (LPCVD) method. 106 are formed. The film thickness of the silicon oxide film 104 is 3 nm to 10 nm, the film thickness of the silicon nitride film 115 is 5 nm to 15 nm, and the silicon oxide film 106 is 30 nm to 120 nm. At this time, the thermal oxide film for forming the recess is preferably formed by the ISSG method. The reason is the same as in the first embodiment. Next, the memory function body 151 is formed by etching the silicon oxide film 106, the charge holding film 115, and the silicon oxide film 104 by anisotropic dry etching until the surface of the semiconductor substrate 101 and the surface of the gate electrode 103 are exposed. Thereafter, the memory element 2 is formed by the same formation procedure as that of the memory element 1 of the first embodiment.

  As described above, in this formation procedure, the memory element 2 of the present embodiment can be formed without using a special semiconductor manufacturing apparatus as in the first embodiment. Therefore, a low-cost semiconductor memory device can be provided.

(Embodiment 3)
The memory element according to the third embodiment provides a structure that operates normally as a memory even when the element is miniaturized and improves the memory operation speed. FIG. 4 shows a cross-sectional structure of the memory element 3. The memory element 3 is different from the memory element 2 of the second embodiment only in the structure of the source electrode and the drain electrode, so that this will be described and the others will be omitted. In FIG. 4, the same reference numerals as those in FIG. 3 are assigned to the same components as those in the second embodiment in FIG.

  The memory element 3 of the present embodiment further has an effect resulting from the difference in the structure of the source electrode and the drain electrode in addition to the effect of the memory element 2 of the second embodiment. This will be described below. The source electrode is constituted by a source diffusion region 117 and a source LDD (Lightly Doped Drain) region 127 having a deep junction depth, and the drain electrode is constituted by a drain diffusion region 118 and a drain LDD region 128 having a deep junction depth. These diffusion regions are all N-type. In both the source electrode and the drain electrode, the LDD regions 127 and 128 are formed with a shallower junction depth and a lower concentration than the deep diffusion regions 117 and 118. Therefore, since the electric field strength between the source and drain electrodes can be suppressed, even if the memory element is miniaturized and the gate length is shortened and the distance between the source and drain electrodes is shortened, the short channel effect is effectively suppressed. Thus, a fine memory element can be provided. The LDD regions 127 and 128 are covered with a P-type high concentration diffusion region 140 (halo region). The concentration of the P-type impurity in the halo region 140 is higher than the concentration of the P-type impurity in the channel region. Therefore, it has a structure that suppresses the short channel effect. Further, due to the presence of the halo region 140, a PN junction (boundary between the shallow N-type drain diffusion region (drain LDD region) 128 and the dense P-type halo region) immediately below the charge holding film 115 is formed on the surface of the semiconductor substrate 101. It is steep. For this reason, the probability of occurrence of hot electrons and hot holes increases. Therefore, the writing speed and erasing speed can be increased. The halo region 140 is separated from the gate insulating film 102. Therefore, the threshold voltage of the channel region immediately below the gate insulating film 102 can be kept low. Therefore, the write operation can be performed at high speed.

Next, a procedure for forming the memory element 3 of the present embodiment will be described. As for the formation procedure, only the formation procedure of the source / drain electrodes is different from the formation procedure of the memory element 1 of the first embodiment. First, after forming recesses immediately below both ends of the gate electrode 103, arsenic ions are energized with 1 keV to 10 keV and 1 × 10 ¹⁴ / cm ² to 2 × 10 ¹⁵ / cm to form LDD regions 127 and 128. ^In order to form the halo region 140 with an implantation amount of ² , boron ions are implanted with an energy of 10 keV to 20 keV, an implantation amount of 1 × 10 ¹³ / cm ² to 1 × 10 ¹⁴ / cm ² , and an angle of 20 ° to 40 °. Implantation is performed by a well-known ion implantation method at an implantation angle of 4 to 8 rotations (adjusting the implantation amount once so that the total implantation amount becomes the above implantation amount). Next, after forming the memory function body 151, arsenic ions are applied with energy of 5 keV to 50 keV and 2 × 10 ¹⁵ / cm ² to 1 × 10 ¹⁶ / cm ² in order to form deep diffusion regions 117 and 118. Implantation is performed by a well-known ion implantation method. The annealing treatment was performed by a RTA (rapid heat treatment) method at a temperature of 1010 ° C. to 1100 ° C. for a time of 1 to 20 seconds. At this time, the deep diffusion regions 117 and 118 are formed so as not to cover all or most of the LDD regions 127 and 128, that is, not to impair the effect of suppressing the short channel effect. The parameters that determine the lateral diffusion width of the deep diffusion regions 117 and 118 are the width of the memory function body 151, the implantation conditions of the deep diffusion regions 117 and 118, and the annealing conditions, which are sufficient for the LDD regions 127 and 128. It adjusts suitably so that it may leave. Next, although not shown, a refractory metal silicide film is formed in a region where the silicon surface of the source diffusion region 107, the drain diffusion region 108, and the gate electrode 103 is exposed by a well-known technique, and then interlayer insulation Films, contact plugs, metal wirings, and the like are formed to complete the semiconductor memory device.

  As described above, in this formation procedure, the memory element 3 of the present embodiment can be formed without using a special semiconductor manufacturing apparatus as in the first and second embodiments. Therefore, a semiconductor memory device capable of high-speed operation at low cost can be provided.

(Embodiment 4)
In the fourth embodiment, a forming procedure for embedding a memory element of the present invention in a logic process at low cost is provided. This will be described in detail with reference to FIGS. FIG. 5 compares the process (mask) of the logic process and the logic process in which the memory element of the present invention is mixedly mounted. FIG. 5A shows a logic process flow, and FIG. 5B shows a logic process flow when the memory elements of the present invention are mixedly mounted. This figure shows a process that requires a mask for photolithography, and shows the flow up to the first metal layer. The memory element of the present invention can be mixed with logic only by adding a procedure for forming a recess at the gate electrode end. When the number of masks is increased, only one additional sheet is required, and it can be understood that the combined mounting is possible at low cost. Generally, when embedding nonvolatile memories in logic, it is necessary to add 3 to 11 masks. Therefore, the fourth embodiment is a method for dramatically reducing the cost. I understand.

  Next, a formation procedure for mounting the memory element (memory element 3) of the present invention in a logic process will be described with reference to FIGS. In the fourth embodiment, a procedure for forming a recess immediately below both ends of the gate electrode 103 will be described, and the other formation procedure is the same as the logic process, and has been described in the first to third embodiments. So I will omit it. In the figure, cross-sectional views of two devices are shown. The left side shows a memory element of the present invention, and the right side shows a logic element (such as a logic core transistor and a peripheral transistor) other than the memory element. As shown in FIG. 6A, an element isolation region 130 is formed in a predetermined region of the semiconductor substrate 101. Thereafter, although not shown, a P-type well region is formed on the surface of the semiconductor substrate 101. A gate electrode 103 is formed on the P-type well region via a gate insulating film 102.

  Next, as shown in FIG. 6B, a silicon nitride film 125 is formed as an oxidation resistant film. The silicon nitride film 125 was formed to 5 nm to 20 nm using the LPCVD method. In the subsequent process, the film thickness is such that the oxidation resistance is broken during thermal oxidation to form recesses at both ends of the gate electrode 103, and the surface of the underlying gate electrode 103 and the source / drain in elements other than the memory element. Any film thickness may be used as long as the surface of the semiconductor substrate 101 in the diffusion region is not oxidized. Next, in order to remove the silicon nitride film 125 in the memory element region, a resist 160 is formed so as to expose only the memory element region.

Next, as shown in FIG. 6C, the silicon nitride film 125 in the memory element region was removed by CDE (Chemical Dry Etching) using the resist 160 as a mask. The conditions of CDE are CF ₄ / O ₂ / N ₂ mixed gas, gas flow rate is CF ₄ / O ₂ / N ₂ = 270/270/80 sccm, pressure is 70 Pa, and RF (high frequency) power is 700 W. is there. By satisfying this condition, only the silicon nitride film 125 is etched without substantially etching the underlying silicon oxide film (the gate insulating film 102 remaining in the element isolation region 130 and the source / drain regions) and silicon (the surface of the gate electrode 103). Can be selectively removed. In addition, since the CDE method is isotropic etching, a sidewall film is not formed at a step like the gate electrode 103 unlike anisotropic etching. Next, the resist 160 is removed by a known resist ashing process (ashing) and wet cleaning. At this time, the removal of the silicon nitride film 125 is not limited to this method. For example, a silicon oxide film is formed on the silicon nitride film 125 by 5 nm to 10 nm by the LPCVD method, and the resist 160 is patterned. After removing the silicon oxide film by hydrofluoric acid treatment, the resist is removed. Finally, the silicon nitride film 125 may be removed by wet treatment using phosphoric acid boil or the like using the silicon oxide film as a mask.

  Next, as shown in FIG. 7A, when thermal oxidation is performed, a silicon oxide film 126 having a thickness of 5 nm to 20 nm is formed in a region where silicon is exposed in the memory region. At this time, although not shown, a silicon oxide film having a thickness of 1 nm to 2 nm is also formed on the silicon nitride film 125. By this thermal oxidation treatment, a recess filled with part of the silicon oxide film 126 is formed between both ends of the gate electrode 103 and the semiconductor substrate 101. This is oxidized to such a shape because oxygen is easily supplied in the lateral direction through the gate insulating film 102 during thermal oxidation. This thermal oxidation is desirably performed by ISSG oxidation. This is for the same reason as in the first embodiment, and since a bird's beak at both ends of the gate insulating film 102 can be suppressed as much as possible, a memory element with a high writing speed can be realized.

  Next, as shown in FIG. 7B, the silicon oxide film 126 is removed by dipping in hydrofluoric acid. At this time, the silicon oxide film on the silicon nitride film 125 is also removed. By removing the silicon oxide film 126, a recess 161 is formed below the gate electrode 103.

  Next, as shown in FIG. 7C, the silicon nitride film 125 is removed by the CDE method described in FIG. 6C or wet processing such as phosphoric acid boil. At this time, since the selection ratio with respect to the underlying silicon and the silicon oxide film is high under any of the conditions, the underlying film is hardly reduced. After this, the LDD process is performed, and the final cross-sectional shape is not shown in the flow of a normal logic process, but the memory element and the logic of the present invention can be mixedly mounted.

  As described above, a nonvolatile memory (the memory element 3 of the present invention) can be added to a logic LSI by adding only one mask for forming a recess at both ends of a gate electrode with respect to a normal logic process. Can be mixed. Therefore, it is possible to provide a logic LSI in which a nonvolatile memory is embedded at an extremely low cost.

(Embodiment 5)
In the fifth embodiment, the memory element of the present invention is a formation procedure for embedding it in a logic process at a low cost, and a method for forming recesses in both end regions of the gate electrode 103 with fewer process steps than in the fourth embodiment is provided. To do. FIG. 8 illustrates a procedure for forming the semiconductor memory element according to the fifth embodiment. Only the procedure for forming the recesses formed in both end regions of the gate electrode 103 is different from the procedure for forming the memory element according to the fourth embodiment. Since this is different, only this procedure will be described. FIG. 8 illustrates the procedure after FIG. 6B after the silicon nitride film 125 is formed.

  As shown in FIG. 8A, with the resist used as a mask to remove the silicon nitride film 125 in the memory element region, the silicon nitride film 125 is subjected to anisotropic dry etching to form a gate electrode 103 and a semiconductor in the source / drain region. Etching is performed until the surface of the substrate 101 is exposed. Thus, unlike the fourth embodiment, the gate electrode sidewall insulating film 127 made of a silicon nitride film is formed on the sidewall portion of the gate electrode 103 of the memory element.

Next, as shown in FIG. 8B, the surface of the source / drain region is selectively etched using the CDE method to form a recess. Since the CDE method is isotropic etching, the etching proceeds in the lateral direction, so that a recess 161 is formed below both ends of the gate electrode 103 as shown in FIG. At this time, the surface of the gate electrode 103 is also etched, and the height of the gate electrode 103 is lowered by the etching amount. This has no effect on the device. The gate electrode sidewall insulating film 127 prevents the gate electrode 103 from being etched in the lateral direction to reduce the line width, and is necessary for forming a recess. Without the gate electrode side wall insulating film 127, the gate electrode 103 is also etched in the lateral direction, and a recess cannot be formed. The CDE method is performed using a mixed gas of CF ₄ / O ₂ , a gas flow rate of CF ₄ / O ₂ = 150/60 sccm, a pressure of 24 Pa, an RF power of 700 W, and a silicon etching amount of 5 nm to 30 nm. Since this condition is a condition with a high selection ratio with respect to the silicon nitride films 125 and 127 and the silicon oxide film, only silicon to be etched can be selectively etched.

  Next, as shown in FIG. 8C, the silicon nitride film 125 and the gate electrode sidewall insulating film 127 are removed by the CDE method described in FIG. 6C or wet processing such as phosphoric acid boil. At this time, since the selection ratio with respect to the underlying silicon and the silicon oxide film is high under any of the conditions, the underlying film is hardly reduced. After this, the LDD process is performed, and the final cross-sectional shape is not shown in the drawing according to the normal logic process flow, but the memory element and the logic element of the present invention can be mounted together.

  As described above, the number of process steps can be reduced in the semiconductor memory element formation procedure of the present embodiment as compared with the semiconductor memory element formation procedure of the fourth embodiment. Therefore, it is possible to provide a logic LSI in which a low-cost nonvolatile memory is embedded. The CDE method is used to form the recess. Therefore, bird's beaks formed at both ends of the gate insulating film 102 are not formed by the thermal oxidation method. Therefore, a memory element having a faster write operation than that in Embodiment 4 can be provided.

  In the first embodiment, the region 105 a-1 below the portion 105 a of the charge retention film 105 below both ends of the gate electrode 103 is positioned below the surface of the semiconductor substrate 101 immediately below the center of the gate electrode 103. However, most, almost all, or all of the portion of the charge retention film located below both ends of the gate electrode is located below the surface of the semiconductor substrate just below the center of the gate electrode. It may be.

1 is a schematic cross-sectional view of a main part of a memory element according to a first embodiment of the present invention. 2A and 2B are schematic cross-sectional views for explaining the details of the main parts of each memory element according to the first embodiment of the present invention. It is a schematic sectional drawing of the principal part of the memory element of Embodiment 2 of this invention. It is a schematic sectional drawing of the principal part of the memory element of Embodiment 3 of this invention. 5A and 5B are diagrams for explaining the manufacturing cost of the memory element of the present invention. 6 (a), 6 (b), and 6 (c) are diagrams for explaining a method of manufacturing a memory element according to the fourth embodiment of the present invention. 7A, 7B and 7C are diagrams for explaining a method of manufacturing a memory element according to the fourth embodiment of the present invention. 8A, 8B, and 8C are diagrams for explaining a method of manufacturing a memory element according to the fifth embodiment of the present invention. It is a schematic sectional drawing of the principal part of the non-volatile memory which is a prior art.

Explanation of symbols

1, 2, 3 Memory element 101 Semiconductor substrate 102 Gate insulating film 103 Gate electrode 104, 106 Insulating film 105, 115 Charge holding film 105a Part 105a-1 Lower region 107 Source diffusion layer region 108 Drain diffusion layer region 127, 128 LDD area 140 Halo area 150, 151 Memory function body

Claims (10)

A semiconductor layer;
A gate electrode formed on the semiconductor layer via a gate insulating film;
A channel region of a first conductivity type disposed under the gate electrode;
A source diffusion region and a drain diffusion region of a second conductivity type disposed on both sides of the channel region;
A charge holding film having a portion located below both ends of the gate electrode and having a function of holding charges;
2. A semiconductor memory device according to claim 1, wherein at least a lower region of the portion of the charge retention film is located below a surface of the semiconductor layer immediately below the central portion of the gate electrode. The semiconductor memory device according to claim 1,
2. The semiconductor memory device according to claim 1, wherein the thickness of the portion of the charge retention film with respect to the surface of the semiconductor layer gradually increases from the central portion side to the both end portions side of the gate electrode. The semiconductor memory device according to claim 1,
A semiconductor memory device, wherein the source diffusion region and the drain diffusion region are separated from the gate insulating film. The semiconductor memory device according to claim 1,
A semiconductor memory device, wherein the source diffusion region and the drain diffusion region each have an LDD region. The semiconductor memory device according to claim 4.
The semiconductor memory device, wherein the LDD region is covered with a halo region containing a first conductivity type impurity having a concentration higher than a concentration of the first conductivity type impurity in the channel region. The semiconductor memory device according to claim 5.
The semiconductor memory device, wherein the halo region is separated from the gate insulating film. In a manufacturing method of a semiconductor memory device in which a logic element and a memory element are integrated,
Forming a gate insulating film on the semiconductor layer;
Forming a gate electrode at a desired position on the gate insulating film;
Covering an area other than the memory area where the memory element exists with an oxidation-resistant film;
Forming a recess in the semiconductor layer below both ends of the gate electrode of the memory region;
And a step of burying a part of the charge holding film in the recess. The method of manufacturing a semiconductor memory device according to claim 7.
The step of forming the recess includes a step of forming a silicon oxide film on the semiconductor layer below both ends of the gate electrode by a thermal oxidation method, and a step of removing the silicon oxide film. A method for manufacturing a semiconductor memory device. The method of manufacturing a semiconductor memory device according to claim 8.
The step of forming the silicon oxide film comprises forming the silicon oxide film by an ISSG oxidation method. The method of manufacturing a semiconductor memory device according to claim 7.
The method of manufacturing a semiconductor memory device is characterized in that the step of forming the recess in the semiconductor layer forms the recess by chemical dry etching.

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