WO2000057479A1

WO2000057479A1 - Semiconductor device with junctions having dielectric pockets and method for making same

Info

Publication number: WO2000057479A1
Application number: PCT/FR2000/000642
Authority: WO
Inventors: Thomas Skotnicki; Maryse Paoli; Malgorzata Jurczak; Romain Gwoziecki
Original assignee: France Telecom
Priority date: 1999-03-19
Filing date: 2000-03-16
Publication date: 2000-09-28
Also published as: FR2791179A1; FR2791179B1; EP1173890A1

Abstract

The invention concerns a semiconductor device characterised by the presence of dielectric pockets (11, 12) buried in the silicon body and located in the channel region (3) in the proximity of the source (2) and drain (4) regions, self-aligned or external relative to the gate spacers (7, 8). The invention is applicable to MOS transistors.

Description

Semiconductor device with dielectric pocket junctions and its manufacturing process.

The present invention relates generally to a semiconductor device ir such as an MOS transistor, for example a MOS transistor with field effect, having an improved behavior in terms of compromise: supply current (I ₀ "leakage current (1 * OFF) - The invention therefore relates more particularly to applications in the field of CMOS circuits of NLSI technology.

In semiconductor devices such as short channel MOS transistors (≤ 0.18 μm), the effects of short channels result in a leakage current poorly controlled by the gate, going from the drain region to the region of source.

In order to control these leakage currents, for example in transistors, the solutions proposed so far consist either in increasing the doping rate of the channel, or in the use of pockets having an increased doping rate in the vicinity of the junctions, or again in the case where the drain and source zones comprise extensions by a reduction in the doping rate or in the depth of the extensions.

Such solutions are described among others in the articles:

- "Characteristics of a Buried-channel Graded drain with punchthrough stopper (BGP) MOS device (MOS device with floor drain characteristics with buried channel with stopper drilling

(BGP) "H. Sunami, K. Shimohigashi and Ν. Hashimoto, IEEE Trans. Electron Devices, Vol. ED-29, Ν ° 4, pp. 607-610, 1982;

- "High performance dual-gate CMOS utilizing a novel self-aligned pocket implantation (SPI) technology (CMOS double high performance grid using new technology (SPI) implantation of ito-aligned pockets) "A. Hori, M. Segavva, S. Kameyana and M. Yasuhira, IEEE Trans. Electron Devices, Nol. ED-40, Ν ° 9, pp. 1675-1681, 1993 ; and

- "Study of pocket implant parameters for 0.18 μm CMOS (Study of pocket implantation parameters for CMOS 0, 18 μm)" J.

Schmitz, Y.V. Ponomarev, A. H. Montrée, P.H. Woerlee, ESSDERC97 Proceedings, pp. 224-227, 1997.

For advanced technologies, the production of pockets seems the most promising solution, because it makes it possible to control the leakage current, while improving the characteristics of evolution of the threshold voltage with the gate length.

These pockets are produced by implanting dopants of the same type as this channel ix, after production of the grid, and before or after the formation of the spacers. However, this solution has several drawbacks.

These pockets are difficult to place because of the dispersion of dopants during implantation and during recvαits.

The introduction of such pockets of increased doping increases the doping of the channel and leads to a high phis substrate effect, hence a loss in saturation current.

The risk of avalanche is also increased due to higher doping at the level of the drain / channel junction.

In addition, the junction capacities are higher.

Finally, the efficiency of such pockets of increased doping is moderate in the case of short channel devices. To increase the effect, one could use the most doped bags possible but then at the cost of an increase in the drawbacks mentioned above.

The disadvantages associated with strong doping of the channel are as follows:

- a threshold voltage too high causing Line loss in supply current (I ₀ N) due to the decrease in the potential difference N _GS -

Nth (Nos ⁼ gate / source voltage; N ^ = threshold voltage);

- a higher coefficient of effect άxx substrate resulting in a loss of saturation current;

- an increased avalanche risk due to m higher doping axx level of the drain / channel junction; - higher junction capacities.

As for the reduction in doping or in the depth of the extensions, it results in an increase in the series resistances, hence a loss in supply current (I _Q N - The subject of the invention is therefore a semiconductor device such as a MOS transistor, remedying the above drawbacks axxx, and in particular a semi-conductor device in which the penetration of the lines of current less controlled by the gate going from the drain to the output is suppressed, without increasing capacities junctions, neither series resistances, nor the substrate effect, nor the threshold voltage.

The invention also relates to a method for producing such a device.

The semiconductor device according to the invention comprises a silicon substrate having an upper surface, source and drain regions formed in the substrate and defining between them a channel region, a dielectric gate coLiche and a gate on the substrate above the channel region, and spacers on two opposite sides of the grid, said semiconductor device being characterized in that it comprises at least one dielectric pocket in the channel region, adjacent to one of the regions source and drain and located either in self-alignment with the corresponding spacer of the grid, or immediately outside it Read with respect to said spacer, so as to prevent the passage of poorly controlled leakage currents between the drain region and the source region. Preferably, the semiconductor device according to the invention comprises two dielectric pockets as defined above, adjacent, respectively, to the source region and to the drain region.

In general, these dielectric pockets are located at a depth of at least 5 nm, and generally of the order of 40 nm, from the upper surface of the silicon body and the dielectric pocket has a thickness of 5 to 100 nm, preferably 20 to 100 nm.

When the source and drain regions have extensions, as is conventional, the dielectric pockets are located below the extensions and in self-alignment or immediately outside with respect to the gate spacers. Any dielectric material conventionally used in the semiconductor industry, and in particular silicon oxide and silicon nitride, can be used for the dielectric bags.

The realization of aτι minus a dielectric pocket according to the invention, in a semiconductor device, therefore eliminates the current lines going from the drain region to the source region in their lower part while leaving the current lines close to the interface between the gate oxide and the silicon body or substrate which are under the control of the gate polarization. The present invention also relates to a method for manufacturing a semiconductor device comprising at least one dielectric pocket to suppress the passage of current between lower parts of a drain region and of a source region which comprises: a) forming on a silicon substrate a layer of a gate dielectric material, for example a layer of silicon oxide; b) the formation on the grid dielectric layer of a grid; c) forming along two opposite sides of the spacer grid; d) the etching of the substrate on each side of the spacers of the grid to form recesses (for example by etching at fixed time with a depth of the order of 10 to 100 nm); e) depositing, in the recesses, a dielectric material to form in each of the recesses a dielectric pocket located immediately outside with respect to the corresponding gate spacer; f) filling the recesses with silicon; and g) doping the recesses to form source and drain regions.

Alternatively, step b) of forming the gate may include etching of the gate dielectric layer and of the silicon substrate.

(for example over a depth of 10 to 100 nm) to form the recesses on the two opposite sides of the grid; then deposition is carried out in the recesses of a dielectric material to form dielectric pockets located immediately outside relative to opposite sides of the grid. Axx is then filled with the recesses with silicon and the formation of spacers on each of the opposite sides of the grid before proceeding to axx doping the recesses filled with silicon to form the source and drain regions.

Optionally, before the etching of the substrate and the formation of the gate spacers, it is possible to implant dopant to form in the substrate lightly doped areas which serve to form extensions of the source and drain regions. The following description refers to the appended figures, which respectively represent:

Figure 1 - a schematic section of an embodiment of τ.m semiconductor according to the invention; and

Figs 2a to 2d - views, in schematic section, of the main steps in carrying out a method of manufacturing a semiconductor device according to the invention.

As shown in FIG. 1, the semiconductor device according to the invention comprises in substrate or body 1 in silicon, in which source 2 and drain 3 regions are formed. As is conventional, the source regions 2 and drain 3 may have more weakly doped extensions 2a and 3a, respectively.

These source 2 and drain 3 regions and their respective extensions 2a, 3a, define between them a channel region 4. A thin layer of gate dielectric 5 (for example SiO *,) and a gate 6 (for example made of polysilicon) ) are also formed on the upper surface of the substrate 1 above the channel region 4.

As is conventional, the grid 6 is flanked on two opposite sides of spacers 7, 8 (for example in Si ₃ N ₄ ). Finally, contacts 9 and 10 are provided on the source and drain regions 2, 3.

According to the invention, the semiconductor device further comprises, in the embodiment shown, deLix dielectric pockets 1 1 and 12 located in the channel region 4, respectively adjacent to the source and drain regions 2, 3, and auto -aligned with grid spacers 7 and 8. In the embodiment shown, the dielectric pockets 1 1, 12 are located immediately below the extensions. The dielectric pockets 1 1 and 12, for example made of Si0, are generally located at least 5 nm or below the upper surface of the silicon substrate 1 and have a thickness generally of 5 to 100 nm.

Obviously, as indicated above, these dielectric pockets 1 1, 12 could be located inrrnédiaternent outside with respect to the grid spacers 7 and 8.

With the structure according to the invention, the current lines going from the drain 3 to the source 2 in their lower parts are stopped in the pockets 1 1, 12, however qxxe the lines of co going in the part of the channel region a i above the pockets 1 1, 12, are controlled by the grid 6.

Referring to Figures 2a to 2d, we will now describe an implementation of a method for manufacturing a semiconductor device according to the invention.

In conventional manner, as shown in FIG. 2a, a layer of gate dielectric 5, a grid 6 of silicon, possibly surmounted by a protective layer, is produced on a silicon substrate.

13, (for example in Si ₃ N ₄ or SiON), and on two opposite sides of the grid 6 of the spacers 7, 8.

It is optionally possible to implant dopant to create lightly doped zones 22a and 23a which will later be used to form the extensions 2a, 3a of the source and drain regions. As shown in Figure 2b, then etched, still in a conventional manner, recesses 22, 23 on opposite sides of the grid 6, these recesses 22, 23 extending into the substrate or body of silicon 1. It is possible to , for example, use fixed-time etching, with a depth of the order of 10 to 100 nm. At this stage, as shown in FIG. 2c, according to the invention, the dielectric pockets 11 and 12 are formed, for example by conventional chemical vapor deposition (CVD) followed by anisotropic etching.

The dielectric pockets 11 and 12 are formed in the recesses 22, 23 on the walls of the silicon substrate which are located in the extension of the outer walls of the spacers.

As shown in Figure 2c, dielectric pockets also form on the insulating sides of the recesses 22, 23. These dielectric pockets which are not active, do not interfere with the operation of the final device.

Then, as shown in FIG. 2d, the recesses 22, 23 are filled by selective deposition of silicon (for example by epitaxial growth) and by implantation of the dopants to form the source and drain regions.

The device is then completed in a conventional manner.

Claims

1. Semiconductor device comprising xxxx semiconductor substrate (1) in which drain (2) and source (3) regions are formed defining between them a channel region (4), a gate dielectric sheet (5) and a grid (6) on the substrate (1) above the channel region, and spacers (7, 8) S IΓ two opposite sides of the grid

(6), characterized in that it comprises at least one dielectric pocket (1 1, 12) in the channel region (4), adjacent to one of the source and drain regions and located, either in self-alignment with the corresponding spacer (7, 8) of the grid (6), or immediately outside relative to the avidit spacer so as to prevent the passage of leakage currents poorly controlled by the grid going from the drain region (3) to the source region (2).

2. Semiconductor device according to claim 1, characterized in that it comprises line dielectric pocket (1 1) adjacent to the source region and a dielectric pocket (12) adjacent to the drain region, each located respectively in auto -alignment with a corresponding spacer (7, 8) of the grid (6).

3. Semiconductor device according to claim 1, characterized in that it comprises a dielectric pocket (1 1) adjacent to the source region (2) and a dielectric pocket (12) adjacent to the drain region (3) , each located respectively immediately outside relative to a corresponding spacer (7, 8) of the grid (6).

4. A method of manufacturing a semiconductor device according to claim 1, characterized in that it comprises: a) the formation on a silicon substrate (1) of a layer of a gate dielectric material (5 ); b) forming on the grid dielectric layer (5), a grid (6); c) forming along two opposite sides of the grid (6) spacers (7, 8); d) etching the substrate on each side of the spacers (7, 8) of the grid to form recesses (22, 23); e) the deposition, in the recesses, of a dielectric material for forming in each of the recesses a dielectric pocket (1 1, 12) located immediately outside with respect to a corresponding spacer (7, 8); f) filling the recesses by selective epitaxy of silicon in the recesses; and g) doping the filled recesses (22, 23) to form source and drain regions (2, 3).

5. A method of manufacturing a semiconductor device according to claim 1, characterized in that it comprises: a) the formation on a silicon substrate (1) of a gate dielectric layer (5); b) forming S IΓ the gate dielectric layer (5) of a gate (6); c) the etching of the substrate (1) along two opposite sides of the grid (6) to form recesses (22, 23); d) depositing in the recesses (22, 23) a dielectric material to form a dielectric pocket (1 1, 12) in each of the recesses (22, 23); e) filling the recesses (22, 23) by selective epitaxy of the silicon in the recesses; f) the formation of spacers (7, 8) on the two opposite sides of the grid, the dielectric pockets (1 1, 12) then being self-aligned with the grid spacers; and g) doping the filled recesses to form the source and drain regions (2, 3).

6. Method according to claim 4 or 5, characterized in that prior to the etching of the substrate (1), lightly doped zones (22a, 23a) are formed which will subsequently form extensions (2a, 3a) of the source regions and drain (2, 3).

7. Method according to claim 4, characterized in that the doping of the recesses (22, 23) takes place axx during the filling of the recesses.