JP2002246593A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simultaneously realize both a reduction in thin wire resistance of a gate electrode and the scale down of the gate electrode by preventing the occurrence of disconnection or a partially unformed state in a silicide film provided on the gate electrode. SOLUTION: A semiconductor device is provided with the gate electrode 3a and second side walls 6a composed of oxide films provided outside the electrode 3a. The silicide film 12 is formed on the upper surface and on the upper parts of both side faces of the electrode 3a, and third side walls 7 composed of nitride films having flattened upper end faces are provided on the second side walls 6a. In a silicon substrate 1, extension regions 5 and high-concentration source-drain regions 8 are provided. On the gate electrode 3a and source-drain regions 8, silicide films 12 and 9 are respectively provided. The silicide films 12 and 9 respectively have appropriate thicknesses.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having a silicide film provided on a gate electrode and source / drain regions, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, a transistor operating at a low voltage has been required from the viewpoint of power saving of electronic equipment. In order to realize stable operation at a low voltage in a transistor, miniaturization of a gate electrode is effective. However, as the miniaturization of the gate electrode progresses, the influence of the parasitic resistance component, which is a factor of the performance degradation of the transistor, becomes apparent. With reference to FIGS. 6A to 6C, a description will be given of a technique conventionally performed as a means for reducing the contact resistance of the gate electrode and the source / drain region and the thin line resistance of the gate electrode. While doing the following.
6A to 6C are views showing a conventional method for manufacturing a semiconductor device.

First, in a step shown in FIG. 6A, a silicon oxynitride film and a polysilicon film are sequentially deposited on a silicon substrate 101, and then the silicon oxynitride film and the polysilicon film are patterned by lithography and dry etching. Thus, a gate insulating film 102 and a gate electrode 103 are formed. After that, impurities are implanted using the gate electrode 103 as a mask, and extension regions 105 are formed in the silicon substrate 101 on both sides of the gate electrode.

Subsequently, in a step shown in FIG. 6B, a silicon oxide film is deposited on the substrate, and the silicon oxide film is etched back to form an oxide film sidewall 106 on the side surface of the gate electrode 103. I do. After that, impurities are implanted using the gate electrode 103 and the oxide film sidewall 106 as a mask to form a high-concentration source / drain region 108 outside the extension region 105.

Next, in the step shown in FIG. 6C, after a metal film such as cobalt is deposited on the substrate, the exposed surface portions of the gate electrode 103 and the source / drain regions 108 are reacted with the metal. Thus, the metal silicide film 109 for lowering the resistance is formed in a self-aligned manner to complete the semiconductor device. By forming the metal silicide film, contact resistance, which is one of the parasitic resistances, can be reduced. At the same time, the cross-sectional area of the gate electrode increases, and the low-resistance metal silicide film 109 can also reduce the fine line resistance.

[0006]

By the way, miniaturization of a semiconductor device by the above-described steps is advantageous for power saving and high integration, but makes manufacturing physically difficult. Under such circumstances, in the above-described conventional method, in the step of forming the metal silicide film 109 shown in FIG. 6C, the metal silicide film is formed at the end of the gate electrode and the end of the exposed portion of the source / drain region. It may not be formed sufficiently. Therefore, there is a problem that disconnection and an increase in thin line resistance are likely to occur particularly at the gate portion.

The reason is considered to be that the optimum silicide film thickness for reducing the contact resistance is often different between the gate electrode 103 and the source / drain regions. That is, in the gate electrode 103, it is desirable to form a thick metal silicide film to form silicide over the entire upper surface of the gate electrode. Conversely, in the source / drain regions, a thin metal silicide film is formed to reduce junction leakage. It seems desirable to suppress.

An object of the present invention is to provide a semiconductor device capable of simultaneously realizing miniaturization of a gate electrode and reduction of fine line resistance when forming a silicide film for the purpose of reducing the resistance of a gate electrode, and a method of manufacturing the same. Is to do.

[0009]

According to the present invention, there is provided a semiconductor device comprising:
A semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode made of a conductor film provided on the gate insulating film, and a gate electrode formed in a region extending from the upper surface to the upper side surface of the gate electrode. A gate silicide film, a first sidewall provided on a portion of the side surface of the gate electrode other than an upper portion, and a first sidewall provided on a side surface of the first sidewall and the gate silicide film. The first sidewall is a second sidewall capable of selective etching.
And a source / drain region provided outside the gate electrode in the semiconductor substrate.

As a result, the surface area of the gate silicide film is increased because the gate silicide film also covers the upper portion of the side surface of the gate electrode. An increase can be prevented.

By forming the cross section of the first sidewall in an L-shape, for example, the first sidewall has a high etching selectivity with respect to the silicon oxide film and the second sidewall has a high etching selectivity with respect to the silicon oxide film. When formed of a silicon nitride film, direct contact between the nitride film and the silicon substrate can be prevented.

A third side wall made of an insulating film capable of being selectively etched with the second side wall is further provided between the first side wall and the gate electrode, so that the left and right source / source regions are provided. The distance between the drain regions can be properly maintained.

Further, when an SD silicide film is further provided on the upper surface of the source / drain region, contact resistance in the source / drain region can be reduced.

In this case, the gate silicide film provided on the upper surface of the gate electrode is replaced with the SD on the source / drain region.
By suppressing the junction leakage in the source / drain regions by making the film thicker than the silicide film, it is also possible to prevent an increase in the fine line resistance of the gate electrode due to the occurrence of a disconnection or an unformed portion in the silicide film on the gate. Can be.

[0015] Further, regarding the material of the side wall, it is preferable that the first side wall is formed of a silicon oxide film and the second side wall is formed of a silicon nitride film. These can be selectively etched from each other.

When the upper surface of the second side wall is flattened, the upper end of the second side wall becomes thicker, so that the first side wall is selectively etched. Furthermore, it is possible to prevent the upper end of the second sidewall from being removed by etching.

Preferably, the silicide film is formed of a metal silicide selected from a tungsten silicide film, a titanium silicide film, a cobalt silicide film and a nickel silicide film.

Thus, the contact resistance at the gate electrode and the source / drain regions can be reduced, and the increase in the thin line resistance at the gate electrode can be prevented.

The first method of manufacturing a semiconductor device according to the present invention comprises:
(A) selectively forming a gate insulating film and a gate electrode made of a conductive film on a semiconductor substrate; and (b) forming a sidewall made of an insulating film on a side surface of the gate electrode. (C) forming at least source and drain regions by implanting impurities using at least the gate electrode as a mask;
A step (d) of forming a silicide film and the step (d)
(E) exposing an upper portion of the gate electrode and the sidewall by flattening after depositing an interlayer insulating film on the substrate after the step (e).
(F) forming a gate silicide film.

According to this method, the silicide film on the gate electrode and the silicide film on the source / drain regions are formed in different steps, so that the respective film thicknesses can be optimized. In other words, in the gate electrode, by forming the silicide film to be thicker, it is possible to prevent an increase in thin line resistance due to disconnection or occurrence of a part where no silicide is formed. On the other hand, on the source / drain regions, the junction leakage can be suppressed by forming the silicide film relatively thin.

In the above step (a), when an antireflection film is provided in the lithography step on the upper surface of the gate electrode, a gate electrode having a designed shape can be formed with good control.

In the step (e), it is preferable that an impurity is implanted into the gate electrode immediately after the gate electrode is exposed by a planarization process.

Thus, a large amount of impurities can be implanted into the gate electrode as compared with the method of implanting impurities in the step (a). Further, for example, when a PMIS transistor is formed, the exudation of boron can be suppressed as compared with the method of implanting boron in the above step (a).

The SD silicide film and the gate silicide film are made of a metal silicide selected from a tungsten silicide film, a titanium silicide film, a cobalt silicide film and a nickel silicide film, so that a gate electrode and a source are formed. -The contact resistance in the drain region can be reduced, and the increase in the fine line resistance in the gate electrode can be prevented.

According to a second method of manufacturing a semiconductor device of the present invention,
(A) selectively forming a gate electrode comprising a gate insulating film and a conductor film on the semiconductor substrate; and (b) depositing a first insulating film on the substrate after the step (a). Depositing a second insulating film selectively etchable with the first insulating film on the first insulating film, and etching back at least the second insulating film to form a gate. (D) leaving a first sidewall made of the first insulating film and a second sidewall made of the second insulating film on side surfaces of the electrode, and removing impurities using at least the gate electrode as a mask. A step (e) of forming source / drain regions by implantation, a step (f) of forming an SD silicide film on the surface of the source / drain regions, and an interlayer insulating film on the substrate after the step (f). After depositing the film, flat (G) exposing the gate electrode and the upper portions of the first and second sidewalls by processing, and removing the upper portion of the first sidewall by selective etching, and forming The method includes a step (h) of forming an air gap and a step (i) of forming a gate silicide film on the upper surface and the upper side surface of the exposed gate electrode.

According to this method, the silicide film on the gate electrode and the silicide film on the source / drain regions are formed in different steps, so that the respective film thicknesses can be optimized. That is, by forming the silicide film thicker on the gate electrode, it is possible to prevent an increase in fine line resistance due to disconnection of the silicide film or occurrence of a part where the silicide film is not formed. On the other hand, on the source / drain regions, the junction leakage can be suppressed by forming the silicide film relatively thin.

In the second method of manufacturing a semiconductor device, when the antireflection film is provided on the upper surface of the gate electrode in the step (a), the gate electrode having the designed shape can be formed with good control. it can.

In the step (g), it is preferable to implant an impurity into the gate electrode immediately after exposing the gate electrode by the planarization process.

Thus, a larger amount of impurities can be implanted than in the method of implanting impurities in the step (a). Further, for example, when a PMIS transistor is formed, the exudation of boron can be suppressed as compared with the method of implanting boron in the above step (a).

The SD silicide film and the gate silicide film are made of a metal silicide selected from a tungsten silicide film, a titanium silicide film, a cobalt silicide film, and a nickel silicide film. The contact resistance in the source / drain regions can be reduced, and the increase in the fine line resistance in the gate electrode can be prevented.

Further, after the step (a) and before the step (b), a step of forming a third sidewall on the side surface of the gate electrode, and the step of forming the third electrode on the side face of the gate electrode. Forming a low-concentration source / drain region by injecting an impurity at a lower concentration than the source / drain region as a mask. In the step (e), the gate electrode and the first to the third A method of implanting impurities using the wall as a mask can also be used.

In this case, by forming the low-concentration source / drain regions, the withstand voltage effect of the transistor can be improved. Further, by using the third sidewall as a mask, the left and right low-concentration source / drain regions can be formed. The intervals between the regions can be appropriately maintained.

After the step (b) and before the step (c),
A step of etching back the first insulating film may be added. In this case, for example, when forming the low-concentration source / drain regions, it is possible to appropriately maintain the interval between the left and right low-concentration source / drain regions. it can.

When at least the upper surface of the second sidewall is flattened in the step (g), the film thickness of the upper end portion becomes large, so that the first sidewall is selectively etched. In addition, it is possible to prevent the upper end of the second sidewall from being removed by etching.

[0035]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIGS. 1A to 1D and FIG. 2A
FIGS. 1D to 1D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

First, in a step shown in FIG. 1A, an element isolation (not shown) for surrounding the active region is formed on the silicon substrate 1, and then the active region of the silicon substrate 1 is formed on the active region by a thermal oxidation method. A silicon oxide film is formed. Furthermore, NO / O ₂
A silicon oxynitride film 2 having a thickness of 2.0 nm is formed by performing a nitridation process on the silicon oxide film using a gas system. After that, a film thickness of 200 nm is formed on the silicon oxynitride film 2.
Is deposited. Subsequently, a silicon oxynitride film 4 having a thickness of about 50 nm is deposited on the polysilicon film 3 by the CVD method. In the following steps, an NMIS transistor will be mainly described.

Next, in the step shown in FIG. 1B, the silicon oxynitride film 4, the polysilicon film 3, and the silicon oxynitride film 2 are patterned by lithography and dry etching using a KrF light source. Gate electrode 3a made of silicon, antireflection film 4a, and gate insulating film 2
a is formed. Here, since the antireflection film 4a functions as an antireflection film in a lithography process, the gate electrode 3a having a designed shape can be formed with good control.

Further, using the gate electrode 3a as a mask,
Arsenic ions (As ⁺ ) are implanted under the conditions of an acceleration voltage of 3 keV and a dose of 1 × 10 ¹⁵ cm ⁻² to form extension regions 5 on both sides of the gate electrode 3a in the silicon substrate 1. Here, prior to arsenic ion implantation, in order to secure a proper interval between the left and right extension regions 5,
An oxide film sidewall having a thickness of about 10 nm serving as an offset spacer may be formed on the side surface of the gate electrode 3a. Further, instead of the extension region 5, an LDD region containing a lower concentration impurity may be formed.

Next, in the step shown in FIG. 1C, a silicon oxide film having a thickness of about 60 nm is deposited on the substrate by the CVD method, and then the silicon oxide film is etched back, and the gate electrode 3a and the reflection are formed. A sidewall 6 is formed on the side surface of the prevention film 4a. After that, using the gate electrode 3a and the sidewall 6 as a mask, arsenic ions are accelerated to 40 k
Implantation is performed under the conditions of eV and a dose of 4 × 10 ¹⁵ cm ⁻² to form a high concentration source / drain region 8 outside the extension region 5.

Subsequently, in the step shown in FIG. 1D, a heat treatment (RTA) at 1000 ° C. for about 10 seconds is performed to activate As in the extension region 5 and the high concentration source / drain region 8. Next, a metal cobalt film having a thickness of 8 nm is deposited on the entire surface of the substrate by the CVD method.
After heating to 00 ° C to react cobalt and silicon,
The unreacted metal cobalt film is removed by selective etching. Then, the phase transition of silicide is performed at 700 to 800 ° C. As a result, a 16 nm-thick cobalt silicide film 9 (SD silicide film) is formed on the exposed surface of the high-concentration source / drain region 8. At this time,
Since the gate electrode 3a is covered with the antireflection film 4a, no cobalt silicide film is formed. In this embodiment, cobalt is used as the metal material for silicide, but tungsten, titanium, nickel or the like may be used.

Next, in the step shown in FIG. 2A, an interlayer insulating film 10 made of silicon oxide or the like is deposited on the substrate by the CVD method, and thereafter, a chemical mechanical process is performed until the upper surface of the gate electrode 3a is exposed. A polishing (CMP) process is performed.

Thereafter, in the step shown in FIG. 2B, in order to make the gate electrode 3a made of the polysilicon film 3 conductive, phosphorus ions are formed in the NMIS transistor formation region and boron ions are formed in the PMIS transistor formation region. Ions (not shown) are implanted. Thereby, the gate electrode 3a
Can be reduced, and the driving force of the transistor can be improved.

Subsequently, in the step shown in FIG.
A 12-nm-thick metal cobalt is deposited on the gate electrode 3a by a method, and after heating at 400 to 500 ° C. to react cobalt with silicon, an unreacted metal cobalt film is removed by etching. Then, the phase transition of silicide is performed at 700 to 800 ° C. Thereby, the gate electrode 3
24 nm thick cobalt silicide film 12 only on a
(Gate silicide film) is formed. FIG.
In the step (d), the silicide phase change can be omitted, and the silicide phase change can be performed collectively in this step.

Next, in a step shown in FIG. 2D, after an upper interlayer insulating film 16 made of silicon oxide or the like is deposited on the substrate by the CVD method, the interlayer insulating film 10 and the upper interlayer insulating film 16 are formed. A contact hole is formed to penetrate and reach the cobalt silicide film 9 on the high concentration source / drain region 8 and the cobalt silicide film 12 on the gate electrode 3a. Next, the plug 13 is formed by filling the contact hole with tungsten (W) or the like by the CVD method. Thereafter, a semiconductor device is completed through a wiring process and the like.

In this embodiment, the cobalt silicide film 12 on the gate electrode 3a and the high concentration source / drain regions 8
Since the film is formed in a step different from that of the cobalt silicide film 9 above, the thickness of each film can be optimized. In other words, in the gate electrode 3a, by forming the cobalt silicide film 12 to be thicker, it is possible to prevent an increase in fine line resistance due to disconnection or occurrence of a partially unformed portion.
On the other hand, in the high-concentration source / drain region 8, on the other hand, by forming the cobalt silicide film 9 to be thin, the junction leakage can be suppressed.

In this embodiment, ion implantation for imparting conductivity to the gate electrode 3a was performed in the step shown in FIG. 2B, but in the step shown in FIG. Impurity implantation may be performed. In that case, NMIS
Phosphorus ions (P ⁺ ) and PM
Boron ions (B ⁺ ) are implanted into the IS transistor formation region. However, in order to suppress the exudation of boron in the PMIS transistor formation region, boron ions are not implanted in the step of FIG. 1A, and boron ions are applied to the gate electrode of the PMIS transistor in the step of FIG. Is preferably injected. (Second Embodiment) FIG. 3 is a sectional view of a semiconductor device according to a second embodiment of the present invention. As shown in the figure,
The semiconductor device of the present embodiment includes a gate insulating film 2a made of silicon oxynitride formed on a silicon substrate 1 and a gate electrode 3a made of polysilicon containing impurities formed on the gate insulating film 2a. The gate electrode 3
a third side wall 14 made of silicon oxide covering the side surface a and having a thickness of about 10 nm, and a lateral thickness 15 nm provided outside the third side wall 14 and made of silicon oxide having an L-shaped cross section. And the first side wall 15a. Further, the semiconductor device of the present embodiment is provided on the cobalt silicide film 12 for reducing parasitic resistance, which is provided over the upper surface and the upper portion of both side surfaces of the gate electrode 3a, and on the first sidewall 15a. And a second sidewall 7 having a lateral thickness of 60 nm and made of silicon nitride having a flattened upper surface. Further, the silicon substrate 1 includes an extension region 5 provided immediately below and on both sides of the gate electrode 3a, and a high-concentration source / drain region 8 provided outside the extension region 5. .
Further, a cobalt silicide film 9 for reducing parasitic resistance is provided on the surface of the high-concentration source / drain region 8. The impurity contained in the gate electrode 3a is phosphorus or the like in the case of an NMIS transistor,
In the case of an IS transistor, boron or the like is used. Further, the extension region 5 and the high concentration source / drain region 8
Is boron or the like in the case of a PMIS transistor, and arsenic or the like in the case of an NMIS transistor. Although the gate insulating film is made of silicon oxynitride in this embodiment, the gate insulating film may be made of silicon oxide or the like. In the present embodiment, cobalt is used as the metal material for silicide, but tungsten, titanium, nickel, or the like may be used.

The feature of the semiconductor device of this embodiment is that the cobalt silicide film 12 on the gate electrode 3a and the cobalt silicide film 9 on the high-concentration source / drain regions 8 are formed in different steps in a manufacturing process described later. Therefore, the point is that each film thickness is optimized. Gate electrode 3
5A, the cobalt silicide film 12 is formed to be thick to prevent an increase in fine line resistance due to disconnection or occurrence of a partially unformed portion. On the other hand, in the high-concentration source / drain region 8, the cobalt silicide film 9 is formed to be thin in order to suppress junction leakage.

Moreover, in the present embodiment, since the cobalt silicide film 12 also covers the upper portions of both sides of the gate electrode 3a, it is possible to remarkably reduce the fine line resistance.

FIGS. 4 (a) to 4 (d) and FIGS.
(D) is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to the second embodiment of the present invention.

First, in the step shown in FIG. 4A, after an element isolation (not shown) for surrounding the active region is formed on the silicon substrate 1, the active region of the silicon substrate 1 is formed on the active region by thermal oxidation. A silicon oxide film is formed. Furthermore, NO / O ₂
A silicon oxynitride film having a thickness of 2.0 nm is formed by performing a nitridation process on the silicon oxide film using a gas system.
Thereafter, a 200-nm-thick polysilicon film is deposited on the silicon oxynitride film. Subsequently, by the CVD method,
A silicon oxynitride film having a thickness of about 50 nm is deposited on the polysilicon film. In the following steps, mainly NMIS
The transistor will be described.

Next, the silicon oxynitride film, the polysilicon film and the silicon oxynitride film are patterned by lithography and dry etching using a KrF light source to form a gate electrode 3 made of polysilicon.
a, an antireflection film 4a, and a gate insulating film 2a.
Here, since the antireflection film 4a functions as an antireflection film in a lithography process, the gate electrode 3a having a designed shape can be formed with good control.

Subsequently, after depositing a silicon oxide film on the substrate by the CVD method, etch back is performed to form a third sidewall 14 having a thickness of about 10 nm serving as an offset spacer on the side surface of the gate electrode 3a. I do. Thereby, an appropriate interval between the left and right extension regions 5 can be secured. Thereafter, using the gate electrode 3a and the third sidewall 14 as a mask, arsenic ions are
The implantation is performed under the conditions of an acceleration voltage of 3 keV and a dose of 1 × 10 ¹⁵ cm ⁻² to form extension regions 5 on both sides of the gate electrode 3 a in the silicon substrate 1. Here, instead of the extension region 5, L containing an impurity at a lower concentration is used.
A DD area may be created. Furthermore, by the CVD method,
A 15 nm-thick covering oxide film 15 is formed on the substrate.

Next, in the step shown in FIG. 4B, after depositing a silicon nitride film having a thickness of about 60 nm on the substrate by the CVD method, the silicon nitride film is etched back. Subsequently, the exposed portion of the coating oxide film 15 is removed by selective etching. As a result, a first sidewall 15a made of silicon oxide having an L-shaped cross section is formed outside the third sidewall 14, and a second sidewall 7 made of silicon nitride is formed.
Is formed on the second side wall 15a. Next, the gate electrode 3a, the third sidewall 14, the first
Arsenic ions are implanted under the conditions of an acceleration voltage of 40 keV and a dose of 4 × 10 ¹⁵ cm ^{−2 using} the side wall 15 a and the second side wall 7 as masks, and a high concentration source / drain region 8 is formed.

Next, in the step shown in FIG. 4C, a heat treatment (RTA) at 1000 ° C. for about 10 seconds is performed to activate As in the extension region 5 and the high concentration source / drain region 8. Thereafter, a metal cobalt film having a thickness of 8 nm is deposited on the entire surface of the substrate by a CVD method,
After heating to 00 ° C to react cobalt and silicon,
Unetched metal cobalt film is removed by etching. Then, the phase transition of silicide is performed at 700 to 800 ° C. As a result, a cobalt silicide film 9 having a thickness of 16 nm is formed on the exposed surface of the high-concentration source / drain region 8. At this time, since the gate electrode 3a is covered with the antireflection film 4a, no cobalt silicide film is formed. Although cobalt is used as the silicide metal material in this embodiment, tungsten, titanium, nickel, or the like may be used.

Next, in a step shown in FIG. 4D, after an interlayer insulating film 10 made of silicon oxide or the like is deposited on the substrate by the CVD method, a CMP process is performed until the upper surface of the gate electrode 3a is exposed. I do.

Thereafter, in the step shown in FIG. 5A, phosphorus ions are added to the NMIS transistor forming region in order to make the gate electrode 3a made of a polysilicon film conductive.
Boron ions (not shown) are implanted into the PMIS transistor formation region. The ion implantation may be performed in the step shown in FIG. 4A.
Since there is a possibility that an error will occur when patterning a,
It is more preferable to perform this step.

Next, in the step shown in FIG. 5B, the third side wall 14, the first side wall 15a, and the interlayer insulating film 10 are wet-etched to remove the upper portions thereof. Thereby, the upper portion of the side surface of the gate electrode 3a, the second
A gap 11 is formed between the side wall 7 and the gate electrode 3a. This depth is preferably about 10 nm to 50 nm.

In the step shown in FIG. 5B, the gap 11 is formed between the second side wall 7 and the gate electrode 3a by performing wet etching. To silicide. In this case, since the width of the upper end surface of the second sidewall 7 is increased by the flattening process, the upper end of the second sidewall 7 is not removed by wet etching. Therefore, the silicide does not expand in the lateral direction and the self-aligned contact (SA
C) There is no problem in the process.

Subsequently, in the step shown in FIG.
A 12-nm-thick metal cobalt is deposited on the gate electrode 3a by a method, and is heated to 400 to 500 ° C. to react cobalt with silicon. Then, an unreacted metal cobalt film is removed by selective etching. Then 700-800
Invert the silicide phase at ℃. Thus, the cobalt silicide film 1 having a thickness of 24 nm is formed only on the gate electrode 3a.
2 are formed. In the step of FIG. 4C, the silicide phase change can be omitted, and the silicide phase change can be performed collectively in this step.

Next, in a step shown in FIG. 5D, after an upper interlayer insulating film 16 made of silicon oxide or the like is deposited on the substrate by the CVD method, the interlayer insulating film 10 and the upper interlayer insulating film 16 are formed. A contact hole is formed to penetrate and reach the cobalt silicide film 9 on the high concentration source / drain region 8 and the cobalt silicide film 12 on the gate electrode 3a. Next, the plug 13 is formed by filling the contact hole with tungsten (W) or the like by the CVD method. Thereafter, a semiconductor device is completed through a wiring process and the like.

In the present embodiment, as in the first embodiment, the cobalt silicide film 12 on the gate electrode 3a and the cobalt silicide film 9 on the high concentration source / drain region 8 are formed in different steps. Each film thickness can be optimized. That is, in the gate electrode 3a, by forming the cobalt silicide film 12 to be relatively thick,
It is possible to prevent an increase in fine line resistance caused by disconnection or occurrence of a partially unformed portion. On the other hand, high concentration source
Conversely, in the drain region 8, the junction leak can be suppressed by forming the cobalt silicide film 9 to be thin.

Further, in the present embodiment, since the cobalt silicide film 12 also covers the upper portions on both sides of the gate electrode 3a, disconnection hardly occurs, and an increase in thin line resistance can be more effectively prevented.

(Other Embodiments) In the second embodiment, an L-shaped first side wall 15a is formed in the step shown in FIG. 4B.
In the step of FIG. 4A, the silicon oxide film may be etched back to form a substantially wedge-shaped first sidewall. In this case, since the first sidewall plays a role of an offset spacer at the time of ion implantation, an appropriate space between the left and right source / drain extension regions 5 is ensured as in the second embodiment. There is an effect that can be.

[0064]

According to the semiconductor device of the present invention or the method of manufacturing the same, the silicide film on the gate electrode is formed in a region extending from the upper surface to the upper portion of the side surface, or on the gate electrode and on the source / drain regions. Since measures such as forming a silicide film individually are taken, effects such as prevention of an increase in thin line resistance at the gate electrode due to disconnection of the silicide film or occurrence of a partially unformed portion can be exhibited. .

[Brief description of the drawings]

FIGS. 1 (a) to 1 (d) show steps in a manufacturing process of a semiconductor device according to a first embodiment of the present invention up to forming a cobalt silicide film on a surface portion of a high concentration source / drain region. FIG.

FIGS. 2A to 2D are cross-sectional views showing a process up to forming an interlayer insulating film and a plug over a MIS transistor in a manufacturing process of the semiconductor device according to the first embodiment of the present invention; It is.

FIG. 3 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

FIGS. 4A to 4D are cross-sectional views illustrating a process up to a planarization process after depositing an interlayer insulating film in a manufacturing process of a semiconductor device according to a second embodiment of the present invention. .

FIGS. 5A to 5D are cross-sectional views showing a process up to forming an interlayer insulating film and a plug above a MIS transistor in a manufacturing process of a semiconductor device according to a second embodiment of the present invention; It is.

FIGS. 6A to 6C are cross-sectional views showing steps of manufacturing a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Silicon oxynitride film 2a Gate insulating film 3 Polysilicon film 3a Gate electrode 4 Silicon oxynitride film 4a Antireflection film 5 Extension region 6 Sidewall 7 Second sidewall 8 High concentration source / drain region 9 Cobalt silicide Film 10 interlayer insulating film 11 void 12 cobalt silicide film 13 plug 14 third sidewall 15 coating oxide film 15a first sidewall 16 upper interlayer insulating film

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Ryujun Yamada 1006 Kazuma Kadoma, Kadoma, Osaka Prefecture F-term in Matsushita Electric Industrial Co., Ltd. (reference) 4M104 BB01 BB18 BB20 BB21 BB25 BB28 CC01 CC05 DD43 DD55 DD79 DD84 EE09 EE17 GG09 GG10 GG14 HH14 HH15 HH16 5F048 AA01 AA07 BB01 BB06 BB07 BB08 BB11 BB12 BC05 BC06 BF06 BF15 BF16 DA00 DA25 DA27 DA30 5F140 AA01 AA10 AA14 AA24 BA01 BD09 BE07 BE08 BF04 BG BG BG BG BG BG BG BG BG BG BG BG BG BG BG BG BG52 BG53 BG54 BG58 BH14 BH15 BJ08 BJ11 BJ17 BJ27 BK02 BK13 BK21 BK30 BK34 BK38 BK39 CE07 CE14

Claims (19)

[Claims] A semiconductor substrate; a gate insulating film formed on the semiconductor substrate; a gate electrode formed of a conductive film provided on the gate insulating film; A gate silicide film formed in a region extending over the region, a first sidewall provided on a portion of the side surface of the gate electrode except for an upper portion, and a side wall of the first sidewall and the gate silicide film. A semiconductor device comprising: a first sidewall provided; a second sidewall capable of being selectively etched; and source / drain regions provided outside the gate electrode in the semiconductor substrate. 2. The semiconductor device according to claim 1, wherein the first sidewall has an L-shaped cross section. 3. The semiconductor device according to claim 1, wherein the insulating film is provided between the first side wall and the gate electrode and is capable of selectively etching the second side wall. A semiconductor device further comprising a third sidewall. 4. The semiconductor device according to claim 1, further comprising an SD silicide film provided on an upper surface of said source / drain region. 5. The semiconductor device according to claim 4, wherein said gate silicide film is thicker than said SD silicide film provided on an upper surface of said source / drain region. 6. The semiconductor device according to claim 1, wherein said first sidewall is made of a silicon oxide film, and said second sidewall is made of a silicon nitride film. A semiconductor device characterized by being performed. 7. The semiconductor device according to claim 1, wherein an upper surface of said second sidewall is flattened. 8. The semiconductor device according to claim 1, wherein the SD silicide film and the gate silicide film are
A semiconductor device comprising a metal silicide selected from a tungsten silicide film, a titanium silicide film, a cobalt silicide film, and a nickel silicide film. 9. A step (a) of selectively forming a gate insulating film and a gate electrode made of a conductive film on the semiconductor substrate, and forming a sidewall made of an insulating film on a side surface of the gate electrode. A step (b), a step of forming source / drain regions by implanting impurities using at least the gate electrode as a mask, and a step (d) of forming an SD silicide film on the surface of the source / drain regions (E) exposing an upper portion of the gate electrode and the sidewall by flattening after depositing an interlayer insulating film on the substrate after the step (d); Forming a gate silicide film; and (f) forming a gate silicide film. 10. The method of manufacturing a semiconductor device according to claim 9, wherein in the step (a), an antireflection film is provided on an upper surface of the gate electrode. 11. The method for manufacturing a semiconductor device according to claim 9, wherein in the step (e), an impurity is implanted into the gate electrode immediately after exposing the gate electrode by a planarization process. A method for manufacturing a semiconductor device, comprising: 12. The method for manufacturing a semiconductor device according to claim 9, wherein said silicide film is one of a tungsten silicide film, a titanium silicide film, a cobalt silicide film, and a nickel silicide film. A method for manufacturing a semiconductor device, comprising a selected metal silicide. 13. A step (a) of selectively forming a gate electrode comprising a gate insulating film and a conductor film on the semiconductor substrate.
And (b) depositing a first insulating film on the substrate after the step (a); and forming a second insulating film selectively etchable with the first insulating film by the first insulating film. (C) depositing on the film, etching back at least the second insulating film, and forming a first sidewall made of the first insulating film on the side surface of the gate electrode and the second insulating film. A step (d) of leaving a second sidewall made of a film; a step (e) of implanting impurities using at least the gate electrode as a mask; and a step (e) of forming a source / drain region; (F) forming an SD silicide film on the substrate; and, after the step (f), depositing an interlayer insulating film on the substrate, and then planarizing the gate electrode and the first and second sidewalls. Expose the top Step (g), after the step (g), a step (h) of removing an upper portion of the first sidewall by selective etching to form a gap on a side portion of the gate electrode; Forming a gate silicide film on the upper surface and the upper surface of the side surface of the formed gate electrode. 14. The method of manufacturing a semiconductor device according to claim 13, wherein in the step (a), an anti-reflection film is provided on an upper surface of the gate electrode. 15. The method for manufacturing a semiconductor device according to claim 13, wherein in the step (g), an impurity is implanted into the gate electrode immediately after exposing the gate electrode by a planarization process. A method for manufacturing a semiconductor device, comprising: 16. The method of manufacturing a semiconductor device according to claim 13, wherein said SD silicide film and said gate silicide film are
One of a tungsten silicide film, a titanium silicide film, a cobalt silicide film, and a nickel silicide film
A method for manufacturing a semiconductor device, comprising a selected metal silicide. 17. The method for manufacturing a semiconductor device according to claim 13, wherein after the step (a) and before the step (b), a first electrode is formed on a side surface of the gate electrode. Forming a low-concentration source / drain region by implanting an impurity at a lower concentration than the source / drain region using the gate electrode and the third sidewall as a mask. In the step (e), the gate electrode and the first to third electrodes
And implanting impurities using the side walls as masks. 18. The method for manufacturing a semiconductor device according to claim 13, wherein the first insulating film is etched after the step (b) and before the step (c). A method of manufacturing a semiconductor device, further comprising a backing step. 19. The method for manufacturing a semiconductor device according to claim 13, wherein in the step (g), at least an upper surface of the second sidewall is flattened. A method for manufacturing a semiconductor device.