JPH08264771A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE: To obtain a semiconductor device wherein the resistance of a gate electrode is reduced, and the restraint of a leak current and the reduction of a diffusion layer capacitance can be realized at the same time, while a device is miniaturized. CONSTITUTION: A gate electrode 48b is formed in a T-shape, whose upper part is made wider than a gate insulating film 44 in order to reduce the resistance of the gate electrode. A second conducting film 48a is stretched and formed on a side wall insulating film and an element isolation part. When the second conducting film 48a is etched, a recessed part is not formed by overetching. As to a source drain-region, a sufficient area can be maintained by forming the second conducting film 48a composed of poly silicon on a substrate 41. A shallow diffusion layer is formed on the substrate 41. The junction of a source-drain diffusion layer does not approach a metal silicide layer, and a sufficient source.drain region can be maintained while a problem like a leak current due to a deep diffusion layer is evaded.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a MISFET.

[0002]

2. Description of the Related Art In recent years, with the demand for higher density and higher speed of LSIs, higher speed of semiconductor devices is required. Above all, attempts have been made to reduce the parasitic resistance of the source / drain and the gate of the MISFET, and a salicide technique for forming a silicide film which is a reaction film of metal and silicon in a self-aligned manner has been proposed.

FIG. 4 (e) is a completed sectional view of a MOSFET to which such a salicide technique is applied. Source·
A metal silicide film 8 is formed on the surfaces of the drain diffusion layer 6 and the gate electrode 5a. As a result, the resistance of the source / drain diffusion layer 6 and the gate electrode 5a is reduced.

A method of manufacturing such a conventional MOSFET will be described with reference to FIGS. First, FIG.
As shown in (a), LOCOS (L
ocalOxidation of Silicon)
A device isolation region 2 for electrically isolating adjacent devices is formed by a method such as a method, and after a P well region 3 is formed by implanting P-type impurities such as boron and heat treatment, gate oxidation is performed on the substrate surface by heat treatment or the like. The film 4 is formed.

Thereafter, as shown in FIG. 4 (b), the CVD
(Chemicai Vapor Depottisio
The gate polysilicon film 5 is formed to a film thickness of 300 nm by the n) method or the like, and the resist pattern 6 is formed in the region where the gate electrode is to be formed by a lithography process.

Next, as shown in FIG. 4C, RIE (Reactive) is performed using the resist pattern 6 as a mask.
The gate electrode 5a is formed by a long etching method, and As is used as a mask to inject As energy 20
Implantation is performed at a dose of 1 × 10 ¹⁴ cm ⁻² and a dopant for the thin diffusion layer 6 a.

Then, as shown in FIG.
_{The two} films are deposited on the surface of the substrate 1 to a thickness of 100 nm by the CVD method and etched to a thickness of 100 nm by the RIE method or the like to form SiO ₂ side wall films 7 on both sides of the gate electrode 5a. Using the gate electrode 5a as a mask, As for the dense diffusion layer 6b, As is ion-implanted at an acceleration energy of 40 kev and a dose amount of 3 × 10 ¹⁵ cm ⁻² , and RTA (Ra
The source / drain diffusion layer 6 is formed by activating by a pid Thermal Aneal method or the like. Then, the natural oxide film is removed by hydrofluoric acid treatment.

Next, as shown in FIG. 4 (e), a titanium film having a thickness of 30 nm is deposited on the surface of the substrate 1 by the sputtering method, and the titanium film is reacted with the substrate silicon and the gate polysilicon by the RTA method. The titanium silicide film 8 is selectively formed only on the source / drain diffusion layer 6 and the gate electrode 5a. After that, the unreacted titanium film is removed by a treatment of sulfuric acid / hydrogen peroxide system, a SiO ₂ film for the interlayer insulating film 9 is deposited, openings for source / drain electrodes are formed, and a metal electrode such as Al is formed. By forming 10, the conventional MOSFET is completed.

By adopting the salicide technique in the manufacturing process as described above, the silicide film can be selectively formed, a wider contact area can be secured as compared with the method of patterning by the photolithography method, and the parasitic resistance is reduced. It is controllable.

However, as the high integration progresses as described above, miniaturization of the MISFET is required, and some problems have become apparent in the salicide technique. Fine MISFE
At T, the junction depth of the source / drain diffusion layer needs to be sufficiently shallow in order to prevent the short channel effect.
At this time, a certain distance is required between the metal silicide film and the junction position of the diffusion layer for the purpose of suppressing the leak current, and the metal silicide film needs to be thin.

In the conventional process, since the source / drain diffusion layer and the silicide film on the gate electrode are formed at the same time, when the metal silicide film is formed thin as described above, the resistance of the gate electrode is reduced. There is a problem of becoming insufficient.

Further, as miniaturization progresses, it is necessary to shorten the width of the gate electrode, which synergizes with the thinning, resulting in deterioration of the crystallinity of the silicide film and a problem of a thin line effect in which the resistivity decreases.

To solve this problem, the embedded type, conc
In a transistor called ave type in which a gate electrode is embedded and formed so as to be surrounded by an insulating film, the resistance can be reduced by increasing the area of the gate electrode. However, in order to fully exert the characteristics of the structure, the gate electrode is formed close to the source / drain regions via the relatively thin insulating film. Therefore, there is a problem that the overlap capacity becomes large.

On the other hand, in the device shown in FIG. 4 (e), if the concentration of the source / drain diffusion layers is increased for the purpose of improving the electrode driving force, the junction capacitance with the substrate increases and high-speed operation becomes impossible. There is also a problem.

To solve this problem, as shown in FIG. 5C, polysilicon is deposited from the diffusion layer 18 to the element isolation region 2 to form a polysilicon film 15a on the substrate. MOSFETs have been proposed. According to this device, the driving force is secured in the source / drain regions, and the silicide film is formed on the surface of the polysilicon film 5 and does not penetrate deeply into the substrate 1, so that the leak current can be suppressed and the diffusion can be achieved. The layer capacity can also be reduced.

The method of forming this MOSFET is shown in FIG.
This will be described with reference to (c). The formation of the LOCOS insulating film 2, the well region 3, the gate oxide film 4a, and the gate electrode 5a on the substrate 1 as shown in FIG. The method is the same as the method shown in b), and the detailed description of the steps and symbols is omitted here.

After forming a gate electrode on the substrate 1, CVD is performed.
Then, a polysilicon film 15 is formed by a method or the like, and a resist pattern 16 is formed by a lithographic process on the surface of the polysilicon film 15 from the predetermined region of the source / drain diffusion layer to the LOCOS insulating film 2.

After that, the polysilicon film 15 is formed by RIE using the resist pattern 16 as a mask as shown in FIG. 5B. Then, ion implantation for the source / drain diffusion layers is performed on the surface of the polysilicon film 15a and the substrate 1. At this time, the resist pattern 16
Difficult to fit on the planned area of the drain diffusion layer,
There will always be some misalignment.

Further, when patterning films of a plurality of devices on one wafer, patterning varies depending on the position on the wafer due to gas flow, non-uniformity of pressure, etc., and partial etching can be completed completely. Sometimes there is not. Due to this problem, over-etching is usually performed for complete patterning.

When over-etching is performed in this apparatus, the etching selectivity of the polysilicon film and the substrate silicon film is low on the surface of the substrate 1 where the polysilicon film 15a is not formed on the surface. Therefore, the over-etching affects the substrate. As a result, the recess 17 is formed. When the source / drain diffusion layer is ion-implanted, a deep diffusion layer is formed immediately below the recess 17.

After that, as shown in FIG. 5C, the substrate 1
An insulating film for interlayer separation is formed on the surface by a CVD method or the like, an opening for contact is formed, and then a metal wiring is formed to complete the MOSFET.

When the source / drain diffusion layer 18 penetrates deeply into the substrate 1 as in this device, a leak current is likely to occur, the short channel effect is deteriorated, and the parasitic resistance is increased, which is an initial purpose. A device that can be miniaturized cannot be achieved, which has been a major obstacle to practical use.

[0023]

As described above, in the conventional semiconductor device, problems such as an increase in resistance of the gate electrode due to miniaturization, generation of leak current, and operation delay due to diffusion layer capacitance have occurred. . The present invention solves the above-mentioned problems, and while promoting miniaturization of the device, the resistance of the gate electrode is reduced,
It is another object of the present invention to provide a semiconductor device capable of simultaneously suppressing leakage current and reducing diffusion layer capacitance.

[0024]

In order to solve the above problems, the first aspect of the present invention is to provide a semiconductor substrate having a gate insulating film formed on its surface, and a gate electrode formed on the semiconductor substrate. From the first conductive film, the first sidewall insulating films formed on both sides of the first conductive film, and the surface of the first conductive film,
A second conductive film that is formed as a gate electrode and extends on the surface of the side wall insulating film on the side of the first conductive film, and a source / drain diffusion film that is formed on the surface of the semiconductor substrate. Provided is a semiconductor device characterized by being provided.

The second conductive film is a silicon film or a metal film, and in the case of the silicon film, it is desirable to provide a metal silicide film on the surface. In order to solve the above problems, a second aspect of the present invention is to form a semiconductor substrate having a gate insulating film formed on its surface, a gate electrode formed on the gate insulating film, and both side portions of the gate electrode. A first side wall insulating film, which separates the first side wall insulating film and an adjacent element;
A third conductive film formed so as to extend from a part of the first side wall insulating film to the surface of the semiconductor substrate and the element isolation; ,
Provided is a semiconductor device comprising at least a source / drain region formed on the surface of the third conductive film.

The first and third conductive films are a metal film, a metal silicide film, or a silicon film. In the case of a silicon film, the same metal silicide film is formed on each surface, which complicates the process. It is desirable to prevent

The first conductive film is a silicon film, and when the third conductive film metal silicide film is used, a thick metal silicide film can be formed on the surface of the first conductive film, in which case the gate electrode is low. Be made resistant.

In order to solve the above problems, the third aspect of the present invention is to provide a semiconductor substrate having a gate insulating film formed on the surface thereof, and a first electrode formed on the gate insulating film to serve as a gate electrode. A conductive film, a first sidewall insulating film formed on both sides of the first conductive film, a surface of the first conductive film, and a part of the first sidewall insulating film surface on the first conductive film side. A second conductive film which is formed as a gate electrode and extends from the first side wall insulating film on the side of the semiconductor substrate where the surface is exposed,
A third conductive film formed so as to extend to the surface of the semiconductor substrate, the third conductive film, and a source formed on at least the surface of the third conductive film of the semiconductor substrate. A drain region is provided, and the third conductive film is provided with a contact with a wiring on the element isolation.

It is preferable that the second and third conductive films are formed of the same film in order to prevent the process from becoming complicated.
It is preferable that the first sidewall insulating film is formed with a width equal to or larger than a processing limit width for separating the second insulating film and the third conductive film from the same film.

In the above second and third aspects of the present invention, the third aspect
It is preferable that at least a part of the contact portion that forms the upper wiring of the conductive film is formed above the element isolation. It is preferable that the width of the source / drain region sandwiched between the first sidewall insulating film and the element isolation region is narrower than the processing limit of the contact hole in order to reduce the diffusion layer capacitance.

The third conductive film is preferably used as the first layer wiring. Further, in order to solve the above-mentioned problems, a fourth step of the present invention is to form a gate insulating film on a semiconductor substrate, to form a first conductive film on the gate insulating film, and to form a gate insulating film, And a step of forming a sidewall insulating film on a sidewall of the first conductive film, a step of forming an element isolation for separating adjacent elements, a first conductive film surface, and a first conductive film side A second conductive film is formed so as to extend to the surface of the side wall insulating film of the portion, and the surface of the semiconductor substrate and the isolation between elements are located above the exposed part of the side wall insulating film on the side of the semiconductor substrate. The method includes a step of forming a third conductive film so as to extend, and a step of forming a source / drain region on at least the surface of the third conductive film and the surface of the semiconductor substrate. A method for manufacturing a semiconductor device is provided.

After forming the first conductive film, it is preferable to perform ion implantation for thin source / drain regions. After forming the thin source / drain regions, adjacent to the thin source / drain regions on the surface of the semiconductor substrate,
Before forming the third conductive film, a step of forming a part of the sidewall insulating film by controlling its width so as to be used as a mask when forming a source / drain region that is darker than the source / drain region. In addition, it is preferable to form the rest of the sidewall insulating film.

In order to solve the above-mentioned problems, the fifth aspect of the present invention is to provide a semiconductor substrate having a gate insulating film formed on the surface thereof,
The gate electrode formed on the gate insulating film, the first side wall insulating film formed on both sides of the gate electrode, the side wall conductive film formed on the outside thereof, and the adjacent element are separated from each other. Element isolation and a third conductive film formed so as to extend from the part of the sidewall conductive film to the surface of the semiconductor substrate and the element isolation, the third conductive film, and the surface of the semiconductor substrate. Among these, there is provided a semiconductor device characterized by comprising at least a source / drain region formed on the surface of the third conductive film.

The first and third conductive films are metal films, metal silicide films, or silicon films, and in the case of the sidewall conductive film silicon film, the same metal silicide film is formed on each surface. It is desirable from the viewpoint of preventing complication.

When the first conductive film is a silicon film and the third conductive film is a metal silicide film that can withstand the process of the silicidation process, a thick metal silicide film can be formed on the surface of the first conductive film. In this case, the resistance of the gate electrode is lowered.

When the side wall conductive film is an amorphous silicon film, it is preferably recrystallized by a thermal process. It is desirable that the side wall conductive film contains impurities of the same conductivity type as the source and drain to serve as a solid phase diffusion source for forming a shallow diffusion layer near the gate. In the case where the sidewall conductive film is a silicon film and does not contain impurities, the impurity implantation is performed in the same step as the impurity implantation step for the source / drain formed outside the sidewall conductive film for the sake of simplification of the process. Desirable for. When the side wall conductive film is made of metal or metal silicide film, it is necessary to form the source / drain diffusion layer before forming the side wall conductive film, and further form the source / drain to suppress the leakage current and the short channel effect. Is desirable. Further, it is desirable to control the capacitance formed between the sidewall conductive film and the gate electrode by processing after forming the third conductive film.

[0037]

According to the first and third aspects of the present invention, the width of the gate electrode is larger than that of the gate insulating film as compared with the conventional device having the same gate area as the gate insulating film. Is also widely formed. Therefore, the resistance of the gate electrode can be reduced without increasing the design rule. Further, when the silicide film is formed on the surface, the generation of the thin line effect is suppressed.

Further, by taking the above means, the second aspect of the present invention is to provide a structure in which both ends of the third conductive film formed on the semiconductor substrate extend over the sidewall insulating film and the element isolation. Become. Therefore, even if some over-etching is performed when patterning the third conductive film, only a recess is formed in the sidewall insulating film and element isolation. Therefore, there is no problem of forming a recess on the substrate surface unlike the conventional technique,
It does not affect the operating characteristics of the device such as the occurrence of leakage current.

When a silicon film is used for the third conductive film and a metal silicide film is formed on the surface of the third conductive film, the metal does not enter the substrate and does not come close to the junction of the source / drain regions. It is possible to completely suppress the generation of leak current while achieving resistance.

A silicon film is used for the first conductive film, a metal silicide film is formed on the surface of the first conductive film, and the third conductive film is a film that can withstand the process of forming the metal silicide film. It is possible to use a metal silicide material that produces less effect for the gate electrode or to make the silicide film of the gate electrode thick. Further, although it is not suitable for the gate electrode due to a problem such as a thin wire effect, it is possible to use a metal silicide film material suitable for the source / drain regions from the viewpoint of resistance reduction, and the material selectivity is widened. Problems such as low resistance are improved in the entire device.

By taking the above means, the third aspect of the present invention can be obtained.
As in the second aspect, the problem of the concave portion of the substrate as described above does not occur, and the characteristics of the device are not affected. Further, when the silicide film is formed on the surface, it can be formed sufficiently thick.

In the second and third aspects of the present invention described above, at least a part of the contact portion which is to be the wiring of the upper layer of the third conductive film is formed on the above-mentioned element isolation, and the source / drain region has a contact width. If the width is not more than sufficient, it is possible to suppress the junction capacitance.

The sidewall insulating film is formed with a width equal to or more than the processing limit for separating the second and third conductive films, so that the second and third conductive films do not completely form a recess on the substrate surface. It is prevented.

Since the third conductive film is used as the first layer wiring, the number of laminated layers can be reduced by one layer. further,
By adopting the above means, the fourth and second conductive films of the present invention can be collectively formed, and a good device can be formed without increasing the number of steps.

Further, by forming the side wall insulating film having a predetermined width in this device in a divided manner, the distance between the dense source / drain region and the gate electrode can be adjusted to a desired width. Furthermore, by using the sidewall conductive film, it is possible to reduce the resistance of the source / drain regions, and when the sidewall conductive film is used as the solid-phase diffusion source of the source / drain, a shallow source / drain diffusion layer can be formed, which is short. Effective in suppressing the channel effect.

[0046]

Embodiments of the present invention will be described below. FIG. 1 is a completed plan view of a MOSFET which is a first embodiment of the present invention. In the present embodiment, the second conductive film 48b is formed so as to extend from above the first conductive film 45 to a part of the sidewall insulating film 47 and has a width wider than that of the first conductive film 45. . The first conductive film 45 is formed with the same width as the gate insulating film and defines the channel length. Therefore, it is possible to increase the gate width and reduce the resistance while reducing the channel length. Furthermore, by forming a metal silicide film on the surface of the second conductive film 48b, it is possible to prevent an increase in resistance due to the thin line effect.

The third conductive film 48a is formed so that both ends thereof extend on the sidewall insulating film 47 and the element isolation 42d. Therefore, even if over-etching is performed when patterning the third conductive film, the substrate surface is not etched and the operation of the device is not affected.

Further, the third conductive film 48a is formed by the element isolation 42.
The source / drain electrodes are contacted with each other in the region including the element isolation 42, and the width of the source / drain diffusion layer on the substrate surface is not formed as wide as necessary for the contact. It is possible to minimize the RC delay caused by the junction capacitance between the diffusion layer and the substrate.

Further, since no recess is formed on the surface of the substrate, it is possible to secure a sufficient distance from the junction interface of the source / drain diffusion layer of the substrate if the metal silicide film is not formed on the third conductive film. It is also possible to suppress the leak current generated when the junctions are close to each other. Therefore, the metal silicide film can be formed relatively thick. For example, even with a material such as Ni, which is known to deeply penetrate by heat treatment during silicidation, the problem of leak current can be suppressed.

Similar effects can be obtained when the side wall insulating film 47 is a double side wall made of a conductive film. Figure 2
(E) is a sectional complete view of the MOSFET of the present embodiment.

As described above, the gate electrode 48b is formed in a T shape, and the upper portion of the gate electrode 48b is wider than the gate insulating film 44, and the resistance of the gate electrode can be reduced although the design rule is the same as the conventional one. I understand.

The second conductive film is formed so as to extend over the sidewall insulating film and the element isolation. Therefore, no recess is formed on the substrate surface due to over-etching when etching the second conductive film.

A sufficient area of the source / drain region is secured by placing a low resistance film on the substrate 41.
It is sufficient to form a shallow diffusion layer. Therefore, a sufficient source / drain region can be secured while avoiding a problem such as a leak current due to the deep diffusion layer.

Since the cross-sectional area of the current can be wide,
Low resistance can be measured. The method for manufacturing the FET of this embodiment will be described below with reference to FIGS.

First, an element isolation 42 is formed on a silicon substrate 41 by the LOCOS method, p-type ion implantation for a well is performed, and an oxide film for a gate insulating film is formed by thermal oxidation. Then, a polysilicon film for a gate electrode is formed to a thickness of 300 nm by the CVD method or the like. After that, the gate electrode 45 and the gate oxide film 44 are formed using the resist pattern formed by the lithography process as a mask. After that, using this gate electrode as a mask, FIG.
Thin source / drain regions 46a as shown in FIG.
Ion implantation for implantation energy 20 kev, dose 3
Perform at +10 ¹⁴ cm ^-2 .

Next, a Si ₃ N ₄ film is formed into a 4 by CVD method or the like.
The sidewall Si ₃ N ₄ film 47 is formed by depositing it to a thickness of 00 nm and performing etching by the RiE method or the like.
When the SiN film is formed, its width is formed to a required width by controlling the film thickness and etching time. Then, using the side wall Si ₃ N ₄ film 47 as a mask, ion implantation for the dense source / drain diffusion layer 46b is performed with an implantation energy of 40 kev and a dose amount of 3 × 10 ¹⁵ cm.
Set it to ^-2 . After that, the impurities introduced by the RTA method or the like are activated to form a source / drain diffusion layer 46 as shown in FIG. 2B.

Subsequently, as shown in FIG. 2C, the substrate 4
A polysilicon film 48 having a thickness of 20 nm is formed on one surface by a CVD method or the like, and a resist pattern 49 is formed as a mask by a photolithography process. Of this resist pattern, for the gate electrode, the polysilicon film 48b to be formed is formed so as to extend from the gate electrode 45 to a part of the sidewall SiN film 47. For the polysilicon film 48a on the source / drain region 46, the side wall Si ₃ N _{4 is used.}
The polysilicon film 48a formed over part of the film 47 to the surface of the substrate 41 and on the element isolation 42 is formed.

Then, the polysilicon film 48b for the gate electrode and the polysilicon film 48a for the source / drain regions are formed by etching by the RiE method using the resist pattern 49a as a mask. At this time, the side wall S
The i ₃ N ₄ film 47 and the polysilicon film 48 can be sufficiently selected, and the substrate surface is exposed, so that the substrate is deeply etched as in the conventional case, and the depth of the diffusion layer due to the subsequent ion implantation is deep. It never happens. Then, the metal for the silicide film is accumulated on the surface and heat-treated to form the metal silicide films 52a and 52b.

Then, the S film having a film thickness of 30 nm is formed on the surface of the substrate 41.
The iO ₂ film is accumulated by a CVD method or the like, an opening for contact is formed on the element isolation 42, and metal wirings 51a and 51b are formed.
Are formed to complete the semiconductor device of this embodiment shown in FIG.

In this embodiment, the side wall S having a width wider than that of the conventional one.
Since the i ₃ N ₄ film 47 is formed at one time, the dense source / drain diffusion layer 43 is formed at a position apart from the gate insulating film 44. For this reason, there is concern about the driving force of the device, but instead of forming the side walls collectively, the formation is divided twice or more to form a narrow side wall, and then a deep source. Ion implantation for the drain diffusion layer, then
By forming the sidewall Si ₃ N ₄ film having a required width, it is possible to obtain a large driving force while suppressing the occurrence of the short channel effect. In addition, the polysilicon film 48a is relatively RI.
It is a film having no selectivity with respect to Si ₃ N ₄ in the E step, and even if Si ₃ N ₄ is deeply etched by overetching, it does not affect the device characteristics.

Next, a second embodiment of the present invention will be described with reference to FIG. The gate electrode of this embodiment is made of a polysilicon film 45 and has a NiSi film 52b on its surface. Since the NiSi film 52b is not formed by salicide at the same time as the source / drain regions, it is not restricted by the leak current and is formed thicker than the conventional one, so that it is a low resistance film.

The third conductive film in this embodiment is WS.
It consists of i. The manufacturing method of the present embodiment will be described below with reference to FIG.
It demonstrates using (e). However, FIG. 3 (a), (b)
Up to the point, can be performed in the same manner as in the first embodiment,
A description of the steps and detailed description of reference numerals will be omitted.

The third conductive film shown in FIG. 3C is a WSi film 48, which is deposited on the surface of the substrate 41 by the CVD method. After this, as shown in FIG. 3C, the resist pattern 49
Are formed so as to extend over the sidewall insulating film 47 and the element isolation 42.

Subsequently, as shown in FIG. 3D, the WSi film 60 is RiE with the resist pattern 60 as a mask.
Formed by the above method, Ni is deposited on the surface for the metal silicide film of the gate electrode, and heat treatment is performed to obtain NiSi.
The film 52b is formed.

In the present embodiment, as described above, by forming the metal silicide film of the gate electrode separately from the source / drain regions, the silicide film for the gate electrode can be formed relatively thick. Therefore, it is possible to prevent the generation of the thin line effect peculiar to the gate electrode, and it is possible to significantly reduce the resistance.

In such a manufacturing method, WSi does not react with Ni, and WSi is used for the treatment with an acid necessary for NiSi film formation.
It has become possible because Si can withstand. Then, FIG.
As shown in (e), the interlayer insulating film 50 is deposited by the CVD method, an opening for contact is provided, and the electrodes 51a and 5 are formed.
1b is formed, and the semiconductor device of this embodiment is completed.

For the third conductive film in this embodiment, MoSi ₂ or the like can be used in addition to WSi. Further, the metal silicide film of the gate electrode may be Pt, Co, Ti, etc. in addition to Ni.

If attention is paid only to lowering the resistance of the gate electrode, it is possible to form the source / drain electrodes on the surface of the semiconductor substrate by forming only the second conductive film and not using the third conductive film. Is.

The present invention is not limited to the above embodiment,
It can be widely applied without departing from the spirit of the present invention. In the present embodiment, the third conductive film 48a is formed such that both ends thereof extend on the sidewall conductive film 47a and the element isolation 42d. Therefore, even if over-etching is performed when patterning the third conductive film, the substrate surface is not etched and the operation of the device is not affected.

Further, the third conductive film 48a is formed by the element isolation 42.
The source / drain electrodes are contacted in a region including the element isolation region 42 and the source / drain diffusion layers on the substrate surface are not formed as wide as necessary for the contact. It is possible to minimize the RC delay caused by the junction capacitance between the drain diffusion layer and the substrate.

Furthermore, since no recess is formed on the surface of the substrate, a metal silicide film formed on the third conductive film can secure a sufficient distance from the junction interface of the source / drain diffusion layers of the substrate. It is also possible to suppress the leak current generated when the junctions are close to each other. Therefore, the metal silicide film can be formed relatively thick. For example, even with a material such as Ni, which is known to deeply penetrate by heat treatment during silicidation, the problem of leak current can be suppressed. Further, the sidewall conductive film needs to be formed with a width equal to or larger than the distance required to separate the third conductive film, but the resistance of the source / drain does not increase. If the solid-phase diffusion source is used, shallow source / drain diffusion layers can be formed.

The third conductive film is formed so as to extend over the sidewall conductive film and the element isolation. Therefore, no recess is formed on the substrate surface due to overetching when etching the third conductive film.

A sufficient area of the source / drain region is secured by placing a low resistance film on the substrate 48a.
It is sufficient to form a shallow diffusion layer for No. 1. Therefore, it is possible to secure a sufficient source / drain region while avoiding a problem such as a leak current due to the deep diffusion layer.

Since the cross-sectional area of the current can be wide,
Low resistance can be measured. Hereinafter, a method of manufacturing the FET of this embodiment will be described with reference to FIGS.

First, an element isolation 42 is formed on a silicon substrate 41 by the LOCOS method, p-type ion implantation for a well is performed, and an oxide film for a gate insulating film is formed by thermal oxidation. Then, a polysilicon film for a gate electrode is formed to a thickness of 300 nm by the CVD method or the like. After that, the gate electrode 45 and the gate oxide film 44 are formed using the resist pattern formed by the lithography process as a mask. After that, using this gate electrode as a mask, FIG.
Thin source / drain regions 46a as shown in FIG.
Ion implantation is performed with an implantation energy of 20 kev and a dose amount of 3 × 10 ¹⁴ cm ⁻² .

Next, a Si ₃ N ₄ film is formed into 2 by the CVD method or the like.
The sidewall Si ₃ N ₄ film 47 is formed by depositing it to a thickness of 0 nm and performing etching by the RiE method or the like. Further, a polysilicon film is deposited to a thickness of 300 nm, and R
The sidewall polysilicon film is formed by performing the IE method. Then, using the side wall POS silicon 47a as a mask, ion implantation for the dense source / drain diffusion layer 46b is performed with an implantation energy of 40 kev and a dose amount of 3 × 10 ¹⁵ c.
Set it as m ^-2 . Thereafter, the impurities introduced by the RTA method or the like are activated to form the source / drain diffusion layers 46 as shown in FIG. 4B, and at the same time, the impurities are implanted into the sidewall polysilicon film 47a.

Subsequently, as shown in FIG. 4C, the substrate 4
A WS film 48 having a thickness of 20 nm is formed on one surface by a CVD method or the like, and is formed by a photolithography process using the resist pattern 49 as a mask. This resist pattern is formed such that the upper polysilicon extends from a part of the sidewall polysilicon film 47a to the surface of the substrate 41, and the WS film 48a formed on the element isolation 42 extends.

Then, by etching by the RIE method using the resist pattern 49a as a mask, the source
The WS film 48a for the drain region is used. At this time, even if the sidewall polysilicon film 47 is over-etched during the processing of the WS film 48, the substrate surface is exposed, so that the substrate is deeply etched, and the depth of the diffusion layer due to the subsequent ion implantation becomes deep. There is no.

Then, the S film having a film thickness of 30 nm is formed on the surface of the substrate 41.
The iO ₂ film is accumulated by a CVD method or the like, an opening for contact is formed on the element isolation 42, and metal wirings 51a and 51b are formed.
Are formed to complete the semiconductor device of this embodiment shown in FIG.

In this embodiment, the shallow source / drain is formed by ion implantation, but the shallow source / drain can be formed by solid phase diffusion from the side wall, and the process can be simplified.

Further, by over-etching the sidewall polysilicon film 47a using the WS film 48a as a mask, it is possible to reduce the capacitance formed between the sidewall polysilicon film and the gate electrode.

[0082]

According to the present invention, it is possible to provide a semiconductor device in which the resistance of the gate electrode is reduced and the suppression of the leak current and the reduction of the diffusion layer capacitance can be achieved at the same time while the device is miniaturized. It will be possible.

[Brief description of drawings]

FIG. 1 is a plan view showing a first embodiment of the present invention.

2A to 2D are cross-sectional views for each step showing a method for manufacturing the first embodiment of the present invention.

3A to 3D are cross-sectional views for each step showing a method for manufacturing a second embodiment of the present invention.

4A to 4C are cross-sectional views for each step showing a method for manufacturing a conventional semiconductor device of the present invention.

5A to 5C are cross-sectional views for each step showing a method of manufacturing another conventional semiconductor device of the present invention.

[Explanation of reference numerals] 1,41 ... Silicon substrate 2, 42 ... Isolation between elements 3, 13 ... Well 4 ... Oxide film 4a, 44 ... Gate insulating film 5, 15, 48 ... Polysilicon film 6, 16, 49 ... Resist Patterns 5a, 45, 48b ... Gate electrodes 6a, 46a ... Thin source / drain diffusion layers 6a, 46b ... Dark source / drain diffusion layers 6 , 18 ... Source / drain diffusion layers 7, 47 ... Side wall SiN film 47a ... Side wall polysilicon Films 8, 52a, 52b ... Metal silicide films 9, 50 ... Interlayer insulating films 10, 51a, 51b ... Metal wirings 15a, 48a ... Source / drain regions 17 ... Over-etched substrate 18a ... Deeply formed source / drain diffusion Layer 48a ... Source / drain region 48b ... Gate electrode 51a ... Source / drain contact 51b ... Gate Electrode contact

Claims (22)

[Claims] 1. A semiconductor substrate having a gate insulating film formed on a surface thereof, a first conductive film formed on the gate insulating film to serve as a gate electrode, and both side portions of the first conductive film. A first side wall insulating film to be formed, and a gate electrode formed by extending from a surface of the first conductive film to a part of the surface of the first side wall insulating film on the first conductive film side. And a source / drain diffusion layer formed on the surface of the semiconductor substrate. 2. The semiconductor device according to claim 1, wherein the second conductive film is a silicon film, and a metal silicide film is provided on a surface of the silicon film. 3. A semiconductor substrate having a gate insulating film formed on a surface thereof, a first conductive film formed on the gate insulating film and serving as a gate electrode, and formed on both sides of the gate electrode. A first sidewall insulating film, a device isolation region for separating adjacent devices, and a part of the sidewall insulating film are formed so as to extend to the surface of the semiconductor substrate and the device isolation. A third conductive film, a source formed on at least the surface of the third conductive film, and the surface of the semiconductor substrate;
A semiconductor device comprising: a drain region. 4. The semiconductor device according to claim 3, wherein the first and third conductive films are silicon films, and the same metal silicide film is formed on each surface thereof. 5. The first conductive film is a silicon film, a metal silicide film is formed on the surface thereof, and the third conductive film is the metal forming the metal silicide film on the surface of the first conductive film. 4. The semiconductor device according to claim 3, which is a metal silicide film having different metals as constituent elements. 6. A semiconductor substrate having a gate insulating film formed on a surface thereof, a first conductive film formed on the gate insulating film to serve as a gate electrode, and on both sides of the first conductive film. A sidewall insulating film to be formed, element isolation for separating adjacent elements, a surface of the first conductive film, and a part of the first sidewall insulating film on the side of the first conductive film A second conductive film that extends over the surface and serves as a gate electrode, and a portion of the sidewall insulating film on the semiconductor substrate side where the surface is exposed are separated from the surface of the semiconductor substrate and the element isolation. A third conductive film formed so as to extend upward, and the third conductive film.
And a source / drain region formed on at least the surface of the third conductive film of the semiconductor substrate. 7. The semiconductor device according to claim 6, wherein the second and third conductive films are silicon films, and the same metal silicide film is formed on the surfaces thereof. 8. The first sidewall insulating film is formed of the second and third insulating films.
7. The semiconductor device according to claim 6, wherein the semiconductor device is formed with a width equal to or larger than a processing limit width for separating the conductive film. 9. The semiconductor device according to claim 3, wherein at least a part of a contact portion which is a wiring of an upper layer of the third conductive film is formed on the element isolation. 10. The semiconductor device according to claim 3, wherein a width of the source / drain region sandwiched by the first sidewall insulating film and element isolation is narrower than a processing limit. 11. The semiconductor device according to claim 3, wherein the third conductive film is used as a first layer wiring. 12. A step of forming a gate insulating film on a semiconductor substrate, a step of forming a first conductive film on the gate insulating film, a sidewall of the gate insulating film and the first conductive film. First
A side wall insulating film, a step of forming an element isolation for separating adjacent elements, a surface of the first conductive film, and a part of the first conductive film side of the first conductive film. The second conductive film extends to the surface of the side wall insulating film, and the exposed part of the surface of the side wall insulating film on the side of the semiconductor substrate extends above the surface of the semiconductor substrate and the element isolation. And a step of forming a source / drain region on at least the surface of the third conductive film among the surface of the third conductive film and the surface of the semiconductor substrate. And a method for manufacturing a semiconductor device. 13. The method of manufacturing a semiconductor device according to claim 11, wherein the first sidewall insulating film is formed with a width equal to or larger than a processing limit for separating the second and third conductive films. 14. The method of manufacturing a semiconductor device according to claim 11, wherein thin source / drain regions are formed after forming the first conductive film. 15. A mask for forming a source / drain region that is darker than the source / drain region, adjacent to the thin source / drain region on the surface of a semiconductor substrate after forming the thin source / drain region. In order to use, the step of forming a part of the first sidewall insulating film while controlling the width thereof, and forming the rest of the sidewall insulating film before forming the third conductive film. 15. The method for manufacturing a semiconductor device according to claim 14. 16. The method of manufacturing a semiconductor device according to claim 12, wherein the sidewall conductive film is formed of a polycrystalline or amorphous silicon film. 17. The method of manufacturing a semiconductor device according to claim 16, wherein the sidewall conductive film is recrystallized. 18. The method of manufacturing a semiconductor device according to claim 16, wherein the sidewall conductive film contains impurities. 19. The method of manufacturing a semiconductor device according to claim 18, wherein the sidewall conductive film is used as a solid phase diffusion source. 20. A method of manufacturing a semiconductor device, wherein the capacitance between the sidewall conductive film and the gate electrode is controlled by processing after forming the sidewall conductive film. 21. A semiconductor substrate having a gate insulating film formed on a surface thereof, a first conductive film formed on the gate insulating film to serve as a gate electrode, and formed on both sides of the gate electrode. The second sidewall insulating film, the sidewall conductive film formed on both sides of the sidewall insulating film, the element isolation region for separating between adjacent elements, and a part of the sidewall conductive film from the semiconductor. A third surface formed to extend to the surface of the substrate and the element isolation region
Of the conductive film, the third conductive film, and the source formed on at least the surface of the third conductive film among the surfaces of the semiconductor substrate.
A semiconductor device comprising: a drain region. 22. A solid-phase diffusion source for a source / drain diffusion layer by implanting impurities of the same conductivity type as the source / drain diffusion layer into the sidewall conductive film. Semiconductor device.