GB2360128A - Method of making semiconductor device with salicide electrode - Google Patents

Method of making semiconductor device with salicide electrode Download PDF

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Publication number
GB2360128A
GB2360128A GB0113671A GB0113671A GB2360128A GB 2360128 A GB2360128 A GB 2360128A GB 0113671 A GB0113671 A GB 0113671A GB 0113671 A GB0113671 A GB 0113671A GB 2360128 A GB2360128 A GB 2360128A
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layer
semiconductor device
forming
polysilicon
silicide
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GB0113671A
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GB0113671D0 (en
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Water Lur
Tony Lin
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to GB0113671A priority Critical patent/GB2360128A/en
Priority claimed from GB9625264A external-priority patent/GB2320134A/en
Publication of GB0113671D0 publication Critical patent/GB0113671D0/en
Publication of GB2360128A publication Critical patent/GB2360128A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/66583—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H01L29/66598—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

Abstract

Salicide (self-aligned silicide) electrodes are formed using a process that does not require oxide spacer structures alongside polysilicon gate electrodes and wiring lines. The process comprises forming insulating layer (56) over semiconductor substrate (10), forming a shaped polysilicon structure (58) with laterally extending protrusions (62) over insulating layer (56), and depositing metal layer (70) (e.g. titanium) over the polysilicon structure (58), preferably by physical vapour deposition, and annealing the metal layer (70), preferably by rapid thermal annealing at about 700{ for 10 to 120 seconds to produce metal silicide layer (74, Fig. 15). The polysilicon structure (58) can be the electrode of a MOS transistor, where lightly-doped source and drain regions (64) are formed by ion implantation with the protrusions (62) acting as a mask for the implantation. Gate electrodes (58) and wiring lines (60) fabricated by this method have lower stress in the silicide layers, producing salicide structures having lower resistance than gate electrodes and wiring lines formed using conventional salicide techniques.

Description

2360128
Background of the Invention.
1 Field of the Invention.
The present invention relates to semiconductor devices incorporating electrodes consisting of a layer of polysilicon covered by a self-aligned layer of metal silicide.
2. Description of the Related Art.
As line widths and geometries for semiconductor devices are made smaller, the polysilicon electrodes that form the gates of MOS devices and wiring lines within semiconductor devices become undesirably resistive. Multilayer electrodes in which a layer of polysilicon is covered by one or more layers of metals or metal silicides are used to provide electrodes having a lower resistance than electrodes consisting solely of polysilicon. Silicide electrodes may consist, for example, of a layer of polysilicon having a thickness of approximately 1000 A to 3000A covered by titanium silicide to a thickness of greater than 100 A.
1 A typical implementation of such a multilayer electrode is the so-called self-all-ned silicide structure, illustrated in idealized form in Figs. 1-4. Figs. 1-4 show cross-sectional views of MOS devices at an early stage of manufacture. The illustrated MOS devices are formed on a P-type substrate 10 and include thick field oxide regions 12 to provide isolation from other, adjacent
MOS devices. A gate oxide layer 14, formed by thermal oxidation, covers the active device region of the illustrated device and a polysilicon gate electrode 16 is formed on the gate oxide layer 14. The polysilicon gate electrode 16 is formed by depositing a layer of undoped polysilicon over the substrate, typically using low pressure chemical vapor deposition (LPCVD), implanting and activating impurities into the polysilicon to render it conductive, and patteming the polysilicon using photolithography. Polysilicon wiring line 18 is formed on the field oxide region
12 at the same time as the gate electrode 16.
Doped source/drain regions 20 are formed on either side of the polysilicon gate electrode to define the channel region of the illustrated MOS transistor. Generally, a lightly doped drain (LDD) structure is used in small design rule MOS transistors of the type that are primarily used in modem memory and logic devices. LDD source/drain regions 20 are typically formed in a two step process, beginning with a relatively low level dopant implantation made self-aligned to a polysilicon gate electrode 16 as illustrated in Fig. 1. Subsequently, spacer oxide regions 22 (Fig.
2) are formed on either side of the gate electrode by first depositing a layer of CVD oxide over the Fig. 1 structure and then anisotropically etching back the oxide layer to expose the substrate over the source/drain regions 20. Etching back the CVD oxide layer produces the spacer oxide regions 22 on either side of the polysilicon gate electrode 16. This process also provides spacer regions 24 on either side of the polysilicon wiring line 18, if the wiring line 18 is exposed during 2 the oxide deposition and etch back process. After the spacer oxide regions 22 are provided on either side of the polysilicon gate electrode 16, a second, heavier ion implantation is made into the source/drain reelons 20 self-allened to the spacer oxide regions 22 (not shown).
The structure illustrated in Fig. 2 includes a polysilicon gate electrode 16 and a polysilicon wiring line 18. For smaller line widths, even highly doped polysilicon is sufficiently resistive to diminish the performance of MOS circuits due to decreased signal levels and longer RC time constants. To reduce the resistance of these gate electrodes and wiring lines, further processing of the Fig. 2 device continues to convert the gate electrode 16 and wiring line 18 into silicide structures using self-aligned silicide (salicide) techniques. Although a variety of different silicides are known to be acceptable, the silicide most commonly used at this time is titanium silicide, and that structure is described herein. Referring now to Fig. 3, silicide lines are formed by first sputtering a layer of titanium over the surface of the device to a thickness of, for example, 500 A.
This titanium layer 26 is converted into titanium silicide at the surface of the polysilicon layers 16, 18 and at the exposed portions of the substrate, including the source/drain regions 20, in a two step process. In the first process step, the device is subjected to a rapid thermal anneal (RTA) by heating the device to a temperature of up to about 70CC for about thirty seconds, converting the titanium layer 26 into titanium silicide (nominally TiSi2) where the titanium layer is in contact with a silicon (crystalline or polycrystalline) surface. The device is then etched using a wet etch consisting of H.202 and NH,OH diluted in water, removing unreacted titanium from the surface of the device, exposing the oxide regions of the device. Layers of titanium silicide 30, 32 are left over the polysilicon. gate electrode 16 and over the wiring line 18. When the sourceldrain regions are exposed during the silicidation process, titanium silicide regions 34 are also formed on the 3 surface of the source/drain regions 20. Such titanium silicide regions 34 provide lower sheet resistance over the sourceldrain regions and provide better contacts to the source/drain regions 20. Titanium silicide contacts on the source/drain regions are thus preferred so long as the amount of silicon consumed in the silicidation process does not alter the gate performance or result in excessive Junction leakage at the source/drain regions.
After the unreacted titanium is etched from the device, further processing is necessary to provide suitable self-aligned silicide (salicide) structures for the gate electrodes and wiring lines of the device. The process steps described to this point form a relatively ffigh resistivity phase of titanium silicide on the silicon surfaces, so that the illustrated salicide structure does not have as low of resistivity as is desirable. It is accordingly necessary to expose the device to a second rapid thermal anneal at a temperature in excess of 8OWC for at least ten seconds to convert the titanium silicide to the lower resistivity phase of titanium silicide. The device is then subjected to further processing to complete the fabrication.
A number of the processing steps necessary to the formation of salicide structures are critical. For example, if the temperature control is poor for the initial RTA step of converting the titanium in contact with silicon to titanium silicide, then it is possible that the temperature of the device may get high enough for rapid silicon transport laterally along the titanium layer (26 in Fig.
3), which could convert titanium to titanium silicide in undesirable regions. For example, if silicon is transported along the portion of the titanium layer extending over the oxide spacers 22 on either side of the gate electrode 16, then a "stringer" may be formed bridging between the gate electrode and the source/drain regions 20. Such a stringer 36 bridging between the gate silicide layer 30 and the source/drain silicide region 34 is illustrated in Fig. 5. The formation of the Fig. 5 4 structure is obviously undesirable in that it shorts the gate to the source/drain region and renders the transistor inoperative.
For smaller device geometries, gate electrodes and wiring lines become narrower and It becomes increasingly more necessary to provide sufficiently low resistivity gate electrodes and wiring lines within memory and logic devices. On the other hand, as narrower gate electrodes and wiring lines are implemented, it is increasingly more difficult to form appropriate salicide electrode structures. In panicular, it is difficult to provide the low resistivity phase of titanium silicide for narrow line width gate electrodes and wiring lines. It is accordingly desirable to develop better designs and more robust processing techniques for forming low resistance salicide structures.
Brief Description of the Drawings.
Figs. 1-4 illustrate the process steps for forming a salicide structure in accordance with conventional teachings.
Fig. 5 illustrates a stringer formed on a transistor, shorting the gate to the drain of the transistor.
Fig. 6 illustrates a difficulty in producing acceptable salicide structures.
Figs. 7-15 illustrate stages in the manufacture of MOS devices incorporating salicide structures in accordance with the present invention.
a of sE circuits Ix[ w3=diT tD the netr-d of tl-e p knenticin c-ire briefly sxarari2ed bakw.
A first example provides a semiconductor circuit having a wiring line and a MOS device incorporating a gate electrode. The MOS device is formed over a semiconductor substrate. Each of the wiring line and the gate electrode have a salicide structure comprising a polysilicon lower layer having sidewalls and a layer of metal silicide overlying the polysilicon lower layer and extending laterally beyond each of the sidewalls of the polysilicon lower layer.
Another example provides a semiconductor circuit comprising a semiconductor substrate, a layer of insulating material on the sedconductor substrate, and a polysilicon structure on the layer of insulating material formed to have two sidewalls extending above the semiconductor substrate. A layer of conductive material is formed on the polysilicon structure extending laterally beyond both sidewalls of the polysilicon structure.
Still another exarriple provides a semiconductor circuit comprising a semiconductor substrate and a layer of insulating matefial on the semiconductor substrate. A polysilicon structure is formed on the layer of insulating material so as to have two sidewalls extending above the semiconductor substrate. A layer of conductive material on the polysilicon structure extends laterally beyond both sidewalls of the polysilicon structure, and a first LDD source/drain region formed within the semiconductor substrate having a first lightly doped region and a first heavily doped region, the first lightly doped region having a boundary adjacent to a lower edge of a first one of the sidewalls of the polysilicon structure and the first heavily doped region having a boundary formed self aligned to a first edge of the layer of conductive material.
6 A f irst aspect of the present invention includes a method of forming a semiconductor device including a MOS transistor, including the steps of forming an insulator on a semiconductor substrate and forming a shaped polysilicon electrode on the insulator, the shaped polystlicon electrode having protrusions extending laterally over the semiconductor substrate. The method includes the further steps of forming, by ion implantation, LEID source/drain regions within the substrate on either side of the shaped polysilicon electrode using the protrusions of the shaped polysilicon electrode as a mask for the ion implantation to define the LDD source/drain region dopant distribution, and forming a metal silicide layer over the shaped polysilicon electrode.
For a particularly preferred embodiment of this aspect of the invention, the step of forming the shaped polysilicon electrode structure includes the steps of depositing a first layer of masking material on the semiconductor device and a second layer of masking material on the first layer of masking material and forriling an opening by removing a portion of the first and the second layers of masking material. The second layer of masking material is etched laterally so that the opening is wider at the second layer than at the first layer. Polysilicon is deposited within the opening and the first and second layers of masking material are removed.
Another aspect of the invention provides a method of making a semiconductor device by providing a semiconductor substrate and providing a layer of insulating material over at least a portion of the semiconductor substrate. A shaped polysilicon structure is formed over the layer of insulating material, the shaped polysilicon structure having protrusions extending laterally over a surface of the semiconductor substrate. A metal layer is deposited on the shaped polysilicon structure and the semiconductor device is annealed to produce a layer of metal silicide on the shaped polysilicon structure.
7 Detailed Description of the Preferred Embodimenis.
Preferred embodiments of the present invention form semiconductor devices incorporating salicide (self-aligned silicide) structures in a process that preferably does not form oxide spacer structures alongside the polysilicon gate electrodes and wiring lines. Rather, a shaped polysilicon gate electrode is formed having an upper surface that can be converted to a silicide such as titanium silicide. The shaped polysilicon electrode preferably includes protrusions that extend away from the body of the electrode and extend over the silicon substrate. The polysilicon gate electrode may, for example, have a cross section in the shape of a "t". By first performing low dopant level ion implantation at an angle to reach the substrate regions shadowed by the protrusions from the gate electrode, an appropriate light ion implantation can be made for the source/drain regions. A subsequent, high dopant level ion implantation is made using an implantation direction perpendicular to the surface of the substrate so that the protrusions extending from the gate electrode act as a mask for the Wgh dopant level ion implantation that completes the sourceldrain structure. In this way, a lightly doped drain (LDD) type structure can be formed for both of the sourceldrain regions without using spacer oxide regions. Gate electrodes and wiring lines having this structure are more consistently of a higher quality, and generally have lower resistance than gate electrodes and wiring lines formed using conventional salicide techniques.
The present inventors believe that the observed improvements in salicide electrode and wiring line formation and performance achieved by using preferred embodiments of the present invention relate to forming the salicide structure so that the silicide layer of the gate electrode is grown in such a manner as to have a low level of stress. It becomes increasingly difficult to form 8 acceptable low resistivity salicide electrodes and wiring lines when these structures are made using polysillcon lines that are less than one half micron across. In particular, the resistivity of cate electrodes and wiring lines rises precipitously for line widths of less than one half micron.
The increase in the resistivity for smaller line widths reflects the fact that the second annealing step conventionally used to produce the low resistivity phase of silicide can be ineffective for such narrow line widths. To understand why this happens, it is useful to consider a more realistic model of what happens during the formation of conventional salicide structures.
Fig. 6 illustrates a mechanism that is believed to explain the difficulty in converting silicide layers formed on narrow line width polysilicon layers to the low resistivity silicide phase. Fig, 4, discussed above, shows a well defined titanium silicide layer extending uniformly across a polysilicon gate electrode. This is an idealized representation of what is produced during the rapid thermal anneal that converts titanium in contact with a layer of silicon into a layer of titanium silicide. The inventors have observed that this process step more typically forms a titanium silicide structure 3 8 such as that illustrated in Fig. 6. Near the edge of the polysilicon gate electrode, the gate oxide spacers 22 appear to "clamp" the edges of the titanium silicide layer 38, linting the growth of the titanium silicide layer which typically must expand to a thickness greater than the silicon layer consumed during the growth process. Thus, titanium silicide grows most freely near the center of the gate electrode so that the thickest part of the titanium silicide layer 38 is formed above the center of the polysilicon gate electrode 16. Titanium silicide along the edges of the layer 38 has a high level of stress, as it is formed, while the more central portion of the titanium silicide has a relatively lower level of stress. If the width of the titanium silicide layer 3 8 is sufficiently small, then a considerable level of stress will exist even at the center of the 9 1 flicide layer 3) 8. If too high of a stress level exists across the entire titanium silicide]aver t tall urn st I as it is formed, then a subsequent annealing step may not be successful in converting enough of the titanium silicide layer 38 to the low resistivity phase. A salicide structure in which the as grown silicide layer has too high of a level of stress may thus produce an undesirably resistive salicide structure which is poorly suited for use as a gate electrode or a wiring line.
The present inventors accordingly believe that, at least for small line widths, it is desirable to form salicide structures using silicide layers having a reduced stress level. Salicide structures that are formed incorporating a reduced stress silicide layer and a preferred method of making such structures are now described with reference to Figs. 7-15. While these figures illustrate particularly preferred embodiments of the present invention within MOS transistors and wiring lines in a particular configuration of a semiconductor device, embodiments of the present invention can be used to form gate electrodes and wiring lines in a wide variety of serrconductor devices. In addition, while the description of the following embodiments emphasizes the formation of NMOS devices, salicide structures in accordance with the present invention may be implemented to advantage in PMOS devices as well. This is true whether the polysilicon of the PMOS gate is doped N-type or P-type. Although it is possible to use the salicide structure described herein only for the gate electrodes (or, conversely, only for the wiring lines) of a device, it is presently believed that it is most desirable to use the described sallicide structure for all of the first level polysilicon lines, at least for those devices in which high conductivity electrodes and wiring lines are desirable.
Fig. 7 illustrates in cross section a small portion of a semiconductor circuit incorporating a MOS device at an early stage in the manufacturing process. A P-type substrate 10 is provided and device isolation reeions such as field oxide regions 12 are provided as necessary. A pad oxide is grown thermally or deposited by chemical vapor deposition (CVD) over the active device regions of the device to a thickness of between about 50 to 300k The channel threshold adjust implantation is then performed in the typical manner using, for example, boron or boron fluoride ions for NMOS devices or, for example, arsenic or phosphorus ions for PMOS devices to a dose of between about 3 x 10 " ions/c M2 to about 5 x 1013 lonS/CM2 at an energy of between about 5 to KeV. Next, a series of layers of material are deposited at least over the regions of the device where salicide gate structures and wiring lines are to be formed. The series of layers will be patterned into a form or mask structure to be used in forming a shaped polysilicon line which will undergo further processing to form a salicide structure. As such, it is possible to use a variety of different combinations of layers to provide the desired form or mask structure. In a preferred embodiment, a layer 42 of silicon nitrideS'3N, is deposited first, a layer 44 of silicon oxideS'02 'S deposited next, and then a second layer 46 of silicon nitride is deposited. Each of these layers can be deposited using one of the conventional CV1) processes well known in the art, with each of the layers having a thickness of between about 1000 A to 3000 A. The total thickness of the layers is preferably about 3000 A, but this may be readily varied to form salicide structures of different thicknesses.
After the layers 42, 44, 46 that will be formed into the polysilicon form have been deposited, photolithography is performed to provide openings through the three layers at the regions where salicide structures are to be formed. This photolithography may use a mask that is -the reverse of the conventional first polysilicon mask pattern so that, after the photoresist is exposed and removed, openings through the photoresist will leave the layer 46 exposed over the 11 regions where the salicide structures are to be formed. Then, the layers 42, 44 and 46 are etched in a substantially anisotropic manner using, for example, plasma etching with SF6 and He for the S'3N, layers 46 and 42 and using CHF3 and 0-, for the SiO, layer 44. A- fier the photoresist is stripped, the device will appear as shown in Fig. 8 with an opening 48 over the illustrated active device region and an opening 50 on top of the field oxide region 12. A lateral etch of the middle
S'02 layer 44 is then performed by dipping the device in a dilute I-IF solution (e.g., ERH20 = 1: 10) for between about two to about seven minutes. This will result in an undercut 52 being formed laterally across layer 44 witWn opening 48 and an undercut 54 being formed across layer 44 within opening 50. The undercut etch will also result in the removal of the pad oxide 40 where it is exposed to the dilute HT solution, as well as a slight undercut beneath layer 42. The extent of the undercut of layer 44 determines how far polysilicon protrusions will overhang the substrate for the shaped polysilicon structure that is to be formed. Accordingly, as will be described in greater detail below, the extent of the undercut will establish the position of the edge of the heavily doped portion of the LEID source/drain regions of the device. Thus, the extent of the undercut may desirably be adjusted in accordance with the particular structure that is desired for the source/drain regions. The presently preferred extent of the undercuts 52, 54 is between about 500 A to about 2000 A.
After the undercut etching has been performed, the substrate 10 will be exposed within the opening 48. A gate oxide layer 56 (Fig. 10) is then thermally grown in the conventional manner to a thickness of between about 30 A to about 300 A. Polysilicon is deposited by CVD to a sufficient depth to extend above the first layer 42 and more preferably to extend above layer 44.
The thickness of the polysilicon layer will typically be about the thickness of the three layers 42, 12 44 and 46. CVD polysilicon will readily deposit within the undercut regions 52, 54 (Fig. 9) to form shaped polysilicon structures 58, 60 as shown in Fig. 10. The polysilicon structures are preferably doped iii.yilii during deposition by the addition of the appropriate dopant gas during the CVD process, or the polysilicon structures may alternately be doped later by ion implantation.
The stack of layers 42, 44, 46 is then removed using conventional etchants, such as hot H3P04 for the S'3N, layer 46 and 42 and a dilute HF (in H20) solution for the S'02 layer 44, to provide the structure shown in Fig. 11.
Next, the anti-punchthrough implantations are formed and the lightly doped portions of the source/drain regions are formed. These implantations are made in a self-aligned manner using the protrusions 62 extending from the polysilicon electrode 58 as a mask during oblique angle ion implantation. The implantation angles are readily determined by the length by which the protrusions 62 extend over the surface of the substrate 10 and the angle necessary for the implantation to have "line of sighf' to the base of the polysilicon electrode 58. Typically, the implantation angle will be between about 15' to about 60'. The anti- punchthrough implantations 64 and lightly doped drain implantations 66 are made in the well known manner using implantations of boron, boron fluoride, arsenic or phosphorus ions to a dose of between about 5 x W' ions/cm'to about 2 x IC ions/cm' at an energy of between about 5 to 80 KeV. The resulting structure is illustrated in Fig. 12.
The heavily doped portions of the source/drain regions are then formed by implantation perpendicular to the surface of the substrate (i.e., no tilt angle), using the protrusions 62 extending from the polysilicon electrode 58 as a mask for the heavy implantation. Because the edge of heavily doped region is determined by where the "shadows" of the protrusions 62 fall on 13 the substrate, the heavily doped regions (68, Fig. 13) are formed selfaligned to the protrusions, Typically, the heavily doped regions are formed by an implantation of boron, boron fluoride, arsenic, antimony or phosphorus ions to a dose of between about 1 x 10,' ionS/CM2 to about 1 x 1016 ion S/CM2 at an energy of between about 5 to 200 KeV. The source/drain regions are then activated by heating the device to a temperature of between about 800T to 1 100T for between seconds (RTA, higher temperature) and 60 minutes (lower temperature).
Next, the silicide portion of the salicide structure is formed. As is known in the art, acceptable silicide layers can be formed using a number of different base metals, including titanium, cobalt, nickel, platinum and palladium. At the present time, titanium silicide is the most widely implemented, but both cobalt and nickel silicides are believed to have desirable characteristics for reduced line width devices. The processing steps characteristic to each of these different silicides are well known and reported in the literature. Accordingly, while the following description is made in terms of titanium silicide, other silicides can also be utilized in this process, as is known in the art.
After thermal activation of the dopants, the device is as illustrated in Fig. 13. The native (thermal) oxide formed in this process is removed using a dilute I-IF solution, and then a thin layer of the metal to be silicided is deposited over the device using physical vapor deposition (e.g., sputtering). In the illustrated embodiment, titanium is deposited to a thickness of between about A to 800 A, producing thin layers 70 over the surface of the device, as shown in Fig. 14. The thickness of metal to be deposited is determined by balancing the need to deposit sufficient titanium to form a uniform layer with sufficient metal to provide a desirably conductive titanium silicide layer against the need to leave sufficient silicon below the silicided structures. Excessive 14 silicon consumption during silicidation can lead to unacceptablejunct ion leakage from the source/drain rep-ions, among other problems. As is illustrated in Fig. 14, there is poor nietal coverage in the region where the substrate is shadowed by the prot sions 62 from the poiys'i 1 ru i icon electrode 58.
The discontinuities in the metal layer 70 adjacent the gate electrode ensure that bridging (such as that illustrated in Fig, 5) should not occur. Thus, it is possible to perform the initial silicidation at a temperature sufficiently high to produce the low resistivity phase of titanium silicide. Accordingly, titanium silicide could be formed by performing a rapid thermal anneal (RTA) of the Fig. 14 device at a temperature of about 75WC for about twenty seconds. A subsequent etch would remove the unreacted titanium. In this process, however, there may be considerable silicon transport along the titanium layer 70, which could result in titaiiium silicide stringers extending over portions of the device in an undesirable fashion. It is therefore still likely preferred that silicidation be per-formed in a two-step process. Regardless, the existence of the discontinuities in.the sputtered titanium layer reduce the criticality of the temperature and other controls for the processing steps in the two-step annealing process. Preferably, the Fig. 14 structure is subjected to a first RTA at a temperature with.in the range of 600-750'C, more preferably of about 700T, for 10 to 12 0 seconds, more preferably 20 to 60 seconds, in a nitrogen ambient. For cobalt silicide, a temperature of about 550-600'C is preferably used for the initial silicidation step. Titanium nitride, titanium-rich titanium silicide, titanium oxide and unreacted titanium are then etched from the surface ofthe device in a solution of N114011, H202 and H20 (for example, at a ratio of 1: L5), leaving titanium silicide layers 72 over the heavily doped portions 68 of the source/drain regions. Titanium silicide regions 74, 76 also remain over the polysillcon portion 58 of the gate electrode and over the polysilicon portion 60 of the wiring line.
The remaining titanturn silicide is then converted to the lower resistivity phase in a RTA at a temperature wIthin a range of about 700'C to 90WC for between about 10 to 60 seconds. Most preferably, the second RTA is performed at a temperature of about 850'C for about 20 seconds.
In this embodiment, the titanium silicide regions 74, 76 are less constrained than in the conventional salicide process. Ideally, the titanium silicide will be essentially unconstrained in the vertical direction, since there are no spacer oxide regions to verlically compress the titanium silicide in the regions where the silicon is consumed. The titanium silicide regions 74, 76 are thus formed with much lower stress levels than occur in the conventional silicidation process (illustrated in Figs. 1-4). There will still be stress introduced into the titanium silicide layer along the horizontal direction due to the mismatch between the titanium silicide and the underlying (unconsumed) silicon, but the structure should nevertheless have a much reduced stress level after the initial silicidation process than in conventional salicide processes. As such, the second RTA has a much improved likelihood of converting the titanium silicide to the preferred low resistivity phase. The titanium silicide structures 74, 76 have approximately the same width (i.e., approximately 500 A to approximately 2000k) as the silicon protrusions 62 that exist prior to the silicidation process.
Subsequent processing proceeds in the conventional manner, with the deposition of a interpolysilicon or pre-metal dielectric layer such as atmospheric pressure CVD S'02 or borophosphosilicate glass (13PSG) over the Fig. 15 structure. Thus, CVD S'02 or BPSG will typically be disposed adjacent the lower sidewalls of the polysilicon electrode 58 (between the protrusions of silicide layer 74 and the substrate 10) and adjacent the lower sidewalls of 16 poiysilicon wiring line 60 (between the protrusions of silicide layer 76 and the field oxide 12). Vias are formed through the CV1) S'02 or BPSG down to the silicide regions as necessary, forming polysilicon or metal contacts and first metal or second polysilicon wiring lines and interconnects. The remaining structures and processes are conventional and so are not described further herein. It should be noted that certain configurations of gate electrodes, wiring lines and silicided regions of the substrates sometimes include additional layers of conductive materials such as refractory metals or nitrides of metals (e.g., titanium nitride) formed on top of the salicide structure.
The present invention has been described in terms of certain preferred embodiments. The invention is not, however, limited to the specific embodiments described, but also includes such modifications and variations as fall within the scope of the following claims.
17

Claims (1)

1. A method of making a semiconductor device, comprising the steps of: 5 providing a semiconductor substrate and providing a layer of insulating material over at least a portion of the semiconductor substrate; forming a shaped polysilicon structure over the layer of insulating material, the shaped polysilicon structure having protrusions extending laterally over a surface of the semiconductor substrate; depositing a metal layer on the shaped polysilicon structure; and annealing the semiconductor device to produce a layer is of metal silicide on the shaped polysilicon structure. 2. The method of claim 1, wherein the metal layer is deposited by physical vapor deposition. 3. The method of claim 1, wherein the metal layer is deposited in such a manner that there is discontinuity in the deposited metal layer at or near the protrusions of the polysilicon structure. 4. The method of claim 1, wherein the step of annealing the semiconductor device consists of a rapid thermal anneal performed at a temperature within the range of 6000C to 7500C. 5. The method of claim 4, wherein the rapid thermal anneal is performed at a temperature of about 700'. 6. The method of claim 4, wherein the rapid thermal anneal continues for a time between 10 to 120 seconds.
7. The method of claim 5, wherein the rapid thermal anneal continues for 20 to 60 seconds. 8. The method of claim 1, further comprising the step of etching the device in a solution of NH40H, H202 and H20 subsequent to the step of annealing the semiconductor device.
18 9. The method of claim 8, further comprising a second step of annealing the semiconductor device at a temperature of about 8500C for about 20 seconds.
10. The method of claim 1, further comprising a second step of annealing the semiconductor device at a temperature of greater than 7000C for about 10 to about 120 seconds.
11. A method of forming a semiconductor device including a MOS transistor, the method of making the MOS transistor comprising the steps of:
forming an insulator on a semiconductor substrate; forming a shaped polysilicon electrode on the insulator, the shaped polysilicon electrode having protrusions extending laterally over the semiconductor substrate; forming by ion implantation LDD source/drain regions within the substrate on either side of the shaped polysilicon electrode using the protrusions of the shaped polysilicon electrode as a mask for the ion implantation to define the LDD source/drain region dopant distribution; and forming a metal silicide layer over the shaped polysilicon electrode. 12. The method of claim 11, wherein the step of forming the shaped polysilicon electrode structure comprises the steps of: depositing a first layer of masking material on the semiconductor device and a second layer of masking material on the first layer of masking material; forming an opening by removing a portion of the first and the second layers of masking material; laterally etching the second layer of masking material so that the opening is wider at the second layer than at the first layer; depositing polysilicon within the opening; and removing the first and second layers of masking 35 material. 13. The method of claim 12, further comprising the step of depositing a third layer of masking material on the second 19 layer of masking material before the step of forming an opening. 14. The method of claim 13, wherein the first and third layers of masking material are formed of the same material. 15. The method of claim 14, wherein the second layer of masking material comprises silicon oxide. 16. The method of claim 13, wherein the polysilicon is deposited by chemical vapor deposition and is doped in situ.
17. The method of claim 11, wherein the step of forming a metal silicide layer comprises the steps of: depositing a layer of metal on the semiconductor device; annealing the semiconductor device to form metal is silicide on the shaped polysilicon electrode; and etching unreacted metal from the semiconductor device.
18. The method of claim 17, wherein the deposited metal is selected from the group consisting of titanium, cobalt, nickel, platinum and palladium.
GB0113671A 1996-12-04 1996-12-04 Method of making semiconductor device with salicide electrode Withdrawn GB2360128A (en)

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JP2009524221A (en) * 2006-01-17 2009-06-25 インターナショナル・ビジネス・マシーンズ・コーポレーション Structure and method for landing pad of MOSFET gate electrode

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WO1993010558A1 (en) * 1991-11-18 1993-05-27 Vlsi Technology, Inc. Extended polysilicon self-aligned gate overlapped lightly doped drain structure for submicron transistor
JPH07183504A (en) * 1993-12-22 1995-07-21 Nec Corp Manufacture of semiconductor device
US5464782A (en) * 1994-07-05 1995-11-07 Industrial Technology Research Institute Method to ensure isolation between source-drain and gate electrode using self aligned silicidation
JPH08264771A (en) * 1995-03-22 1996-10-11 Toshiba Corp Semiconductor device and its manufacture

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Publication number Priority date Publication date Assignee Title
US5144393A (en) * 1989-04-04 1992-09-01 Mitsubishi Denki Kabushiki Kaisha Structure for a PSD type field effect transistor
WO1993010558A1 (en) * 1991-11-18 1993-05-27 Vlsi Technology, Inc. Extended polysilicon self-aligned gate overlapped lightly doped drain structure for submicron transistor
JPH07183504A (en) * 1993-12-22 1995-07-21 Nec Corp Manufacture of semiconductor device
US5464782A (en) * 1994-07-05 1995-11-07 Industrial Technology Research Institute Method to ensure isolation between source-drain and gate electrode using self aligned silicidation
JPH08264771A (en) * 1995-03-22 1996-10-11 Toshiba Corp Semiconductor device and its manufacture

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009524221A (en) * 2006-01-17 2009-06-25 インターナショナル・ビジネス・マシーンズ・コーポレーション Structure and method for landing pad of MOSFET gate electrode

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