JPH023244A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To maintain a gate insulation film in favorable condition by laminating a real electrode and a dummy electrode so as to constitute a gate electrode, and forming a source area and a drain area by a self-alignment method in which those electrodes are used as masks, and then removing the dummy electrode so as to bury high melting point metal in that trace. CONSTITUTION:In the active element formation area on a silicon semiconductor substrate 1 are formed a gate insulation film 6 consisting of SiO2,a gate electrode 7 at the first layer which uses, e.g., polycrystal silicon containing impurity as material, an etching stoppage film 8 consisting of titanium nitride, and a dummy gate electrode 9 Which uses, e.g., polycrystal silicon. After burying the gate electrode 7 at the first layer, the etching stoppage film 8, and the dummy gate electrode 9 using sidewalls 12 R consisting of, e.g., SiO2 and interlayer insulation films 14 consisting of, e.g., SiO2, the dummy electrode 9 is removed. In the trace that the gate electrode 9 is removed, a gate electrode at the second layer consisting of high melting point metal such as tungsten, etc., is formed.

Description

[Detailed Description of the Invention] [Summary] Reduced MIS (metal 1 insulator)
Regarding a method suitable for manufacturing a semiconductor device having a field effect transistor (semiconductor), a so-called dummy gate process is adopted, while a gate insulating film can be maintained in good condition as originally formed. For the purpose of this, a process of forming a gate insulating film, a gate electrode, and a dummy gate electrode on a semiconductor substrate, and then an impurity ion implantation process using a self-alignment method using the gate electrode pattern as a mask. a step of forming a source region and a drain region by performing heat treatment to activate the impurities; then, a step of forming an insulating film to fill the gate electrode patterns and then removing only the dummy gate electrode; Next, the method includes the step of embedding a high melting point metal in the area where the dummy gate electrode has been removed.

[Industrial application field]

The present invention relates to a method suitable for manufacturing a semiconductor device having a reduced MIS field effect transistor.

In order to increase the integration of semiconductor devices, their constituent elements must be reduced in size. For example, in a field effect transistor, it is necessary to reduce the values of (1) the thickness of the gate insulating film, (2) the depth of the source and drain regions, (2) the thickness of the gate electrode, and (2) the channel length.

In the present invention, attention is paid to the depths of the source and drain regions (2) and the thickness of the gate electrode (2).

[Conventional technology]

Conventionally, the so-called ion implantation method, in which impurities are ionized and implanted into a semiconductor substrate, has been used to introduce impurities to form conductive regions such as source and drain regions, from the viewpoint of good controllability and good uniformity. It has been adopted.

In this case, a self-alignment method using the gate electrode as a mask is often adopted. However, when the gate electrode is thin, there is a problem in that ions penetrate through the gate electrode and reach the underlying gate insulating film, deteriorating the withstand voltage.

Another problem with thinning the gate electrode is that the resistance value of the gate electrode/wiring increases. Therefore, even though a thin gate electrode is preferable for higher integration, it is not possible to make the gate electrode thinner arbitrarily. To address this problem, high melting point metals,
For example, this problem can be solved by using titanium (Ti). However, in this case, since a self-alignment method is adopted, it goes without saying that the refractory metal gate electrode is formed before ion implantation into the source and drain regions. When heat treatment is performed to activate the constituent impurities, the high melting point metal gate electrode changes in quality, and in particular, peels off from the gate insulating film.

In order to solve this problem, the present inventors created a dummy
He developed a technique called the gate process.

That is, the gate electrode of the MIS field effect transistor is formed of polycrystalline silicon, which has a high etching selectivity with respect to silicon dioxide (SiOz), and by using this as a mask and performing ion implantation, the source region is formed using a self-alignment method. Then, a drain region is formed, and heat treatment is performed to activate the implanted impurities. Up to this point, there is no difference from the conventional technology, but after this, for example, chemical vapor deposition (chemical vapor deposition)
ion: CVD) method to deposit 5io2, etc., etch and bank it to expose the top surface of the polycrystalline silicon gate electrode, and then apply an appropriate etching method to remove the polycrystalline silicon. The silicon gate electrode is removed and a high-melting point metal is buried in its place to form the gate electrode.

In this way, the high-melting point metal gate electrode is not exposed to high-temperature heat treatment, so there is no possibility that the underlying layer will peel off.

[Problem to be solved by the invention]

According to the above-mentioned improved conventional technology, considerable success has been achieved in terms of suppressing deterioration of the high melting point metal gate electrode.

However, it turns out that there are still problems with that method.

That is, when removing the dummy gate electrode originally created, the gate insulating film is considerably damaged.

The present invention makes it possible to maintain the good condition of the gate insulating film as originally formed, while employing a so-called dummy gate process.

[Means to solve the problem]

1 and 2 are cross-sectional side views of essential parts of a semiconductor device at key points in the process for detailed explanation of the present invention.
This will be explained with reference to these figures.

Refer to FIG. 1 (1) A gate insulating film 6 made of Si02 is formed in the active element formation region on the silicon semiconductor substrate 1, and a first layer gate electrode 7 made of polycrystalline silicon containing impurities, for example.
, an etching stop film 8 made of, for example, titanium nitride (T i N), and a dummy film made of, for example, polycrystalline silicon.
A gate electrode 9 is formed.

(2) Impurity ions are implanted to form the source region 10 and drain region 11, and heat treatment is performed to activate the impurities.

See Figure 2 (3) First layer gate electrode 7, etching stop film 8,
The dummy gate electrode 9 is connected to a side wall 12 made of, for example, 5i02, and a glabella insulating film 1 made of, for example, 5i02.
4, and then remove the dummy gate electrode 9.

(4) A second layer gate electrode 15 made of a high melting point metal such as tungsten (W) is formed in the area where the dummy gate electrode 9 has been removed. Although 13 is a high melting point metal silicide film, this is not essential.

Thereafter, on the second layer gate electrode 15, a gate electrode/wiring made of, for example, aluminum (1M) or the like is formed.

In this way, in the present invention, the first layer gate electrode 7 on the gate insulating film 6 is left as it is formed.
The gate insulating film 6 is not damaged, and
Since the etching when removing the dummy gate electrode 9 is automatically stopped by the etching stop film 8, no control is required.

For this reason, in the method of manufacturing a semiconductor device according to the present invention, a gate insulating film (for example, gate insulating film 6) and a gate electrode (for example, gate electrode 7) forming a dummy gate electrode (for example, dummy gate electrode 9), and then ion implantation of impurities by a self-alignment method using these gate electrode patterns as a mask and activation of the implanted impurities. There is a step of performing heat treatment to form a source region (for example, n-type source region 10) and a drain region (n-type drain region 11), and then forming an insulating film (for example, side wall and 12 and interlayer insulating film 14) and then removing only the dummy gate electrode, and then burying a high melting point metal (for example, W film 15) in the area where the dummy gate electrode was removed. Construct to include.

[Effect]

By adopting the above-mentioned means, the gate insulating film maintains the original state in which the gate electrode film serving as the gate electrode is stacked and is not damaged in any way;
The high melting point metal embedded in the remains of the dummy gate electrode is
It is selectively grown after high-temperature heat treatment to activate impurities in the source and drain regions.
There is no risk of peeling off, and since the high melting point metal is not exposed to high temperatures, there is no risk of the resistance value increasing due to reaction with 5i02 etc. Furthermore, the ions forming the source and drain regions Since a dummy gate electrode is present during implantation, there is no risk of impurity ions penetrating through the gate electrode.

〔Example〕

3 to 12 are cross-sectional side views of essential parts of a semiconductor device at key points in the process for explaining one embodiment of the present invention, and the following description will be made with reference to these figures. Note that the same symbols as those used in FIGS. 1 and 2 indicate the same parts or have the same meanings. In addition, here, salicide (se 1f-aligned 5ilici)
Although the present invention is directed to a Mis field effect semiconductor device having a (de:5ALICIDE) structure, it is not limited thereto.

Refer to FIG. 3. (1) By applying a thermal oxidation method, Si with a thickness of, for example, about 200 [people] is formed on the p-type silicon semiconductor substrate 1.
An OZ film 2 is formed. This 5i02 film 2 is a silicon nitride (Si3N4
) The stress generated between the film and the silicon semiconductor substrate 1 is alleviated.

See Figure 4 (by applying the 21CVD method, the thickness, for example, 15
By forming a Si3N film 3 of about 0.00 (person) and applying ordinary photophosphorography technology, Si
The 3N4 film 3 is patterned to leave only the part covering the active element formation region and remove the rest.

(3) By applying an ion implantation method, for example, boron (B) ions are implanted at a high concentration to form the p++ channel cut 95 region 4.

Refer to FIG. 5. (4) A heat treatment is performed in a wet oxidizing atmosphere to form an inter-element isolation insulating film 5 made of Si02.

(5) The Si3N film 3 used as an oxidation-resistant mask and the SiO2 film 2 used as a buffer film are removed to expose the active element forming region of the silicon semiconductor substrate 1.

By applying the +61CVD method as shown in Fig. 6, the thickness of
By forming a gate electrode film made of polycrystalline silicon containing impurities of about 0 [person], and then applying a sputtering method, a Ti film with a thickness of, for example, about 300 [person] is formed.
An etching stop film 8 made of N is formed, and then C
By applying the VD method, the thickness can be reduced to, for example, 2000 C.
A dummy gate electrode film made of polycrystalline silicon having a thickness of about 100 cm is formed.

(7) By applying ordinary photolithography technology, the gate electrode film, the etching stop film, and the dummy gate electrode film are patterned to form the gate electrode 7,
An etching stop film 8 in the shape of a gate electrode and a dummy gate electrode 9 are formed.

(8) By applying the ion implantation method, R(P) ions are implanted at a dose of, for example, 4 X I Q10 (am-23) and an acceleration energy of, for example, 60 (KeV). A "" type source region 10 and an n-type drain region 11 are formed using a self-alignment method.

See Figure 8 (9) By applying the CVD method, a thickness of, for example, 20
00 (person) SiO2 film is formed, and then reactive ion etching (reactive i) using CF, +H2 as the etching gas.

The side wall 12 is formed by anisotropically etching the Si02 film by applying a method (RIE).

By applying the αφ ion implantation method, arsenic (As) ions are implanted at a dose of, for example, 4×IQ 15 (cm−”) and an acceleration energy of, for example, 70 (KeV) to form the n++ source region 10'. and an n+ type drain region 11'.

αυ RTA (rapid thermal an
By applying the Heal method, steps (8) and 0
Activation of P ions and As ions implanted at the mouth is performed.

As a result, the n- type source region IO, the n++ source region 10', the n- type drain region 11, and the n+ type drain region 11' can actually operate.

(b) By applying a sputtering method, a Ti film with a thickness of, for example, 400 μm is formed, and then RTA
By applying the method, a heat treatment is performed to cause Ti and silicon to react, and a titanium silicide (TiSiz) film 13 is formed.

In this case, since the side wall 12 exists in the '['1Siz film 13, the dummy gate electrode 9,
It is generated only on the source region 10 and drain region 11.

Refer to Fig. 9.031 By applying the CVD method, SiO2II with a thickness of, for example, 4000 (people) can be formed at the lowest possible temperature!
form 14. Incidentally, Si due to such CVD method
Instead of O2 film, spin-on glass
On glass: 5OG) film may also be used.

The 5io2 film 14 and the like formed here need to be formed thick enough to absorb surface irregularities and become flat.

(RIE using 141 etching gas as CF4,000H2)
By applying a method, the 5i02 film 14 is etched and banked to expose the T i S i 2 film 13 covering the surface of the dummy gate electrode 9 .

See Figure 10 α9 For example, by applying a dipping method using hydrofluoric acid diluted to about 1 to 2% as an enchantment,
The TiSi2 film I3 covering the dummy gate electrode 9 is removed, and then the dummy gate electrode 9 is etched and removed by applying a plasma etching method using CF4+02 as an etching gas. Note that this etching automatically stops at the surface of the etching stop film 8 made of TiN.

Oe By applying the RIE method using resist process and etching gas of CF4,000H2 in normal photolithography technology, SiO2PI
A selective etch of J14 is performed to form source and drain electrode contact windows. still,
In this case, etching automatically stops at the TiSi2 film 13.

See Figure 11 07) By removing the photoresist film used as a mask for forming the electrode contact window, for example by immersing it in acetone, and then applying the CVD method.
In each electrode contact window, the thickness is e.g. 500 W.
The film 15 is selectively grown.

Refer to Fig. 12 q81 By applying sputtering method and ordinary photolithography technology, source electrode/wiring 16S, drain electrode/wiring A16D made of AN, for example.
, a gate electrode/wiring 16G is formed.

The gate insulating film 6 in the MIS field effect semiconductor device manufactured as described above maintains the state as it was when the gate electrode film made of impurity-containing polycrystalline silicon, which becomes the gate electrode 7, was formed; It will be understood that the selectively grown W film 15 is not subjected to high temperature heat treatment for activating impurities. The present invention applies not only to MIS field effect semiconductor devices having a salicide structure as seen in the above embodiments, but also to ordinary structure or LDD (lightly doped) semiconductor devices.
Needless to say, it can be implemented in other structures such as a d drain structure. Further, in the above embodiment, the dummy gate electrode 9 made of polycrystalline silicon was used, but this can be replaced with a material having a sufficiently high etching selectivity with respect to the gate electrode 7. Then, the etching stop film 8 becomes unnecessary. Furthermore, the same applies even if the high melting point metal in the above description is a silicide thereof.

〔Effect of the invention〕

In the method for manufacturing a semiconductor device according to the present invention, the gate electrode pattern formed on the gate insulating film is formed by laminating a real electrode and a dummy electrode, and a self-contained electrode pattern is formed by laminating a real electrode and a dummy electrode, and using these electrodes as a mask. A source region and a drain region are formed using an alignment method, and then the dummy electrode is removed and a high-melting point metal is buried in its place.

By adopting the above structure, the gate insulating film maintains the original state in which the gate electrode film serving as the gate electrode is stacked and is not damaged in any way;
The high melting point metal embedded in the remains of the dummy gate electrode is
It is selectively grown after high-temperature heat treatment to activate impurities in the source and drain regions.
There is no risk of peeling, and since the high-melting point metal is not exposed to high temperatures, no deterioration occurs, and even if the gate is made completely thin, its resistance value can be maintained low. Since the dummy gate electrode is present during ion implantation to form the source and drain regions, there is no risk of impurity ions penetrating through the gate electrode.

[Brief explanation of the drawing]

1 and 2 are cross-sectional side views of essential parts of a semiconductor device at key points in the process for explaining the present invention in detail, and FIGS. 3 to 12 are cross-sectional side views for explaining one embodiment of the present invention. 2A and 2B are cross-sectional side views of essential parts of a semiconductor device at important points in the process. In the figure, 1 is a p-type silicon semiconductor substrate, 4 is a p+ type channel cut region, 5 is a field insulating film, 6 is a gate insulating film, 7 is a gate electrode, 8 is an etching stop film,
9 is a dummy gate electrode, 10 is an n-type source region, 1
1 is an n-type drain region, 12 is a side wall, 1
3 is a TiSi2 film, 14 is an interlayer insulating film, 15 is a W film, 1
6S indicates a source electrode/wiring, 16D indicates a drain electrode/wiring, and 16G indicates a gate electrode/wiring. Patent applicant: Fujitsu Ltd. Representative Patent Attorney Shoji Aitani

Claims (1)

[Claims] A step of forming a gate insulating film, a gate electrode, and a dummy gate electrode on a semiconductor substrate, and then ion implantation and implantation of impurities by a self-alignment method using the gate electrode pattern as a mask. a step of forming a source region and a drain region by performing heat treatment to activate the impurities, and a step of forming an insulating film to fill the gate electrode patterns and then removing only the dummy gate electrode. A method for manufacturing a semiconductor device, comprising the steps of: burying a high melting point metal in the area where the dummy gate electrode has been removed.