JPH08306802A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To form a gate electrode of low resistance and a source-drain layer on an NMOS and a PMOS. CONSTITUTION: A polycrystalline silicon film 106, a metal nitride film 201, and a polycrystalline silicon film 109 are deposited on a gate oxide film 105 on a silicon substrate 101 on which a p well 102, an N well 103 and an element isolation region 104 are formed. By anisotropic etching, a gate electrode is formed, and an oxide film spacer 107 is formed on the gate electrode side surface. Only the polycrystalline silicon film 109 is etched. As ions are implanted in a gate electrode 401 and a source-drain region 402 in an NMOS region. BF2 ions are implanted in a gate electrode and a source-drain region 502 of a PMOS region. A metal film 300 is deposited on the substrate, and a metal silicide film 301 is formed on the source-drain region, in a self-alignment manner. The metal silicide film 301 on the source-drain region is made into low resistance. A tungsten film is deposited on a tungsten nitride film of the gate electrode, and a CMOS device structure is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a complementary field effect transistor having a metal film or a metal silicide film on at least a part of a gate electrode and a source region and a drain region. .

[0002]

2. Description of the Related Art MOSFETs (MO
In S field effect transistors), miniaturization of transistors is progressing. In miniaturization of the MOSFET, it is required to shorten the gate length of the gate electrode and to make the junction depth of the diffusion layer in the source and drain regions shallow. These requirements are required. The layer resistance of the drain diffusion layer is increased.

As a result, the parasitic resistance of the gate electrode or the source and drain regions becomes relatively large in proportion to the channel resistance of the device, and the drain current decreases.

In order to prevent deterioration of device characteristics, M.
Sekine et al. (M. Sekine et al., “Self-Aligned T
ungusten Strapped Source / Drain and Gate Technology
Realizing the Lowest Sheet Resistance for Sub-qua
rter Micron CMOS ”, 1994 International Electron Devices Conference (Internationa
Electron Devices Conference), Technical Digest, pages 493-496 (I
EDM94-493-496), 1994), MOSF having a two-layer structure of polycrystalline silicon and a metal film as a gate electrode.
Proposing ET.

In addition, K. Kasai et al. (K. Kasai
Etc., “W / WN _x / Poly-Si Gate Technology for Future Hig
h Speed Deep Submicron CMOS LSIs ", 1994 International Electron Devices Conference, Technical Digest, 49th.
7-500 pages (IEDM94-497-500), 1994),
A MOSFET having a three-layer structure of polycrystalline silicon, a metal nitride film, and a metal film as a gate electrode is proposed.

Referring to FIG. 6, a CMOS (complementary MO type) has a gate electrode having a two-layer structure of polycrystalline silicon and a metal film.
S) A method of manufacturing the device will be described below.

First, a p well 102, an n well 103, and an element isolation region 10 are formed on a silicon semiconductor substrate 101.
4 is formed. Next, a gate oxide film 105 is formed by a thermal oxidation method to form a polycrystalline silicon film 106 to be a gate electrode.
And a CVD oxide film 108 is deposited.

After forming the gate electrode by anisotropic etching, a silicon oxide film is deposited on the substrate by the chemical vapor deposition (CVD) method, and anisotropic etching is further performed to form an oxide film on the side surface of the gate electrode. The spacer 107 is formed (see FIG. 6A).

[0009] Next, to remove only the CVD oxide film 108 by vapor phase etching using hydrogen fluoride gas (vapor HF selective etchi _ng) (see FIG. 6 (B)).

After that, n-type impurities are added to the polycrystalline silicon gate electrode 120 and the source / drain regions 121 in the NMOS region, and the polycrystalline silicon gate electrode 13 in the PMOS region.
0 and p-type impurities are introduced into the source and drain regions 131 by an ion implantation method.

Further, a tungsten film 200 is selectively deposited on the gate electrode and the source / drain regions by the selective CVD method using WF ₆ (see FIG. 6).
(See (C)), the silicide film on the CMOS is completed.

Further, FIGS. 7 and 8 explain a conventional method of manufacturing a CMOS device having a three-layer structure in which a gate electrode has a three-layer structure of polycrystalline silicon (120 or 130), a metal nitride film 201, and a metal film 200 in the order of steps. It is a figure.

First, a p well 102, an n well 103, and an element isolation region 10 are formed on a silicon semiconductor substrate 101.
4 is formed.

Next, a gate oxide film 105 is formed by a thermal oxidation method, and a polycrystalline silicon film (12) which becomes a gate electrode is formed.
0, 130) are deposited (see FIG. 7A).

Further, by the two lithography processes,
N-type impurities are added to the polycrystalline silicon 120 on the NMOS side.
A p-type impurity is introduced into the polycrystalline silicon 130 on the PMOS side by ion implantation, and then a tungsten nitride film 201 and a tungsten film 200 are deposited on the polycrystalline silicon film by a sputtering method to form a gate electrode by anisotropic etching. Form.

After that, a silicon oxide film is deposited on the substrate by chemical vapor deposition (CVD), and anisotropic etching is further performed to form an oxide film spacer 107 on the side surface of the gate electrode.
Are formed (see FIG. 7B).

Next, an n-type impurity is introduced into the source and drain regions of the NMOS region and a p-type impurity is introduced into the source and drain regions of the PMOS region by ion implantation. Further, in order to reduce the resistance of the source / drain regions, a titanium film 300 is deposited on the substrate and then heat-treated to form a metal silicide film 301 on the source / drain regions in a self-aligned manner (FIG. 8C). reference).

The unreacted metal film on the insulating film is selectively removed by wet etching to complete the silicide film on the CMOS (see FIG. 8D).

[0019]

However, in the complementary semiconductor device in which the gate electrode shown in FIG. 6 has a two-layer structure of polycrystalline silicon and a metal film, a metal film is formed by a high temperature process after the formation of the two-layer structure. There is a problem that the silicon film causes a silicidation reaction to destroy the gate insulating film or the junction of the diffusion layers.

Further, in the CMOS type semiconductor device in which the gate electrode shown in FIGS. 7 and 8 has a three-layer structure of polycrystalline silicon, a metal nitride film and a metal film, the silicidation reaction does not occur, but the polycrystalline silicon An additional two lithographic steps are required to introduce impurities into the film, which causes a significant increase in the number of steps, which remains a problem.

Therefore, the present invention solves the above problems,
It is possible to avoid deterioration of device characteristics due to miniaturization (reduction of resistance of gate electrode, improvement of heat resistance, etc.), suppress increase in number of processes, and easily realize complementary field effect (CMOS) transistor structure. It aims at providing a simple manufacturing method.

[0022]

In order to achieve the above object, the present invention provides (a) a field insulating film and a gate insulating film in predetermined regions respectively corresponding to an element isolation region and an element formation region on the surface of a silicon substrate. And forming a gate electrode formed by stacking a first polycrystalline silicon film, a metal nitride film, and a second polycrystalline silicon film in this order on a predetermined region of the gate insulating film. b) An insulating film is formed on the entire surface, and the insulating film is etched back by anisotropic etching until a predetermined region of the surface of the silicon substrate and the upper surface of the gate electrode are exposed. A step of forming a spacer made of an insulating film,
(c) a step of selectively etching only the second polycrystalline silicon of the gate electrode by a vapor phase etching method using chlorine gas; and (d) the first polycrystalline silicon film of the gate electrode. A step of selectively forming impurities of a predetermined conductivity type in the element region on the surface of the silicon substrate,
(e) depositing a metal film and performing heat treatment to form a metal silicide film made of a silicide of the metal film on at least the surface of the diffusion layer formed in the step (d), and (f)
At least selectively etching away the unreacted metal film on the insulating film, leaving the metal silicide film only on the surface of the diffusion layer, and (g) forming a metal film on at least the surface of the gate electrode. And a step of selectively depositing the semiconductor device.

In addition, the present invention, following the step (d),
And before the step (e), ion implantation is performed on the entire surface,
At least the surface of the diffusion layer is made amorphous.

In the present invention, the above-mentioned steps are preferable.
In (c), the silicon substrate is heated to a predetermined temperature to selectively etch only the second polycrystalline silicon.

In the present invention, preferably, the metal silicide film formed on the surface of the diffusion layer is annealed.

In the present invention, the above-mentioned steps are preferable.
In (g), the metal film is selectively formed by a chemical vapor deposition method using a hydrogen reduction reaction.

The present invention also provides (a) NMOS region, PM
A gate electrode is formed by sequentially stacking a first polycrystalline silicon film, a metal nitride film, and a second polycrystalline silicon film on a gate oxide film of a silicon substrate on which an OS region and an element isolation region are formed, (b) A spacer (sidewall) made of an insulating film is formed on the side surface of the gate electrode, and (c) the second polycrystalline silicon film is selectively etched away by heating the substrate to a predetermined temperature, d) First gate electrode in NMOS region
N-type impurities are introduced into the polycrystalline silicon film and the source and drain regions of the above, and p-type impurities are introduced into the first polycrystalline silicon film and the source and drain regions of the gate electrode in the PMOS region, respectively, to cover the substrate (e). As described above, a metal silicide film is formed on the source and drain regions in a self-aligned manner, and then the unreacted metal film is selectively removed.
(f) Annealing the metal silicide film in the source and drain regions, and (g) depositing a metal film on the metal nitride film of the gate electrode by a selective growth method using hydrogen reduction reaction to form a CMOS device structure. Provided is a method for manufacturing a semiconductor device, which is characterized by forming the same.

[0028]

The operation and principle of the present invention will be described below.

The present invention manufactures a semiconductor device having a three-layer structure of a metal nitride film and a metal film on a polycrystalline silicon film as a gate electrode structure in order to reduce the resistance of the gate electrode and maintain heat resistance. It provides a method.

That is, in the manufacturing method of the present invention, as two completely new process techniques, a technique of selectively etching only polycrystalline silicon by a vapor phase etching method using chlorine gas and a metal on the metal nitride film are used. Techniques for selectively depositing films are used.

The selective etching of polycrystalline silicon, which is one of the new techniques, has been completed by the knowledge based on the experimental result of the crystal plane dependence of silicon etching.

In the vacuum chamber, chlorine gas is supplied onto the polycrystalline silicon and single crystal silicon (100) surfaces to etch the silicon. In this case, if the substrate temperature is set to 600 ° C. to 800 ° C., as shown in FIG.
The amount of silicon etching is different between on poly-silicon (poly-Si) and on (100) plane single crystal silicon. In addition,
In FIG. 5, the horizontal axis represents the substrate temperature (° C.) and the vertical axis represents the etching rate (angstrom /).

More specifically, when the substrate temperature is 700 ° C. or lower, single crystal silicon is not etched at all, but etching proceeds on polycrystalline silicon (poly-Si).

Therefore, by using the above etching conditions, only the polycrystalline silicon can be selectively etched.

On the other hand, the selective deposition of a metal film on a metal nitride film, which is another novel technique of the present invention, uses a selective growth reaction using a hydrogen reduction reaction.

By utilizing the hydrogen reduction reaction, selective growth is possible even when the base is not a silicon substrate but a metal nitride film.

By using the above new technique, it is possible to make the gate structure a two-layer structure of a metal nitride film and a polycrystalline silicon film when impurities are introduced into the lower polycrystalline silicon film, and extra lithography is performed. The process can be omitted and can be performed simultaneously with the introduction of impurities into the source and drain regions.

Further, in the present invention, the gate structure is a two-layer structure of a metal nitride film and a polycrystalline silicon film when impurities are introduced into the lower polycrystalline silicon film, and the final gate structure is a metal film and a metal nitride film. In order to obtain a crystalline silicon film,
As the initial gate electrode structure, a three-layer structure of an upper polycrystalline silicon film, a metal nitride film, and a lower multilayer silicon film is used. After forming the initial gate electrode structure and forming the gate side wall, only the upper polycrystalline silicon is selectively etched by a vapor phase etching method using chlorine gas.

By this etching, only the lower polycrystalline silicon film and the metal nitride film remain on the gate electrode. Next, impurities are introduced into the gate electrode and the source and drain regions by ion implantation, and then a metal film is deposited on the metal nitride film by a selective CVD method to form a final gate structure.

[0040]

Embodiments of the present invention will be described below with reference to the drawings.

[0041]

Embodiment 1 FIGS. 1 and 2 are views for explaining a manufacturing method according to a first embodiment of the present invention in the order of steps.

Referring to FIG. 1A, the p well 102,
A gate oxide film 105 is formed on the silicon semiconductor substrate 101 in which the n well 103 and the element isolation region 104 are formed by a thermal oxidation method, a non-doped polycrystalline silicon film (lower polycrystalline silicon film) 106 is 100 nm, and a tungsten nitride film 201 is formed. With a thickness of 20 nm and a non-doped polycrystalline silicon film (upper polycrystalline silicon film) 109 with a thickness of 100 nm,
After forming the gate electrode by anisotropic etching, CV
A silicon oxide film is deposited on the substrate by the D method, and anisotropic etching is further performed to form an oxide film spacer 107 on the side surface of the gate electrode.

Next, the substrate is placed in a vacuum chamber and 1 ×
Evacuate to 10 ^-9 Torr and add chlorine gas to the chamber for 1 sc
Inject under the condition of cm. Further, the substrate is heated to 750 ° C. Then, only the upper polycrystalline silicon film 109 on the surface of the gate electrode is etched (see FIG. 5), and the silicon film is not etched on the substrate silicon (FIG. 1 (B)).
reference).

The etching of the upper polycrystalline silicon film 109 is stopped on the tungsten nitride film 201.

After that, the gate electrode 401 in the NMOS region is formed.
Ion implantation of (arsenic (As)) in the (lower polycrystalline silicon film 106), the source / drain region 402, and boron difluoride (BF ₂ ) in the gate electrode 501 and the source / drain region 502 of the PMOS region. Introduced in. This state is shown in FIG.

Further, as shown in FIG. 1C, a titanium film 300 having a thickness of 35 nm is deposited on the substrate by a sputtering method, and then a lamp annealing method is performed at about 650 ° C. for 10 seconds to form a source / drain region on the source / drain region. The titanium silicide film 301 is formed in a self-aligned manner.

The unreacted metal film on the insulating film is selectively removed by hydrogen peroxide aqueous wet etching.

After that, the resistance of the titanium silicide film 301 in the source / drain regions is reduced by a lamp annealing method at 850 ° C. for 10 seconds.

Further, as shown in FIG. 2D, a tungsten film 200 having a thickness of 80 nm is formed only on the tungsten nitride film of the gate electrode by a chemical vapor deposition method (CVD) using a WF ₆ gas in a hydrogen reduction mode. Deposited and CMO
Form an S-device structure.

In this embodiment, when impurities are introduced into the lower polycrystal silicon film of the gate electrode, the gate structure is a two-layer structure of a metal nitride film and a polycrystal silicon film, and no extra lithography is required. In addition, since it is possible to introduce impurities into the polycrystalline silicon film at the same time as introducing impurities into the source and drain regions, it is possible to avoid an increase in the number of manufacturing steps and to realize a deep sub-micron CMO which has been miniaturized.
It is preferably applied to the production of S devices.

[0051]

[Embodiment 2] FIGS. 3 and 4 are views showing a manufacturing method according to a second embodiment of the present invention in the order of steps.

Referring to FIG. 3A, the p well 102,
A gate oxide film 105 is formed by a thermal oxidation method on a silicon semiconductor substrate 101 having an n well 103 and an element isolation region 104 formed therein, a non-doped polycrystalline silicon film (lower polycrystalline silicon film) 106 having a thickness of 80 nm, and a tungsten nitride film 201. Of 15 nm and a non-doped polycrystalline silicon film (upper polycrystalline silicon film) 109 of 100 nm are deposited, and a gate electrode is formed by anisotropic etching.

After that, a silicon oxide film is deposited on the substrate by the CVD method, and anisotropic etching is further performed to form an oxide film spacer 107 on the side surface of the gate electrode.

Next, the substrate is placed in a vacuum chamber and 1 ×
The gas is evacuated to 10 ^-9 Torr, and then chlorine gas is injected into the chamber under the condition of 1 sccm. Further, the substrate is heated to 750 ° C. Then, only the upper polycrystalline silicon film 109 on the surface of the gate electrode is etched, and the silicon film is not etched on the substrate silicon (see FIG. 3B).

The etching of the upper polycrystalline silicon film 109 is stopped on the tungsten nitride film 201.

After that, the gate electrode 401 in the NMOS region
And arsenic in the source / drain region 402 and the PMOS
Region gate electrode 501 and source / drain region 502
Boron difluoride is introduced by an ion implantation method. This state is shown in FIG.

Next, the acceleration voltage is 30 keV and the dose is 3
The surface of the source / drain regions 402 and 502 is made amorphous by an ion implantation method using arsenic under the condition of × 10 ¹⁴ cm ^-2 (see FIG. 3C).

Further, as shown in FIG. 4D, after a titanium film 300 is deposited to a thickness of 25 nm on the substrate by a sputtering method, a self-implantation method is performed on the source / drain regions by a lamp annealing method at 690 ° C. for 10 seconds. The titanium silicide film 301 is formed in a conformal manner. By forming the surfaces of the source / drain regions 402 and 502 to be amorphous, the formation of the metal titanium silicide film 301 is facilitated.

The unreacted metal film on the insulating film is selectively removed by wet etching using a hydrogen peroxide solution.

After that, the resistance of the titanium silicide film 301 in the source / drain regions is further reduced by a lamp annealing method at 890 ° C. for 10 seconds.

Further, as shown in FIG. 4E, a 60 nm thick tungsten film 200 is deposited only on the tungsten nitride film 201 of the gate electrode by the chemical vapor deposition method using WF ₆ gas in the hydrogen reduction mode. , Forming a CMOS device structure.

Although the present invention has been described above with reference to the above embodiments, the present invention is not limited to the above embodiments, and it is needless to say that various embodiments according to the principle of the present invention are included. In particular, the parameters such as the film thickness illustrated in the above embodiments do not limit the present invention. Further, in the present invention, the metal silicide film formed on the source / drain diffusion layers is not limited to the titanium silicide film, and silicide of other refractory metal such as W can be applied.

[0063]

As described above, according to the present invention,
When a two-layer structure of a metal film and a polycrystalline silicon film is used as a gate electrode, the gate structure is a metal nitride film and a polycrystalline silicon film when impurities are introduced into the lower polycrystalline silicon film.
The present invention avoids an increase in the number of manufacturing steps because it can be formed into a layered structure, unnecessary lithography is unnecessary, and it can be performed at the same time when impurities are introduced into the source and drain regions.

Further, according to the present invention, a metal film, a metal nitride film, and a polycrystalline silicon film are formed from the top as a final gate structure, and a metal silicide film is formed in the source / drain regions, so that heat resistance is significantly increased. Can be improved.

[Brief description of drawings]

FIG. 1 is a diagram for explaining a first embodiment of the present invention in process order.

FIG. 2 is a diagram for explaining a first embodiment of the present invention in process order.

FIG. 3 is a diagram for explaining a second embodiment of the present invention in process order.

FIG. 4 is a diagram for explaining a second embodiment of the present invention in process order.

FIG. 5 is a schematic cross-sectional view of a MOSFET in which a metal film is simultaneously formed on a gate electrode and a diffusion layer in source / drain regions.

FIG. 6 is a diagram illustrating a method of manufacturing a MOSFET in which a gate electrode is formed of a metal film, a metal nitride film, and a polycrystalline silicon film in the order of steps.

FIG. 7 is a diagram illustrating a method of manufacturing a MOSFET in which a gate electrode is formed of a metal film, a metal nitride film, and a polycrystalline silicon film in the order of steps.

FIG. 8 is a diagram showing the substrate temperature dependence of silicon etching on a polysilicon film and on a (100) single crystal silicon substrate.

[Explanation of symbols]

 Reference Signs List 101 silicon semiconductor substrate 102 p well 103 n well 104 element isolation region 105 gate oxide film 106 non-doped polysilicon film 107 oxide film spacer 108 CVD oxide film 109 upper non-doped polysilicon film 200 metal film for gate electrode 201 metal nitride film 300 diffusion layer Metal for metal 301 Metal silicide film 401 NMOS gate electrode 402 NMOS source / drain region 501 PMOS gate electrode 502 PMOS source / drain region

Claims (6)

[Claims] 1. A field insulating film and a gate insulating film are respectively formed in predetermined regions corresponding to an element isolation region and an element formation region on a surface of a silicon substrate, and the field insulating film and the gate insulating film are formed on the predetermined region of the gate insulating film. A step of forming a gate electrode formed by stacking a first polycrystalline silicon film, a metal nitride film, and a second polycrystalline silicon film in this order on the substrate, (b) forming an insulating film on the entire surface, and performing anisotropic etching. By etching back the insulating film until a predetermined region of the surface of the silicon substrate and the upper surface of the gate electrode are exposed, and forming a spacer made of the insulating film on the side surface of the gate electrode, (c) Selectively etching only the second polycrystalline silicon of the gate electrode by a vapor phase etching method using chlorine gas; and (d) the first polycrystalline silicon film of the gate electrode and the A step of selectively forming impurities of a predetermined conductivity type in the element region on the surface of the recon substrate, and (e) a diffusion layer formed in at least the step (d) by performing a heat treatment by depositing a metal film. A step of forming a metal silicide film made of a silicide of the metal film on the surface of, and (f) at least selectively etching away the unreacted metal film on the insulating film so that only the surface of the diffusion layer is formed. A method of manufacturing a semiconductor device, comprising: a step of leaving the metal silicide film left; and (g) a step of selectively depositing a metal film on the surface of the gate electrode. 2. The method, further to the step (d) and before the step (e), further comprising a step of performing ion implantation on the entire surface to amorphize at least the surface of the diffusion layer. 1. The method for manufacturing a semiconductor device according to 1. 3. The method according to claim 1, wherein in the step (c), the silicon substrate is heated to a predetermined temperature to selectively etch only the second polycrystalline silicon.
The manufacturing method of the semiconductor device described in the above. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the metal silicide film formed on the surface of the diffusion layer is annealed. 5. The method of manufacturing a semiconductor device according to claim 1, wherein in the step (g), the metal film is selectively formed by a chemical vapor deposition method using a hydrogen reduction reaction. 6. (a) A first polycrystalline silicon film, a metal nitride film and a second polycrystalline silicon film are formed on a gate oxide film of a silicon substrate on which an NMOS region, a PMOS region and an element isolation region are formed. A gate electrode formed by sequentially laminating is formed, (b) a spacer (side wall portion) made of an insulating film is formed on a side surface of the gate electrode, and (c) the second polycrystalline silicon film is placed on the substrate at a predetermined temperature. Then, the first polycrystalline silicon film of the gate electrode in the NMOS region and the n-type impurities in the source and drain regions are selectively removed by etching.
P-type impurities are respectively introduced into the first polycrystalline silicon film of the gate electrode and the source and drain regions in the region, and (e) a metal film is deposited so as to cover the substrate, and self-aligned on the source and drain regions. After forming a metal silicide film on, the unreacted metal film is selectively removed, (f) the metal silicide film in the source and drain regions is annealed, (g) on the metal nitride film of the gate electrode A method of manufacturing a semiconductor device, comprising depositing a metal film by a selective growth method using hydrogen reduction reaction to form a CMOS device structure.