JP2827962B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a complementary field effect transistor having a metal film or a metal silicide film at least on a gate electrode and at least on a source region and a drain region. .

[0002]

2. Description of the Related Art MOSFETs (MOs) constituting integrated circuits
(S field-effect transistor), the transistor is being miniaturized. In miniaturization of MOSFETs, it is required to shorten the gate length of the gate electrode and to reduce the depth of the junction between the diffusion layers of the source and drain regions. The layer resistance of the drain diffusion layer is increased.

As a result, there is a problem that the parasitic resistance of the gate electrode or the source and drain regions becomes relatively large in proportion to the channel resistance of the device, and the drain current decreases.

In order to prevent device characteristic deterioration, M.P.
Sekine et al. (M. Sekine et al., “Self-Aligned T
ungusten Strapped Source / Drain and Gate Technology
Realizing the Lowest Sheet Resistance for Sub-qua
rter Micron CMOS ”, 1994 International Electron Devices Conference (Internationa
l Electron Devices Conference), Technical Digest, pp. 493-496 (I
EDM94-493 to 496), 1994), a MOSF having a two-layer structure of polycrystalline silicon and a metal film as a gate electrode.
Propose ET.

Further, K. Kasai et al. (K. Kasai)
Etc., “W / WN _x / Poly-Si Gate Technology for Future Hig
h Speed Deep Submicron CMOS LSIs ”, 1994 International Electron Devices Conference, Technical Digest, No. 49
7-500 (IEDM94-497-500), 1994)
A MOSFET having a three-layer structure of polycrystalline silicon, a metal nitride film, and a metal film has been proposed as a gate electrode.

Referring to FIG. 6, a CMOS (complementary MO) having a gate electrode having a two-layer structure of polycrystalline silicon and a metal film is provided.
S) A method for manufacturing a device will be described below.

First, on a silicon semiconductor substrate 101, a p-well 102 and an n-well 103, and furthermore, an element isolation region 10
4 is formed. Next, a gate oxide film 105 is formed by a thermal oxidation method, and a polycrystalline silicon film 106 serving as a gate electrode is formed.
And a CVD oxide film 108 is deposited.

After forming a gate electrode by anisotropic etching, a silicon oxide film is deposited on the substrate by a chemical vapor deposition (CVD) method, and further anisotropically etched to form an oxide film on the side surface of the gate electrode. The spacer 107 is formed (see FIG. 6A).

[0009] Next, to remove only the CVD oxide film 108 by vapor phase etching using hydrogen fluoride gas (vapor HF selective etchi _ng) (see FIG. 6 (B)).

Thereafter, an n-type impurity is added to the polysilicon gate electrode 120 and the source / drain region 121 in the NMOS region, and the polysilicon gate electrode 13 in the PMOS region is
0 and p-type impurities are introduced into the source and drain regions 131 by ion implantation.

Further, a tungsten film 200 is selectively deposited on the gate electrode and the source / drain regions by a selective CVD method using WF ₆ (FIG. 6).
(See (C)), a silicide film on the CMOS is completed.

FIGS. 7 and 8 illustrate a conventional method of manufacturing a CMOS device in which a gate electrode has a three-layer structure of polycrystalline silicon (120 or 130), a metal nitride film 201, and a metal film 200 in the order of steps. FIG.

First, a p-well 102 and an n-well 103 are formed on a silicon semiconductor substrate 101, and an element isolation region 10 is formed.
4 is formed.

Next, a gate oxide film 105 is formed by a thermal oxidation method, and a polycrystalline silicon film (12
0, 130) (see FIG. 7A).

Further, by two lithography steps,
An n-type impurity is added to the polysilicon 120 on the NMOS side.
A p-type impurity is introduced into the polysilicon 130 on the PMOS side by ion implantation. Thereafter, a tungsten nitride film 201 and a tungsten film 200 are deposited on the polysilicon film by sputtering, and a gate electrode is formed by anisotropic etching. Form.

Thereafter, a silicon oxide film is deposited on the substrate by chemical vapor deposition (CVD), and further anisotropically etched to form an oxide film spacer 107 on the side surface of the gate electrode.
Is formed (see FIG. 7B).

Next, an n-type impurity is introduced into the source and drain regions of the NMOS region and a p-type impurity is introduced into the source and drain regions of the PMOS region by ion implantation. Further, in order to reduce the resistance of the source / drain regions, a titanium silicide film 300 is deposited on the substrate and then heat-treated to form a metal silicide film 301 on the source / drain regions in a self-aligned manner (FIG. 8C). reference).

The silicide film on the CMOS is completed by selectively removing the unreacted metal film on the insulating film by wet etching (see FIG. 8D).

[0019]

However, in the complementary semiconductor device shown in FIG. 6 in which the gate electrode has a two-layer structure of polycrystalline silicon and a metal film, the metal film and the metal film are formed by a high-temperature process after the formation of the two-layer structure. There is a problem in that the silicon film undergoes a silicidation reaction and the gate insulating film is destroyed, or the junction of the diffusion layer is destroyed.

In the CMOS type semiconductor device shown in FIGS. 7 and 8 in which the gate electrode has a three-layer structure of polysilicon, a metal nitride film, and a metal film, a silicidation reaction does not occur. Two extra lithography steps are required to introduce impurities into the film, and the problem that the number of steps is greatly increased still remains.

Therefore, the present invention solves the above problems,
A new device that can avoid deterioration of device characteristics due to miniaturization (lower resistance of gate electrode, improved heat resistance, etc.), suppress increase in the number of steps, and easily realize a complementary field effect (CMOS) transistor structure It is intended to provide a simple manufacturing method.

[0022]

In order to achieve the above object, the present invention provides (a) a method of forming a field insulating film and a gate insulating film in predetermined regions respectively corresponding to an element isolation region and an element formation region on a surface of a silicon substrate. Forming a gate electrode formed by laminating a first polycrystalline silicon film, a metal nitride film, and a second polycrystalline silicon film in this order on a predetermined region of the gate insulating film; b) forming an insulating film on the entire surface, performing an etch-back of the insulating film until a predetermined region on the surface of the silicon substrate and the upper surface of the gate electrode are exposed by anisotropic etching, and Forming a spacer made of an insulating film;
(c) selectively etching only the second polycrystalline silicon of the gate electrode by a vapor phase etching method using chlorine gas, and (d) forming the first polycrystalline silicon film of the gate electrode. Selectively forming a predetermined conductivity type impurity in the element region on the surface of the silicon substrate;
(e) depositing a metal film and performing a heat treatment, at least forming a metal silicide film made of silicide of the metal film on the surface of the diffusion layer formed in the step (d); (f)
A step of at least selectively removing the unreacted metal film on the insulating film by etching, and leaving the metal silicide film only on the surface of the diffusion layer; and (g) forming a metal film on at least the surface of the gate electrode. Selectively depositing a semiconductor device.

[0023] Further, the present invention provides a method comprising:
And before the step (e), ion implantation is performed on the entire surface,
At least a step of amorphizing a surface of the diffusion layer is provided.

In the present invention, preferably, the step
In (c), the silicon substrate is heated to a predetermined temperature to selectively etch only the second polycrystalline silicon.

In the present invention, preferably, the metal silicide film formed on the surface of the diffusion layer is annealed.

In the present invention, preferably,
In (g), the metal film is selectively formed by a chemical vapor deposition method using a hydrogen reduction reaction.

Also. The present invention relates to (a) NMOS region, PM
Forming a gate electrode formed by sequentially stacking a first polycrystalline silicon film, a metal nitride film, and a second polycrystalline silicon film on a gate oxide film of a silicon substrate on which an OS region and an element isolation region are formed; (b) forming a spacer (side wall portion) made of the side surface insulating film of the gate electrode, (c) the substrate chlorine
Is heated to a predetermined temperature in a gas atmosphere selectively removed by etching said second polycrystalline silicon film, (d) a first polycrystalline silicon film and the n-type source and drain regions of the gate electrode in the NMOS region Impurities are introduced into the first polycrystalline silicon film of the gate electrode in the PMOS region and the p-type impurities into the source and drain regions, respectively, and (e) a metal film is deposited so as to cover the substrate. After the metal silicide film is formed in a self-aligned manner, the unreacted metal film is selectively removed, (f) annealing the metal silicide film in the source and drain regions, and (g) forming the gate electrode. Provided is a method for manufacturing a semiconductor device, comprising forming a CMOS device structure by depositing a metal film on a metal nitride film by a selective growth method using a hydrogen reduction reaction.

[0028]

The operation and principle of the present invention will be described below.

According to the present invention, there is provided a method of manufacturing a semiconductor device having a three-layer structure composed of a metal nitride film and a metal film on a polycrystalline silicon film as a gate electrode structure in order to reduce the resistance of the gate electrode and maintain heat resistance. It provides a method.

That is, in the manufacturing method of the present invention, two completely new process techniques are a technique of selectively etching only polycrystalline silicon by a vapor phase etching method using chlorine gas and a technique of selectively etching metal on a metal nitride film. And a technique for selectively depositing a film.

The selective etching of polycrystalline silicon, which is one of the new techniques, has been completed based on the knowledge based on the experimental results of the crystal plane dependence of silicon etching.

In a vacuum chamber, chlorine gas is supplied onto polycrystalline silicon and single crystal silicon (100) planes to etch silicon. In this case, when the substrate temperature is set at 600 ° C. to 800 ° C., as shown in FIG.
The amount of silicon etching is different between polycrystalline silicon (poly-Si) and (100) plane single crystal silicon. In addition,
The horizontal axis in FIG. 5 indicates the substrate temperature (° C.), and the vertical axis indicates the etching rate (angstrom /).

More specifically, at a substrate temperature of 700 ° C. or lower, single-crystal silicon is not etched at all, but etching proceeds on polycrystalline silicon (poly-Si).

Therefore, by using the above-mentioned etching conditions, only the polycrystalline silicon can be selectively etched.

On the other hand, the selective deposition of a metal film on a metal nitride film, which is another novel technique of the present invention, uses a selective growth reaction using a hydrogen reduction reaction.

By utilizing the hydrogen reduction reaction, selective growth becomes possible even when the underlying layer is not a silicon substrate but a metal nitride film.

By using the above-described novel technique, when introducing impurities into the underlying polycrystalline silicon film, the gate structure can be made to have a two-layered structure of a metal nitride film and a polycrystalline silicon film. This eliminates the need for a step and can be performed simultaneously with the introduction of impurities into the source and drain regions.

Further, according to the present invention, when introducing impurities into the lower polycrystalline silicon film, the gate structure is a two-layer structure of a metal nitride film and a polycrystalline silicon film, and the final gate structure is formed of a metal film, a metal nitride film and a polycrystalline silicon film. In order to make a crystalline silicon film,
As an initial gate electrode structure, a three-layer structure of an upper polycrystalline silicon film, a metal nitride film, and a lower multilayer silicon film is used. After forming the initial gate electrode structure, after forming the gate side wall, only the upper polycrystalline silicon is selectively etched by a vapor phase etching method using chlorine gas.

As a result of this etching, only the lower polycrystalline silicon film and the metal nitride film remain on the gate electrode. Next, after impurities are introduced into the gate electrode and the source and drain regions by ion implantation, a metal film is deposited on the metal nitride film by a selective CVD method, whereby a final gate structure can be formed.

[0040]

Embodiments of the present invention will be described below with reference to the drawings.

[0041]

[Embodiment 1] FIGS. 1 and 2 are views for explaining a manufacturing method according to a first embodiment of the present invention in the order of steps.

Referring to FIG. 1A, a p-well 102,
A gate oxide film 105 is formed by thermal oxidation on a silicon semiconductor substrate 101 on which an n-well 103 and an element isolation region 104 have been formed, a non-doped polycrystalline silicon film (lower polycrystalline silicon film) 106 has a thickness of 100 nm, and a tungsten nitride film 201 has been formed. Is deposited to a thickness of 20 nm and a non-doped polycrystalline silicon film (upper polycrystalline silicon film) 109 is deposited to a thickness of 100 nm.
After forming a gate electrode by anisotropic etching, CV
A silicon oxide film is deposited on the substrate by the method D, and anisotropic etching is further performed to form an oxide film spacer 107 on the side surface of the gate electrode.

Next, the substrate is placed in a vacuum chamber and 1 ×
Exhaust to 10 ^-9 Torr and place chlorine gas in the chamber for 1 sc
Inject under cm conditions. Further, the substrate is heated to 750 ° C. Then, only the upper polycrystalline silicon film 109 on the gate electrode surface is etched (see FIG. 5), and the silicon film is not etched on the substrate silicon (FIG. 1B).
reference).

The etching of upper polycrystalline silicon film 109 is stopped on tungsten nitride film 201.

Thereafter, the gate electrode 401 in the NMOS region
(The lower polycrystalline silicon film 106) and arsenic (As) in the source / drain region 402, and boron difluoride (BF ₂ ) in the gate electrode 501 and the source / drain region 502 in the PMOS region. Will be introduced at FIG. 1B shows this state.

Further, as shown in FIG. 1C, after a titanium film 300 is deposited on the substrate by sputtering at a thickness of 35 nm by a sputtering method, the lamp is annealed at approximately 650 ° C. for 10 seconds to form a titanium film 300 on the source / drain region. A titanium silicide film 301 is formed in a self-aligned manner.

The unreacted metal film on the insulating film is selectively removed by aqueous hydrogen peroxide based wet etching.

Thereafter, the resistance of the titanium silicide film 301 in the source / drain region is reduced by a lamp annealing method at 850 ° C. for 10 seconds.

Further, as shown in FIG. 2D, a tungsten film 200 is formed to a thickness of 80 nm only on the tungsten nitride film of the gate electrode by chemical vapor deposition (CVD) using WF ₆ gas in a hydrogen reduction mode. Deposit and CMO
Form an S device structure.

In this embodiment, when impurities are introduced into the lower polycrystalline silicon film of the gate electrode, the gate structure has a two-layer structure of a metal nitride film and a polycrystalline silicon film, so that extra lithography is unnecessary. The impurity can be introduced into the polycrystalline silicon film at the same time as the impurity is introduced into the source and drain regions.
It is suitably applied to the manufacture of S devices.

[0051]

[Embodiment 2] FIGS. 3 and 4 are views showing a manufacturing method according to a second embodiment of the present invention in the order of steps.

Referring to FIG. 3A, p-well 102,
A gate oxide film 105 is formed by thermal oxidation on a silicon semiconductor substrate 101 on which an n-well 103 and an element isolation region 104 have been formed, a non-doped polycrystalline silicon film (lower polycrystalline silicon film) 106 has a thickness of 80 nm, and a tungsten nitride film 201 has been formed. Is deposited to a thickness of 15 nm and a non-doped polycrystalline silicon film (upper polycrystalline silicon film) 109 is deposited to a thickness of 100 nm, and a gate electrode is formed by anisotropic etching.

Thereafter, a silicon oxide film is deposited on the substrate by the CVD method, and anisotropic etching is further performed to form an oxide film spacer 107 on the side surface of the gate electrode.

Next, the substrate is placed in a vacuum chamber and 1 ×
The chamber is evacuated to 10 ^-9 Torr, and then chlorine gas is injected into the chamber at 1 sccm. Further, the substrate is heated to 750 ° C. Then, only the upper polycrystalline silicon film 109 on the gate electrode surface is etched, and the silicon film is not etched on the substrate silicon (see FIG. 3B).

The etching of upper polycrystalline silicon film 109 is stopped on tungsten nitride film 201.

Thereafter, the gate electrode 401 in the NMOS region
And arsenic in the source / drain region 402 and PMOS
Region gate electrode 501 and source / drain region 502
, Boron difluoride is introduced by an ion implantation method. FIG. 3B shows this state.

Next, the accelerating voltage is 30 keV and the dose is 3
The surfaces of the source / drain regions 402 and 502 are made amorphous by an ion implantation method using arsenic under the condition of × 10 ¹⁴ cm ⁻² (see FIG. 3C).

Further, as shown in FIG. 4D, after a titanium film 300 is deposited on the substrate by a sputtering method to a thickness of 25 nm, a self annealing is performed on the source / drain region by a lamp annealing method at 690 ° C. for 10 seconds. A titanium silicide film 301 is formed in conformity. The formation of the metal titanium silicide film 301 is facilitated by making the surfaces of the source / drain regions 402 and 502 amorphous.

The unreacted metal film on the insulating film is selectively removed by an aqueous solution of hydrogen peroxide.

Thereafter, the resistance of the titanium silicide film 301 in the source / drain region is further reduced by a lamp annealing method at 890 ° C. for 10 seconds.

Further, as shown in FIG. 4E, a 60 nm thick tungsten film 200 is deposited only on the tungsten nitride film 201 of the gate electrode by a chemical vapor deposition method using WF ₆ gas in a hydrogen reduction mode. Then, a CMOS device structure is formed.

Although the present invention has been described with reference to the above embodiment, the present invention is not limited to the above embodiment, but includes various embodiments according to the principle of the present invention. In particular, the parameters such as the film thickness exemplified in the above embodiment do not limit the present invention. Further, in the present invention, the metal silicide film formed on the source / drain diffusion layers is not limited to the titanium silicide film, and silicide of another refractory metal such as W can be applied.

[0063]

As described above, according to the present invention,
When a two-layer structure of a metal film and a polycrystalline silicon film is used as the gate electrode, when introducing impurities into the lower polycrystalline silicon film, the gate structure is formed of a metal nitride film and a polycrystalline silicon film.
The present invention avoids an increase in the number of manufacturing steps because a layer structure can be used, unnecessary lithography is not required, and the step can be performed simultaneously with the introduction of impurities into the source and drain regions.

Further, according to the present invention, a metal film, a metal nitride film, and a polycrystalline silicon film are formed from the top as a final gate structure, and a metal silicide film is formed in the source / drain regions, thereby greatly improving heat resistance. Can be improved.

[Brief description of the drawings]

FIG. 1 is a view for explaining a first embodiment of the present invention in the order of steps.

FIG. 2 is a view for explaining a first embodiment of the present invention in the order of steps.

FIG. 3 is a view for explaining a second embodiment of the present invention in the order of steps.

FIG. 4 is a view for explaining a second embodiment of the present invention in the order of steps.

FIG. 5 is a schematic cross-sectional view of a MOSFET in which a metal film is simultaneously formed on a gate electrode and on a diffusion layer of a source / drain region.

FIG. 6 is a diagram illustrating a method of manufacturing a MOSFET in which a gate electrode is formed by a metal film, a metal nitride film, and a polycrystalline silicon film in the order of steps.

FIG. 7 is a diagram illustrating a method of manufacturing a MOSFET in which a gate electrode is formed of a metal film, a metal nitride film, and a polycrystalline silicon film in the order of steps.

FIG. 8 is a diagram showing the substrate temperature dependence of silicon etching on a polysilicon film and on a (100) single crystal silicon substrate.

[Explanation of symbols]

 Reference Signs List 101 silicon semiconductor substrate 102 p well 103 n well 104 element isolation region 105 gate oxide film 106 non-doped polysilicon film 107 oxide film spacer 108 CVD oxide film 109 upper non-doped polysilicon film 200 metal film for gate electrode 201 metal nitride film 300 diffusion layer Metal for metal 301 Metal silicide film 401 Gate electrode of NMOS 402 Source / drain region of NMOS 501 Gate electrode of PMOS 502 Source / drain region of PMOS

Claims (6)

(57) [Claims] (A) forming a field insulating film and a gate insulating film in predetermined regions respectively corresponding to an element isolation region and an element forming region on a surface of a silicon substrate; Forming a gate electrode formed by laminating a first polycrystalline silicon film, a metal nitride film, and a second polycrystalline silicon film in this order; and (b) forming an insulating film on the entire surface and performing anisotropic etching. Etching back the insulating film until a predetermined region of the surface of the silicon substrate and the upper surface of the gate electrode are exposed, thereby forming a spacer made of the insulating film on a side surface of the gate electrode; Selectively etching only the second polycrystalline silicon of the gate electrode by a vapor phase etching method using chlorine gas; and (d) forming the first polycrystalline silicon film of the gate electrode and Selectively forming impurities of a predetermined conductivity type in the element region on the surface of the recon substrate; and (e) depositing a metal film and performing heat treatment, and at least the diffusion layer formed in the step (d). Forming a metal silicide film made of silicide of the metal film on the surface of (a), (f) at least selectively etching away the unreacted metal film on the insulating film, only on the surface of the diffusion layer A method of manufacturing a semiconductor device, comprising: a step of leaving the metal silicide film; and (g) a step of selectively depositing a metal film on at least a surface of the gate electrode. 2. The method according to claim 1, further comprising a step of performing ion implantation over the entire surface and amorphizing at least the surface of the diffusion layer, following the step (d) and before the step (e). 2. The method for manufacturing a semiconductor device according to claim 1. 3. The method according to claim 1, wherein in said step (c), said silicon substrate is heated to a predetermined temperature to selectively etch only said second polycrystalline silicon.
The manufacturing method of the semiconductor device described in the above. 4. The method according to claim 1, wherein the metal silicide film formed on the surface of the diffusion layer is annealed. 5. The method according to claim 1, wherein in the step (g), the metal film is selectively formed by a chemical vapor deposition method using a hydrogen reduction reaction. 6. A first polycrystalline silicon film, a metal nitride film, and a second polycrystalline silicon film are formed on a gate oxide film of a silicon substrate on which an NMOS region, a PMOS region, and an element isolation region are formed. to form a sequentially stacked gate electrode comprising, by heating in (b) above on the side surfaces of the gate electrode to form a spacer made of an insulating film (side wall portion), a predetermined temperature in a chlorine gas atmosphere (c) the substrate <br/> selectively removed by etching the second polycrystalline silicon film, an n-type impurity into the first polycrystalline silicon film and the source and drain regions of the gate electrode of (d) NMOS region, PMOS
P-type impurities are respectively introduced into the first polycrystalline silicon film and the source and drain regions of the gate electrode in the region, (e) a metal film is deposited so as to cover the substrate, and a self-aligned After the formation of a metal silicide film, the unreacted metal film is selectively removed, (f) annealing the metal silicide film in the source and drain regions, (g) on the metal nitride film of the gate electrode A method of forming a CMOS device structure by depositing a metal film by selective growth using a hydrogen reduction reaction.