JPH08241984A - Fabrication of semiconductor device - Google Patents

Abstract

PURPOSE: To sufficiently recover the crystallinity of a deeply diffused layer by previously forming a deeply diffused layer using a side wall spacer made of a polycrystal line silicon to control impurity diffusion of a shallow diffused layer while controlling a junction leak current. CONSTITUTION: After formation of P-type well 11, N-type well 12, oxide film 13 for element isolation and gate oxide film 14 on an Si substrate 10, a gate electrode 15 made of polycrystal line Si is formed. After the formation of the gate, a CVD SiO2 film 120 is deposited, a polycrystal line Si film 16 is then deposited, and it is processed into a polycrystal line Si side wall spacer 17 by the anisotropic etching process. Next, the As ions 19 are implanted into the N-MOS FET forming region using the photoresist 18 as a mask and BF3 ions 111 are implanted into the P-MOS FET forming region. After the etching and heat treatment, a deep N-type diffused layer 110 and a deep P-type diffused layer 112 are formed. Moreover, with further processing, a titanium silicide layer is finally formed at the upper part of the deeply diffused layer and gate electrode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a complementary type suitable for miniaturization.
The present invention relates to a method of manufacturing a MOSFET.

[0002]

2. Description of the Related Art Si integrated circuits have realized high integration and high speed by miniaturization of processing dimensions. MOSFET (Metal-Oxid
According to the proportional reduction rule of e-Semiconductor Field Effect Transistor), it is necessary to reduce the gate oxide film thickness and the source / drain junction depth in the depth direction in addition to the miniaturization in the plane direction. Conventionally, an ion implantation method has been used for forming a source / drain pn junction.

3 and 4 show the process flow of the conventional method. After the p well 11, the n well 12, the element isolation oxide film 13, and the gate oxide film 14 are formed on the Si substrate 10, the gate electrode 15 is formed. The SiO ₂ film 101 is provided for gate processing. After the gate processing, a CVDSiO ₂ film 120 is deposited (FIG. 3A). Then, using the photoresist film 18 as a mask, the n-MOSFET
As (arsenic) (or P (phosphorus)) is added to the formation region by p-MO.
B (boron, boron) is ion-implanted into the SFET formation region at a low energy of 20 KeV or less to form a shallow n-type diffusion layer 11
3, shallow p-type diffusion layer 114 is formed (b, c).

Next, a Si oxide film 121 is deposited (d),
The sidewall spacers 122 are formed by processing by anisotropic etching (FIG. 4A). Again, As ions and B ions are ion-implanted with higher energy and higher concentration than before, to form the deep n-type diffusion layer 110 and the deep p-type diffusion layer 112 (b) and (e). Finally, T on the whole surface
i is deposited, and a titanium silicide layer 123 is formed on the deep diffusion layer and the gate electrode (d).

In this conventional method, the high temperature heat treatment for recovering the crystal defects in the ion-implanted layer and activating the impurities is often performed last. As a result, the deep diffusion layer having many defects can be sufficiently activated. However, the high temperature heat treatment for this purpose has a problem that the impurities in the shallow diffusion layer are thermally diffused and the junction is deepened.

Further, in order to completely suppress the short channel effect of a device having a gate length of 0.15 μm or less, a shallower junction is required, and an oxide film doped with boron and phosphorus (boron glass, phosphorus glass) is required. The solid-phase diffusion method from has been reviewed. For example, n with a gate length of 0.04 μm
An example of trial manufacture of a channel MOSFET is the 1993 International Electron Devices Meeting, Tech.
nical Digest, p. 119), and a junction depth of 10n that cannot be achieved by the ion implantation method.
m has been achieved. In this method, the sidewall spacer is formed of phosphor glass (or boron glass). Simultaneously with the activation heat treatment of the deep diffusion layer, impurities are diffused from the sidewall spacers to form a shallow diffusion layer. However, since the crystal defects in the deep diffusion layer are present at a high density in a deep position, the heat treatment for forming the shallow diffusion layer does not sufficiently recover and causes a junction leak current.

[0007]

SUMMARY OF THE INVENTION An object of the present invention is to provide a diffusion layer forming technique capable of sufficiently recovering the crystallinity of a deep diffusion layer and suppressing a junction leak current while suppressing the impurity diffusion of a shallow diffusion layer. To provide.

[0008]

[Means for Solving the Problems] The above-mentioned problems are caused by polycrystalline S
This can be solved by first forming a deep diffusion layer using a sidewall spacer made of i (or amorphous Si). If the sidewall spacers are made of Si, the underlying oxide film can be selectively removed by etching after the deep diffusion layer is formed. After that, a shallow diffusion layer may be formed.

[0009]

In the present invention, the shallow diffusion layer is not formed when the deep diffusion layer is formed, and sufficient heat treatment for recovering the crystallinity is possible. After that, the formation of the shallow diffusion layer can be optimized by using necessary and sufficient heat treatment conditions. As described above, it becomes possible to form a good source / drain pn junction having a very small leak current and an extremely shallow portion, and it becomes possible to operate the ultrafine MOSFET.

[0010]

【Example】

(Embodiment 1) First, an example in which low energy ion implantation is used to form a shallow junction will be described with reference to FIGS.

First, on the Si substrate 10, 2 × 10 ¹⁷ / cm ³
3μm deep p-well 11 containing boron of about 2 ×
After forming an n-well 12 having a depth of 3 μm, a device isolation oxide film 13 having a thickness of 300 nm, and a gate oxide film 14 having a thickness of 3.5 to 5 nm, containing phosphorus of about 10 ¹⁷ / cm ³ and a thickness of 20.
A gate electrode 15 made of 0 nm polycrystalline Si was formed. The polycrystalline Si on the p-well contains 10 ²⁰ / cm 2 phosphorus.
³ or more, polycrystalline Si on the n-well has a boron content of 10 ²⁰ / cm
Contains ³ or more. The SiO ₂ film 101 is provided for gate processing. After gate processing, CVDSiO
_{The 2} film 120 is deposited to a thickness of 5 nm (FIG. 1A). continue,
A polycrystalline Si film 16 is deposited to a thickness of 200 nm (b), and the polycrystalline Si sidewall spacer 1 is formed by anisotropic etching.
Process to 7 (c).

Next, using the photoresist 18 as a mask, 30 As (arsenic) ions 19 are added to the n-MOSFET forming region.
2 × 10 ¹⁵ / cm ² at ˜40 KeV, and 2 × 10 ¹⁵ BF ₂ ions 111 at 20 to 30 KeV in the p-MOSFET formation region.
/ Cm ² ion implantation (d, e). Next, polycrystalline S
After removing the i-side wall spacers 17 by etching, heat treatment is performed at 1000 ° C. for 10 seconds to form a deep n-type diffusion layer 110 and a deep p-type shallow junction 112.
(A).

Next, using the photoresist 18 as a mask again, As (arsenic) ions 19 are formed in the n-MOSFET formation region.
5 × 10 ¹⁴ to 1 × 10 ¹⁵ / cm ² , and 5 × 10 ¹⁴ to 1 × 10 ¹⁵ / c of BF ₂ ions 111 in the p-MOSFET formation region.
Ion implantation with low energy of m ² , 5 KeV or less
(b), (c), heat treatment at 900 ° C. for 10 seconds was performed to form the shallow n-type diffusion layer 113 and the shallow p-type diffusion layer 114.
Subsequently, a Si oxide film 121 is deposited to a thickness of 200 nm (d),
The oxide film sidewall spacer 122 was formed by processing by anisotropic etching. Finally, Ti is applied to the entire surface with 30
Then, a titanium silicide layer 123 was formed on the deep diffusion layer and the gate electrode (e).

Since the shallow diffusion layers 113 and 114 have undergone only the necessary minimum heat treatment, a junction depth of 30 nm can be realized, and high-speed operation of a CMOS with a gate length of 0.15 μm has been demonstrated. Further, the crystal defects of the deep diffusion layers 110 and 112 disappeared by sufficient heat treatment, and the leak current level of the junction could be suppressed to a sufficiently low level.

Further, in the MOSFET of the present invention, the position of the deep diffusion layer (distance from the gate electrode) is determined by the width of the polycrystalline Si sidewall spacer 17, and the position of the silicide layer is determined by the oxide film sidewall spacer 122. Since it is determined by the width, it has the advantage that it can be set independently. For example, if the silicide layer is in direct contact with a shallow junction, the total resistance is determined by the contact resistance between the two, resulting in extremely high resistance. However, the width of the oxide film side wall spacer 122 is set to the polycrystalline Si side wall spacer. By making it wider than the width of 17, it is possible to form them so as to be apart from each other to some extent, and to realize low resistance. On the contrary, source of tungsten (W) /
When selectively grown on the drain and used in place of the silicide layer, the Si film thickness consumed by the reaction is small, so that the structure in which W covers almost the entire surface of the deep diffusion layer is advantageous for lowering the resistance. Therefore, the oxide film side wall spacer 1
It is effective to make the width of 22 smaller than the width of the polycrystalline Si sidewall spacer 17.

(Embodiment 2) Next, an example using As ion implantation and diffusion from a boron glass film will be described with reference to FIG.

First, similarly to the first embodiment, a deep n-type diffusion layer 111 and a deep p-type diffusion layer 112 are formed, and CVDS is performed.
After removing the iO ₂ film 120, the surface was re-oxidized to form a thin Si oxide film 30 of 5 nm (FIG. 5A). Then S
An i ₃ N ₄ film was deposited to a thickness of 8 nm and anisotropic etching was performed to obtain S.
An i ₃ N ₄ sidewall spacer 31 was formed (b). For the sake of simplicity, the description of the thin Si oxide film 30 existing between the gate electrode 15 and the Si ₃ N ₄ sidewall spacer 31 is omitted in the figures and the following figures. Next, after removing the oxide film on the source / drain formation region with an aqueous solution of hydrofluoric acid, the film was introduced into a CVD apparatus and a boron glass film 32 having a thickness of 20 nm was deposited on the entire surface (c). Next, the resist mask 18 is formed only in the p-MOSFET formation region by using ordinary photolithography, and then the As ions 19 are 5 × 1 at 10 KeV or less.
0 ¹⁴ to 1 × 10 ¹⁵ / cm ² ions were implanted to form a shallow n-type diffusion layer 113 (d). Then, the boron glass film on the n-MOSFET region was removed by dry etching using the same resist mask. Next, after removing the resist,
A heat treatment was performed at 900 ° C. for 10 seconds to activate As, and B was diffused from the boron glass film to form a shallow p-type diffusion layer 114. Finally, in the same manner as in Example 1, an oxide film sidewall spacer 122 and a titanium silicide layer 123 were formed (f).

From the above, it was confirmed that a shallow junction having a junction depth of 30 nm can be formed and that a CMOS having a gate length of 0.15 μm operates at high speed without causing a short channel effect. In this method, the selective doping for forming the n-type and p-type shallow diffusion layers is performed in a single photoresist process in a self-aligned manner, which is simpler than the conventional ion implantation method of two times. As a whole, the p-type diffusion layer could be made shallow without any complication of the process.

(Embodiment 3) Next, FIG. 6 shows an example using a method of selectively adsorbing boron using an oxide film selectively grown on an n-type diffusion layer formed by ion implantation as a mask. It demonstrates using.

First, in the same manner as in Example 6, a deep n-type diffusion layer 111 and a deep p-type diffusion layer 112 were formed (FIG. 6).
(A)). Next, the p-MOSFET region is masked with the photoresist 18 by an ordinary photoresist process, and the n-MO
As ions 19 were implanted only in the SFET region at 10 KeV or less to form a shallow n-type diffusion layer 113 (b). After removing the photoresist, the Si ₃ N ₄ sidewall spacer 31 was formed in the same manner as in Example 2. Next, the surface was washed with an aqueous solution of hydrofluoric acid to remove the oxide film on the source / drain regions. In the process of washing with water and drying, a natural oxide film 41 having a thickness of about 1 nm was formed only on the surface of the n-type diffusion layer. This sample was introduced into an ultra-high vacuum system and the substrate temperature was 700 ° C.
_{When 2} H ₆ 42 was adsorbed, Si on the p-MOS region
Adsorption of boron was observed only on the surface (c). Next, 9
A heat treatment is performed at 00 ° C. for 10 seconds to activate As and at the same time B is diffused into Si to form a shallow p-type diffusion layer 114.
Was formed (d). Finally, similarly to Example 1, the oxide film sidewall spacers 122 and the titanium silicide layers 123 were formed (e).

As described above, a shallow junction having a junction depth of 30 nm and a sheet resistance of 2 kΩ / □ can be formed, and the gate length is 0.15 μm.
It was confirmed that the m 2 CMOS operates at high speed without causing the short channel effect. In this method, the selective adsorption phenomenon of B ₂ H ₆ was utilized, and the process was further simplified as compared with Example 2 and the conventional method. HBO ₂ and B ₂ O ₃ may be used as the B source. Further, after adsorbing B, when a Si cap layer having a thickness of 2 to 5 nm is epitaxially grown, B exceeds the solid solubility limit and is incorporated into the Si crystal lattice. After that, by performing heat treatment at 900 ° C. for 10 seconds and then removing the Si layer, it is possible to significantly reduce the resistance of the shallow p-type diffusion layer portion. Further, instead of the natural oxide film, an oxide film of several nm is formed on the n-type diffusion layer by a thermal oxidation method in water vapor, and the thin oxide film grown on other portions is removed by etching with a hydrofluoric acid aqueous solution. A method may be used.

(Embodiment 4) Next, an example using a phosphorus glass film and a boron glass film will be described with reference to FIG.

First, in the same manner as in Example 2, a deep n-type diffusion layer 111, a deep p-type diffusion layer 112, and a Si ₃ N ₄ sidewall spacer 31 were formed (FIG. 7A). next,
The oxide film on the source / drain regions is removed with a hydrofluoric acid solution, introduced into a CVD apparatus, a boron glass film 32 having a thickness of 50 nm is deposited, and this is removed only on the n-MOSFET region by ordinary photolithography and dry etching. It was removed by leaving (b). Next, a phosphorous glass film 33 having a thickness of 20 nm is deposited on the entire surface, and heat treatment is performed at 900 ° C. for 10 seconds to diffuse P and B to form a shallow n-type diffusion layer 113 and a shallow p-type diffusion layer 114. (C). Finally, after selectively etching the boron glass and phosphorus glass films with hydrofluoric acid vapor, the oxide film sidewall spacers 122 are formed in the same manner as in the first embodiment.
And a titanium silicide layer 123 was formed (d).

As described above, a shallow junction having a junction depth of 20 nm and a sheet resistance of 2 kΩ / □ can be formed, and the gate length is 0.1 μm.
It was confirmed that the CMOS of 1) operates at high speed without causing the short channel effect. In this method, of course, the deposition order of phosphorus glass and boron glass may be reversed.

Example 5 Next, a phosphorus glass film and B ₂ H _{6 were used.}
An example using selective adsorption of gas will be described with reference to FIG.

First, in the same manner as in Example 2, a deep n-type diffusion layer 111, a deep p-type diffusion layer 112, and a Si ₃ N ₄ sidewall spacer 31 were formed (FIG. 8A). next,
The oxide film on the source / drain regions is removed with a hydrofluoric acid solution, introduced into a CVD apparatus, a phosphorous glass film 33 having a thickness of 20 nm is deposited, and this is removed only on the n-MOS region by ordinary photolithography and dry etching. It was removed by leaving (b). Next, this sample was introduced into an ultra-high vacuum apparatus, HBO ₂ 51 was vapor-deposited at a substrate temperature of 700 ° C., and boron was adsorbed only on the Si surface on the p-MOSFET region (c). next,
A heat treatment was performed at 900 ° C. for 10 seconds to diffuse P and B to form a shallow n-type diffusion layer 113 and a shallow p-type diffusion layer 114 (d). Finally, in the same manner as in Example 1, the oxide film sidewall spacer 122 and the titanium silicide layer 1
23 was formed (e).

As described above, a shallow junction having a junction depth of 10 nm and a sheet resistance of 2 kΩ / □ can be formed, and the gate length is 0.1 μm.
It was confirmed that the CMOS of 1) operates at high speed without causing the short channel effect. The same process can be performed by combining adsorption of a boron glass film and PH ₃ gas (or P, Sb of solid source). Further, if the phosphorus glass film 33 is thickened to 20 nm or more, the HBO ₂ adsorption does not have to be selective. That is, a method of depositing B on the entire surface, for example, a plasma CVD method can also be used.

Example 6 Next, in Example 5, B
An example in which the resistance of the shallow p-type diffusion layer is reduced by growing Si after selective adsorption of is described with reference to FIG.

First, in the same manner as in Example 2, the deep n-type diffusion layer 111, the deep p-type diffusion layer 112, and the Si ₃ N ₄ sidewall spacer 31 were formed (FIG. 9A). next,
The oxide film on the source / drain regions is removed with an aqueous solution of hydrofluoric acid, introduced into a CVD apparatus, and a phosphorous glass film 33 having a thickness of 20 nm is deposited. Remove it by leaving
Heat treatment was performed at 900 ° C. for 10 seconds to diffuse P and form a shallow n-type diffusion layer 113 (b).

Next, this sample was introduced into an ultrahigh vacuum apparatus,
B ₂ H ₆ 42 was introduced at a substrate temperature of 700 ° C. to adsorb boron only on the Si surface on the p-MOS region (c). Next, the Si film 71 was selectively epitaxially grown to a thickness of 5 nm by the UHV-CVD method and used as a substitute for the shallow p-type diffusion layer (d). This is the method known as delta doping. Finally, after removing the phosphorus glass film 33 by etching, the oxide film side wall spacers 12 are formed in the same manner as in the first embodiment.
2 and a titanium silicide layer 123 were formed (e).

As described above, a shallow junction having a junction depth of 10 nm and a sheet resistance of 1 kΩ / □ can be formed, and the gate length is 0.05 μm.
It was confirmed that the m 2 CMOS operates at high speed without causing the short channel effect. Further, δ-doping of Sb may be used to form the shallow n-type diffusion layer. In this case, first, a δ-doped layer of Sb is formed, and boron doping may be performed using a natural oxide film that selectively grows on the n-type diffusion layer as in the third embodiment.

A method of removing the Si film 71 after the impurity diffusion heat treatment is also effective. In this case, Si
Growth need not be selective. In particular, S as an impurity
When b is used, it is desirable to deposit amorphous Si at a low temperature of 200 ° C. or lower in order to suppress the surface segregation phenomenon in which Sb atoms crawl on the surface during Si growth. It is effective to use the vapor deposition method or the Si sputtering method. As a method of removing the Si film, in addition to the Si etching method, when the Si film is further thinned to a thickness of about 1 nm and grown, a cleaning treatment for oxidizing the Si surface and an oxide film etching with an aqueous solution of hydrofluoric acid may be combined.

(Embodiment 7) Finally, an example in which the Si ₃ N ₄ sidewall spacer forming step in Embodiments 2 to 6 is simplified will be described.

First, gate processing was performed in the same manner as in Example 1 (FIG. 10A). After this, CVD SiO ₂
The film 120, the CVDSi ₃ N ₄ film 82, and the polycrystalline Si film 16 were successively deposited (b). For this, continuous film formation was performed using a single-wafer processing type cluster CVD apparatus. Next, the polycrystalline Si film 16 and the CVD Si ₃ N ₄ film 82 are continuously anisotropically dry-etched by using a single-wafer processing type cluster etching apparatus, and the sidewall spacers (17) are formed.
And 83) (c). Next, As and B are ion-implanted in the same manner as in Example 1, and the deep n-type diffusion layer 11
0, a deep p-type diffusion layer 112 was formed (d), (e). Then, using a single wafer processing type cluster etching device,
The removal of the polycrystalline Si 17, the anisotropic dry etching of the CVD Si ₃ N ₄ film 83, and the removal of the CVD SiO ₂ film 120 are performed.
FIG. 11 (a) performed continuously. Then, in the same manner as in Example 5, the shallow n-type diffusion layer 113 and the shallow p-type diffusion layer 114 were formed, and the SiO ₂ sidewall spacer 122 and the titanium silicide layer 123 were formed (a).

In this embodiment, the number of steps is almost the same as that of the fifth embodiment, but since the continuous film formation and etching are performed by the cluster apparatus, the cycle time for completing the steps can be shortened. did it.

[0036]

According to the present invention, extremely shallow (<30 nm) source / drain junctions having low leakage current can be formed,
High-speed operation of complementary MOSFETs with a gate length of 0.15 μm or less becomes possible.

[Brief description of drawings]

FIG. 1 is a sectional view showing a CMOS forming process according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a CMOS forming process of one embodiment of the present invention.

FIG. 3 is a sectional view showing a conventional CMOS forming process.

FIG. 4 is a cross-sectional view showing a conventional CMOS forming process.

FIG. 5 is a cross-sectional view showing the CMOS formation process of the second embodiment of the present invention.

FIG. 6 is a sectional view showing a CMOS forming process according to a third embodiment of the present invention.

FIG. 7 is a cross-sectional view showing the CMOS formation process of the fourth embodiment of the present invention.

FIG. 8 is a sectional view showing a CMOS forming process according to the fifth embodiment of the present invention.

FIG. 9 is a sectional view showing a CMOS forming process according to a sixth embodiment of the present invention.

FIG. 10 is a sectional view showing the CMOS formation process of the seventh embodiment of the present invention.

FIG. 11 is a sectional view showing the CMOS formation process of the seventh embodiment of the present invention.

[Explanation of symbols]

10 ... Si substrate, 11 ... p well, 12 ... n well, 1
3 ... Element isolation oxide film, 14 ... Gate oxide film, 15 ... Gate electrode, 16 ... Polycrystalline Si film, 17 ... Polycrystalline Si sidewall spacer, 18 ... Photoresist, 19 ... As
Ions, 110 ... Deep n-type diffusion layer, 111 ... BF ₂ ions, 112 ... Deep p-type diffusion layer, 113 ... Shallow n-type diffusion layer, 114 ... Shallow p-type diffusion layer, 120 ... CVDSiO ₂
Film, 121 ... Si oxide film, 122 ... Oxide film sidewall spacer, 123 ... Silicide layer.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shinichiro Kimura 1-280 Higashi Koikekubo, Kokubunji, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.

Claims (7)

[Claims] 1. In a method of forming a source / drain pn junction by implanting accelerated impurity ions into a substrate semiconductor by using a gate electrode as a mask in manufacturing a MOSFET, a film serving as a spacer on a side wall of the gate electrode. Forming a diffusion layer portion adjacent to the spacer by implanting impurity ions and thermally activating the impurities by heat treatment, then removing the spacer film, implanting the impurity ions again, and performing heat treatment. A method of manufacturing a semiconductor device, comprising forming a diffusion layer portion adjacent to the gate electrode. 2. In a method of forming a source / drain pn junction by implanting accelerated impurity ions into a substrate semiconductor by using a gate electrode as a mask in manufacturing a MOSFET, a film serving as a spacer on a side wall of the gate electrode. Are formed, impurity ions are implanted, and the impurities are electrically activated by heat treatment to form a diffusion layer portion adjacent to the spacer, then the spacer film is removed, and then the impurity atoms, molecules, or the like are removed. Depositing a thin film containing,
A method for manufacturing a semiconductor device, characterized by performing heat treatment to diffuse impurities into a substrate semiconductor to form a diffusion layer portion adjacent to the gate electrode. 3. In a method of forming a source / drain pn junction by implanting accelerated impurity ions into a substrate semiconductor by using a gate electrode as a mask in manufacturing a MOSFET, a film serving as a spacer on a side wall of the gate electrode. Is formed, the impurity ions are implanted, and the impurities are electrically activated by heat treatment to form a diffusion layer portion adjacent to the spacer, and then the spacer film is removed.
A method of manufacturing a semiconductor device, comprising: forming a diffusion layer portion adjacent to the gate electrode by adsorbing impurity atoms and molecules and further depositing a substrate semiconductor. 4. In a method of forming a source / drain pn junction by implanting accelerated impurity ions into a substrate semiconductor by using a gate electrode as a mask in manufacturing a MOSFET, a film serving as a spacer on a side wall of the gate electrode. Is formed, the impurity ions are implanted, and the impurities are electrically activated by heat treatment to form a diffusion layer portion adjacent to the spacer, and then the spacer film is removed.
After adsorbing impurity atoms and molecules and further depositing a substrate semiconductor, heat treatment is performed to diffuse the impurities into the substrate semiconductor to form a diffusion layer portion adjacent to the gate electrode,
Finally, a method of manufacturing a semiconductor device, characterized in that the substrate semiconductor film is removed. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the sidewall spacer of the gate electrode is made of polycrystalline Si or amorphous Si. 6. The sidewall spacer of the gate electrode for forming a diffusion layer adjacent to the spacer according to claim 2, 3 or 4, wherein polycrystalline Si or amorphous Si is used.
And a side wall of the gate electrode is covered with a Si nitride film when the diffusion layer adjacent to the gate electrode is formed. 7. The multilayer film of Si nitride film and Si film is processed by anisotropic etching to form a sidewall spacer of the gate electrode for forming a diffusion layer adjacent to the spacer. A method for manufacturing a semiconductor device, wherein after removing the Si film, the Si nitride film is processed again by anisotropic etching to form a sidewall spacer for forming a diffusion layer adjacent to the gate electrode.