JP4048159B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a field effect transistor in which a gate electrode and a well region are electrically connected and a manufacturing method thereof.

  In order to reduce the power consumption of a semiconductor integrated circuit using a field effect transistor (FET), it is effective to lower the operating voltage of the FET. A dynamic threshold voltage-metal oxide semiconductor (DT-MOS) field effect transistor in which a gate electrode and a well region are electrically connected has been proposed as a technique for greatly reducing power consumption by lowering an operating voltage. (Hereinafter referred to as DT-MOS transistor).

  As a conventional first semiconductor device, there is a DT-MOS transistor in which a contact plug is used at a connection portion between a gate electrode and a well region in order to electrically connect the gate electrode and the well region (for example, Japanese Patent No. 2990392). No. Publication (Patent Document 1)). Further, as a conventional second semiconductor device, there is a DT-MOS transistor using a silicide film at a connection portion between a gate electrode and a well region (see, for example, International Publication No. 00/01015 (Patent Document 2)). .

  Since the gate electrode and the well region are electrically connected, when the semiconductor circuit is configured using the DT-MOS transistor, the well region of each DT-MOS transistor is configured to avoid the influence of other transistors. It must be isolated from the well regions of other transistors. Therefore, when forming a DT-MOS transistor, an SOI (Silicon On Insulator) substrate having a structure in which an insulator layer is sandwiched between semiconductor layers is used, or if a bulk substrate is used, a well is formed. The region is constituted by a shallow well region and a deep well region having different polarities, and the shallow well region is electrically isolated by the element isolation region.

  Hereinafter, the operating principle of the DT-MOS transistor will be described. When the potential of the gate electrode is at a low level (when the transistor is off), the potential of the well region is also at a low level, the threshold voltage is the same as that of a normal MOS transistor, and the off current is about the same as that of a normal MOS transistor. It is suppressed. On the other hand, when the potential of the gate electrode is high (when the transistor is on), the potential of the well region also becomes high, the threshold voltage is lowered due to the substrate bias effect, and the driving current is larger than that of a normal MOS transistor. Is obtained. Therefore, a large driving current can be obtained with a low power supply voltage without increasing the leakage current when the transistor is off.

The conventional first and second semiconductor devices will be described with reference to FIGS. FIGS. 10 and 11 are cross-sectional views of the field effect transistor cut in the longitudinal direction of the gate electrode, and explain the method of connecting the gate electrode and the well region in an easy-to-understand manner. In FIG. 10, 101 is a base wafer, 102 is a silicon oxide film, 103 is a p-type silicon layer, 104 is an element isolation oxide film, 105 is a gate oxide film, 106 is a gate electrode, 108 is an interlayer insulating film, 109 is p ⁺ A mold diffusion layer 110 is a contact plug and an Al wiring. In FIG. 11, 201 is a semiconductor substrate, 202 is an element isolation region, 203 is a deep well region, 204 is a shallow well region, 205 is a gate oxide film, 206 is a gate electrode, 207 is a gate electrode sidewall insulating film, and 208 is A high-concentration diffusion layer contact region 209 is a refractory metal silicide film.

  In the DT-MOS transistor described in Japanese Patent No. 2990392 shown in FIG. 10, the electrical connection between the gate electrode 106 and the well region (109) is embedded in a contact hole formed in the interlayer insulating film layer 108. The contact plug 110 is a conductive film. However, depending on the circuit configuration, the contact plug is not always connected to the wiring of the wiring layer. If it is not necessary to connect, the wiring must be arranged so as to bypass the contact plug, so that the area of the wiring layer is increased, which hinders high integration of the semiconductor integrated circuit device.

  In the DT-MOS transistor described in the pamphlet of International Publication No. 00/01015 shown in FIG. 11, the electrical connection between the gate electrode 206 and the well region 203 is made between the side wall of the gate electrode 206 and the surface of the well region 203. This is performed by the formed silicide film 209. For this reason, wiring can be freely arranged also on the upper part of the portion where the gate electrode and the well region are electrically connected. However, when a DT-MOS transistor in which a gate electrode and a well region are electrically connected by a silicide film is produced, it is difficult to obtain a good yield at the electrical connection portion between the gate electrode and the well region. .

The following causes can be considered as the cause of the poor yield of connection between the gate electrode and the well region due to such silicide. A refractory metal such as Co is deposited by sputtering, but the refractory metal cannot be sufficiently deposited on the side wall of the gate electrode close to the vertical, and the gate electrode side wall is not sufficiently silicided. For this reason, the silicide film on the side wall of the gate electrode cannot reliably come into contact with the silicide film on the well region, and the yield of electrical connection between the gate electrode and the well region is deteriorated.
Japanese Patent No. 2903892 (page 4, FIG. 1 (b)) International Publication No. 00/01015 Pamphlet (Page 70, Figure 22)

  The present invention has been made to solve the above problems, and in a transistor in which a gate electrode and a well region are electrically connected, the gate electrode and the well region can be used without using a contact plug that restricts the arrangement of wirings. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same that can reliably perform electrical connection, and can achieve high integration and yield improvement.

  In the semiconductor device of the present invention, a well region and an element isolation region formed on a semiconductor substrate, a gate insulating film formed on the well region, a gate electrode formed on the gate insulating film, and the gate An insulating side wall spacer formed so as to surround the gate electrode except for a part of the outer edge of the electrode and in contact with the side wall of the gate electrode, and the gate electrode in which the side wall spacer is not formed And a semiconductor connection portion for electrically connecting the gate electrode and the well region.

  According to the semiconductor device having the above configuration, since the electrical connection between the gate electrode and the well region is not performed by the contact plug reaching the upper wiring layer, the wiring arrangement is not affected. High integration of a semiconductor integrated circuit device having transistors to which are electrically connected can be achieved. In addition, since the semiconductor connection portion can be formed thicker on the side wall of the gate electrode than the silicide film, electrical connection between the gate electrode and the well region can be ensured. Thus, the yield of a semiconductor integrated circuit device having transistors that are electrically connected to each other can be improved.

  In one embodiment, the semiconductor connection portion is formed so as to gradually increase in thickness from the element isolation region side toward the side wall side of the gate electrode.

  In the semiconductor device of the above embodiment, the vertical step due to the gate electrode is relaxed by forming the semiconductor connection portion so that the thickness gradually increases from the element isolation region side toward the side wall side of the gate electrode. The productivity of the process can be increased. For example, there are effects such as easy planarization of the interlayer insulating film layer and an increase in the margin of etching conditions when the contact hole is formed by etching.

  In one embodiment, a contact region having a higher impurity concentration than the region under the gate electrode is provided on the surface side of the well region electrically connected to the semiconductor connection portion. Yes.

  In the semiconductor device of the above embodiment, a contact region having a higher impurity concentration than the region under the gate electrode is provided on the surface side of the well region that is electrically connected to the gate electrode through the semiconductor connection portion. The semiconductor connection portion and the well region can be reliably connected with low resistance.

  In one embodiment, the semiconductor connection portion has the same conductivity type as the well region, the gate electrode is made of a semiconductor, and at least a part of the semiconductor connection portion in contact with the sidewall is the semiconductor connection. It has the same conductivity type as the part.

  In the semiconductor device of the above embodiment, by making the semiconductor connection portion, the well region, and the gate electrode the same conductivity type, the gate electrode and the semiconductor connection portion can be directly connected with low resistance, and the well region, the semiconductor connection portion, Can be directly connected with low resistance, and the manufacturing process can be simplified. The gate electrode is formed of a semiconductor such as polysilicon, so that the semiconductor connection portion can be selectively deposited on the exposed side wall of the gate electrode.

  The method for manufacturing a semiconductor device of the present invention includes a step of forming a well region and an element isolation region on a semiconductor substrate, a step of forming a gate insulating film on the well region, and a gate electrode on the gate insulating film. Forming a sidewall spacer having insulating properties so as to surround the gate electrode and in contact with the sidewall of the gate electrode, and a part of the sidewall of the gate electrode is the sidewall spacer. A step of removing a part of the side wall spacer so as not to be surrounded by a part of the gate electrode, and a part of the side wall of the gate electrode that is no longer surrounded by the side wall spacer by removing a part of the side wall spacer. Forming a semiconductor connection portion for electrically connecting the gate electrode and the well region.

  According to the method for manufacturing a semiconductor device of the invention, since the electrical connection between the gate electrode and the well region is not performed by the contact plug reaching the upper wiring layer, the wiring arrangement is not affected. High integration of a semiconductor integrated circuit device having a transistor in which a well region and a well region are electrically connected can be achieved. Further, since the semiconductor connection portion of the electrical connection portion between the gate electrode and the well region is formed in a self-aligned manner with respect to the gate electrode, the gate electrode and the well region are not increased without increasing the area of the element. Thus, the electrical connection can be reliably performed, and the yield can be improved.

  As apparent from the above, according to the semiconductor device of the present invention, the gate electrode and the well region are electrically connected by the structure in which the gate electrode is electrically connected to the well region through the semiconductor connection portion. Since the contact plug is not required in the portion where the gate electrode is connected, the semiconductor integrated circuit device having a transistor in which the gate electrode and the well region are electrically connected is highly integrated without affecting the wiring arrangement of the upper wiring layer. be able to. Further, since the semiconductor connection portion is formed thicker than the silicide film on the side wall of the gate electrode, the yield can be improved as compared with the case where the gate electrode and the well region are electrically connected by the silicide film.

  Also, according to one embodiment, the semiconductor connection portion that electrically connects the gate electrode and the well region is gradually thickened from the element isolation region toward the gate electrode. It is mitigated and the productivity of the subsequent manufacturing process can be increased. For example, there are an effect that the planarization of the interlayer insulating film layer is facilitated, an effect that a margin of etching conditions when the contact hole is formed by etching is widened, and the like.

  Further, according to the method of manufacturing a semiconductor device of the present invention, the gate electrode and the well region are connected to the semiconductor connection portion without using a contact plug that affects the arrangement of the wiring for the electrical connection between the gate electrode and the well region. Therefore, high integration of the semiconductor integrated circuit device can be achieved. Since the semiconductor connection portion that electrically connects the gate electrode and the well region is formed in a self-aligned manner with respect to the gate electrode, the electrical connection between the gate electrode and the well region is not increased without increasing the area of the element. Connection can be reliably performed, and the yield of a semiconductor integrated circuit device having a transistor in which a gate electrode and a well region are electrically connected can be improved.

  Hereinafter, embodiments of the present invention will be described in detail.

  In the present specification, the first conductivity type means p-type or n-type. The second conductivity type means n-type when the first conductivity type is p-type, and p-type when the first conductivity type is n-type.

  A preferred embodiment of a semiconductor device of the present invention will be described with reference to FIG. 1A is a plan view of the semiconductor device, FIG. 1B is a cross-sectional view taken along a line AA in FIG. 1A, and FIG. It is sectional drawing in the cut surface BB of a).

  The semiconductor device according to the embodiment of the present invention is formed on a deep well region (or insulator layer) 2 on a semiconductor substrate 1 as shown in FIGS. A well region 11 and an element isolation region 12 are formed on the deep well region 2. The polarity of the well region 11 and the conductivity type of the deep well region 2 are different. That is, the second conductivity type well region 11 is formed on the first conductivity type deep well region 2. A gate insulating film 13 is formed on the well region 11, and a gate electrode 14 is formed on the gate insulating film 13. An insulating sidewall spacer 15 is formed on the sidewall of the gate electrode 14. However, the insulating side wall spacer 15 is not formed on the side wall of the gate electrode 14 in a portion that electrically connects the gate electrode 14 and the well region 11. A semiconductor connection portion 17 is formed in contact with the side wall of the gate electrode 14 at a portion where the gate electrode 14 and the well region 11 are electrically connected. In addition, semiconductor materials 18 and 19 are formed in portions to be source / drain regions. A contact region 20 having a high impurity concentration of the second conductivity type is formed below a portion where the semiconductor connection portion 17 and the well region 11 are in contact with each other. Regions 21 and 22 having a high impurity concentration of the first conductivity type are formed below the portions where the semiconductor regions 18 and 19 to be the source / drain regions are in contact with the well region 11. A silicide film 24 is formed on the gate electrode 14 and the semiconductor connection portion 17. Silicide films 23 and 25 are formed on the semiconductor materials 18 and 19 to be the source / drain regions. A silicon nitride film 16 is formed on the element isolation region 12 except for a part of the region.

  Further, as shown in FIG. 1A, the gate electrode 14 includes an electrode portion 14A located above the channel region sandwiched between the high impurity concentration regions 21 and 22 in the well region 11, and its electrode. The pad portion 14B is wider than the portion 14A. The gate electrode 14 includes a first conductivity type portion 14a and a second conductivity type portion 14b as shown in FIG. The boundary between the first conductivity type portion 14a and the second conductivity type portion 14b is located in the pad portion 14B of the gate electrode 14 to prevent the effective channel width from being narrowed and the drive current from being lowered. The silicide film 24 reduces the resistance between the first conductivity type portion 14 a of the gate electrode 14 and the second conductivity type portion 14 b of the gate electrode 14.

  The gate electrode 14 is electrically connected to the well region 11 through the semiconductor connection portion 17 and the contact region 20 having a high impurity concentration, and reaches the upper wiring layer in the electrical connection between the gate electrode 14 and the well region 11. Since no contact plug is used, the wiring arrangement is not affected. As a result, high integration of a semiconductor integrated circuit device having a transistor in which the gate electrode 14 and the well region 11 are electrically connected can be achieved. In addition, since the semiconductor connection portion 17 is easier to be formed on the side wall of the gate electrode 14 than the silicide film, the electrical connection between the gate electrode 14 and the well region 11 can be reliably performed. The yield of a semiconductor integrated circuit device having a transistor in which the electrode 14 and the well region 11 are electrically connected can be improved.

  2 to 9 illustrate a preferred method for manufacturing a semiconductor device in which a gate electrode and a well region are electrically connected.

  First, as shown in FIG. 2, the first conductivity type deep well region (or insulator layer) 2 formed on the semiconductor substrate 1 is subjected to a first STI (Shallow Trench Isolation) technique and an ion implantation technique. A two-conductivity well region 11 and an element isolation region 12 are formed. The element isolation region 12 is formed so that the well regions 11 of adjacent elements are electrically isolated from each other. 3 to 9, the semiconductor substrate 1 shown in FIG. 2, the deep well region (or insulator layer) 2, and a part below the element isolation region 12 are omitted.

  Next, as shown in FIG. 3, a gate insulating film 13 is formed on the well region 11, and a gate electrode 14 is formed on the gate insulating film 13. The material of the gate insulating film 13 is not particularly limited as long as it has an insulating property. In the embodiment of the present invention, a silicon nitride oxide layer having a thickness of 2 to 5 nm is formed as the gate insulating film 13. If necessary, silicon oxide, silicon nitride, other dielectrics and combinations thereof may be used. The gate electrode 14 is formed by forming a pattern of the silicon oxide film 31 on a polysilicon layer deposited to a thickness of 100 to 350 nm using a well-known photolithography technique and dry etching technique, and then forming a polysilicon layer. It is desirable to form by dry etching. The gate electrode 14 is preferably made of polysilicon, but if necessary, metal, single crystal silicon, or a combination thereof may be used. The silicon oxide film layer 31 is not limited to a silicon oxide film as long as it is a material that becomes a mask when the polysilicon layer is etched.

  Next, as shown in FIG. 4, after depositing an insulating film layer (not shown), well-known dry etching is performed to form an insulating sidewall spacer 15 on the sidewall of the gate electrode 14. The insulating film layer is preferably a silicon nitride film deposited to a thickness of about 5 to 100 nm using a CVD (Chemical Vapor Deposition) method, but the silicon oxide film layer 31 is etched. The material may be any material having etching resistance, and is not limited to the silicon nitride film.

  Next, as shown in FIG. 5, a part of the insulating side wall spacer 15 corresponding to a portion where the gate electrode 14 and the well region 11 are electrically connected is removed by a known photolithography technique and dry etching technique. In the dry etching technique for removing a part of the insulating side wall spacer 15, when a chemical dry etching method not exposed to ions is used, a part of the insulating side wall spacer 15 is removed without damaging the well region 11. It can be removed efficiently.

  Next, as shown in FIG. 6, a semiconductor material 61 is formed so as to surround the gate electrode 14 and outside the side wall of the insulating side wall spacer 15. The semiconductor material 61 is formed by etching back a polysilicon layer deposited by LPCVD (Low Pressure Chemical Vapor Deposition) method to a thickness of 400 to 800 nm by a well-known dry etching technique. Is desirable.

  When the semiconductor material 61 is formed by LPCVD and then etched back, the semiconductor material 61 gradually increases in thickness from the element isolation region 12 toward the gate electrode 14 as shown in FIG. Therefore, the vertical step due to the gate electrode 14 is relaxed, and the productivity of the subsequent manufacturing process can be increased. For example, the interlayer insulating film layer can be easily flattened and the etching condition margin when the contact hole is formed by etching is increased. At this time, since the semiconductor material 61 surrounds the periphery of the gate electrode 14 in a ring shape, the portions serving as the source and the drain are short-circuited.

  When depositing the polysilicon layer, it is important that the native oxide film is not grown at the interface with the well region 11. When a natural oxide film grows at the interface between the surface of the well region 11 and the deposited polysilicon layer, an impurity that becomes a donor (or acceptor) is introduced into the polysilicon layer by ion implantation in a later step, and then heat treatment is performed. When a junction is formed by thermally diffusing impurities in the semiconductor substrate, the natural oxide film serves as an impurity diffusion barrier, and uniform impurity diffusion is inhibited. For this reason, the junction depth of the source and drain becomes non-uniform, which causes the transistor characteristics to vary.

  In the embodiment of the present invention, the polysilicon layer is formed by the pre-exhaust chamber, the nitrogen purge chamber in which the dew point is always kept at −100 ° C. or less, and the LPCVD apparatus equipped with the deposition furnace, so that a natural oxide film is grown. It is possible to grow polysilicon without losing.

  Specifically, the substrate is washed with a hydrofluoric acid-based solution immediately before depositing the polysilicon layer, the natural oxide film is once removed, and then transferred to the preliminary vacuum exhaust chamber. The air atmosphere at the time of transfer is once evacuated and then replaced with a nitrogen atmosphere and transferred to a nitrogen purge chamber in which the dew point is kept at -100 ° C. or lower. Here, the role of the preliminary exhaust chamber is to prevent air during transport from entering the nitrogen purge chamber. Even if it is a very small amount of air, if air is mixed into the nitrogen purge chamber, it takes several days to recover the atmosphere below -100 ° C., and the throughput is extremely deteriorated. The role of the nitrogen purge chamber is to completely remove water molecules adsorbed on the wafer surface by nitrogen purge. Experiments have confirmed that water molecules adsorbed on the wafer surface can be completely removed by nitrogen purge.

  In an ordinary LPCVD apparatus, water molecules that cannot be removed are transported to the deposition furnace while adsorbed on the wafer surface. Since an ordinary polysilicon film is formed at a temperature of about 550 ° C. to 650 ° C., water molecules adsorbed when the wafer is transferred to a deposition furnace maintained at this temperature and oxygen in the atmosphere are formed by silicon. The natural oxide film grows before reacting with the wafer and forming the polysilicon layer. As a result, a natural oxide film grows at the interface between the polysilicon layer and the well region 11. However, in the LPCVD apparatus according to the present embodiment, as described above, the system in which the water molecules adsorbed in the nitrogen purge chamber in which the dew point is always kept at −100 ° C. or lower is completely removed and then transferred to the deposition furnace. Therefore, it is possible to form a polysilicon layer without growing a natural oxide film. Therefore, the impurities can be smoothly diffused into the well region 11 and a uniform junction can be formed with good controllability.

  The semiconductor material 61 may be selectively deposited so as to be formed only on exposed silicon surfaces such as the well region 11 and the gate electrode 14. When the semiconductor material 61 is selectively deposited, it is necessary to deposit the film so that the film deposited on the side wall of the gate electrode 14 and the film deposited on the well region 11 are in sufficient contact. It is necessary to deposit at least thicker than the gate insulating film 13. As an effect of selectively depositing the semiconductor material 61, the semiconductor material 61 is formed only on the silicon surface (exposed surface of the well region 11 and the gate electrode 14) and is not formed on the element isolation region 12. There is an effect that the step of separating the semiconductor material 61 by using the photolithography and etching techniques to be described can be omitted.

  Further, the semiconductor material 61 is preferably made of polysilicon having a high solid diffusion rate of impurities, but amorphous silicon, single crystal silicon, a silicon / germanium alloy, or a combination thereof may be used.

  Next, as shown in FIG. 7, the semiconductor material 61 is mixed with one of the source / drain regions (semiconductor material 18), the other of the source / drain regions (semiconductor material 19), the gate electrode 14 and the well region 11. And an electrical connection portion (semiconductor connection portion 17). In the embodiment of the present invention, after the silicon oxide film 31 on the gate electrode 14 is removed by dilute hydrofluoric acid treatment, a part of the semiconductor material 61 is removed by using a photolithography technique and a dry etching technique, so that the semiconductor The material 61 is separated.

  Next, as shown in FIG. 8, impurities are implanted into the semiconductor connection portion 17, the semiconductor materials 18 and 19, and the gate electrode 14 using a well-known photolithography technique and ion implantation technique. In the impurity implantation, in the impurity implantation into the semiconductor connection portion 17 where the gate electrode 14 and the well region 11 are electrically connected, ions implanted so that the semiconductor connection portion 17 has the same conductivity type as the well region 11. In selecting impurities and implanting impurities into the semiconductor materials 18 and 19 that are part of the source / drain regions, ion species are selected so that the semiconductor materials 18 and 19 have a different conductivity type from the well region 11. In the embodiment of the present invention, ion implantation is performed so as to ensure that the semiconductor connection portion 17 has the second conductivity type. Therefore, a part of the gate electrode 14 has the second conductivity type, and the first conductivity type It is divided into a portion 14a and a second conductivity type portion 14b. Further, by performing impurity implantation so that the boundary between the first conductivity type portion 14a and the second conductivity type portion 14b of the gate electrode 14 is located in the pad portion 14B of the gate electrode 14, the effective channel width is increased. A decrease in drive current due to narrowing can be prevented.

For example, when As ions are used as the impurity ions, the impurity implantation is performed by implanting an amount of about 1 × 10 ¹⁵ to 2 × 10 ¹⁶ cm ⁻² with an implantation energy of about 10 to 180 keV. In the case where P ions are used, an amount of about 1 × 10 ¹⁶ to 2 × 10 ¹⁶ cm ⁻² is implanted with an implantation energy of about 5 to 100 keV, and B ions are used as impurity ions. Can be performed by implanting an amount of about 1 × 10 ¹⁶ to 2 × 10 ¹⁶ cm ⁻² with an implantation energy of about 5 to 40 keV.

  After the impurity implantation, annealing for impurity activation is performed, so that the contact region 20 having a high impurity concentration is formed by impurity diffusion from the semiconductor connection portion 17, and the regions 21 and 22 having a high impurity concentration are formed by the semiconductor material 18. , 19 is formed by impurity diffusion. The annealing for activating the impurities is desirably performed so that the tips of the regions 21 and 22 having a high impurity concentration reach at least the outer edge of the gate electrode 14. A contact region 20 having a high impurity concentration is formed below the semiconductor connection portion 17 so that the gate electrode 14 and the well region 11 are ohmically connected.

  Next, as shown in FIG. 9, an electrical connection between the semiconductor materials 18 and 19, which are part of the source / drain region, the gate electrode 14, and the gate electrode 14 and the well region 11 is performed by a known salicide technique. A refractory metal silicide film is selectively formed on the semiconductor connection portion 17 which is a simple connection portion. The refractory metal used for salicide is preferably made of Co, but Ti, Ni, or a combination thereof may be used.

  Thereafter, the semiconductor device of the present invention can be manufactured by forming contact holes, wirings and the like (not shown) by a known method.

1A is a plan view of a semiconductor device according to an embodiment of the present invention, FIG. 1B is a cross-sectional view taken along the line AA, and FIG. It is sectional drawing in a cut surface. 2A is a plan view for explaining the method for manufacturing the semiconductor device, FIG. 2B is a cross-sectional view taken along the line AA, and FIG. 2C is a cross-sectional view taken along the line BB. It is sectional drawing in a surface. 3A is a plan view for explaining the method for manufacturing the semiconductor device subsequent to FIG. 2C, FIG. 3B is a cross-sectional view taken along the line AA, and FIG. These are sectional drawings in a BB cut surface. 4A is a plan view for explaining the method for manufacturing the semiconductor device subsequent to FIG. 3C, FIG. 4B is a cross-sectional view taken along the line AA, and FIG. These are sectional drawings in a BB cut surface. 5A is a plan view for explaining the method for manufacturing the semiconductor device subsequent to FIG. 4C, FIG. 5B is a cross-sectional view taken along the line AA, and FIG. These are sectional drawings in a BB cut surface. 6A is a plan view for explaining a method for manufacturing a semiconductor device subsequent to FIG. 5C, FIG. 6B is a cross-sectional view taken along the line AA, and FIG. These are sectional drawings in a BB cut surface. FIG. 7A is a plan view for explaining the method for manufacturing the semiconductor device subsequent to FIG. 6C, FIG. 7B is a cross-sectional view taken along the line AA, and FIG. These are sectional drawings in a BB cut surface. FIG. 8A is a plan view for explaining a method for manufacturing a semiconductor device following FIG. 7C, FIG. 8B is a cross-sectional view taken along the line AA, and FIG. It is sectional drawing in a BB cut surface. FIG. 9A is a plan view for explaining the method for manufacturing the semiconductor device subsequent to FIG. 8C, FIG. 9B is a cross-sectional view taken along the line AA, and FIG. These are sectional drawings in a BB cut surface. FIG. 10 is a cross-sectional view showing the structure of a DT-MOS transistor as a conventional first semiconductor device. FIG. 11 is a cross-sectional view showing the structure of a DT-MOS transistor as a conventional second semiconductor device.

Explanation of symbols

1 ... Semiconductor substrate 2 ... Deep well region (or insulator layer)
DESCRIPTION OF SYMBOLS 11 ... Well region 12 ... Element isolation region 13 ... Gate insulating film 14 ... Gate electrode 14A ... Electrode part 14B ... Pad part 14a ... First conductivity type part 14b ... Second conductivity type part 15 ... Side wall spacer 16 ... Silicon nitride Film 17 ... Semiconductor connection portion (electrical connection portion between gate electrode and well region)
18 ... Semiconductor material (part of source / drain region)
19 ... Semiconductor material (part of source / drain region)
20 ... second conductivity type high impurity concentration contact region 21 ... first conductivity type high impurity concentration region 22 ... first conductivity type high impurity concentration region 23-25 ... silicide film 31 ... silicon oxide film 61 ... Semiconductor material 101 ... Underlying wafer 102 ... Silicon oxide film 103 ... p-type silicon layer 104 ... element isolation oxide film 105 ... gate oxide film 106 ... gate electrode 108 ... interlayer insulating film 109 ... p ⁺ type diffusion layer 110 ... contact plug and Al Interconnect 201 ... Semiconductor substrate 202 ... Element isolation region 203 ... Deep well region 204 ... Shallow well region 205 ... Gate oxide film 206 ... Gate electrode 207 ... Gate electrode sidewall insulating film 208 ... High-concentration diffusion layer contact region 209 ... Refractory metal silicide film

Claims (5)

A well region and an element isolation region formed on a semiconductor substrate;
A gate insulating film formed on the well region;
A gate electrode formed on the gate insulating film;
An insulating sidewall spacer formed so as to surround the gate electrode except for a part of the outer edge of the gate electrode and to be in contact with the sidewall of the gate electrode;
The semiconductor device further comprises a semiconductor connection portion formed so as to be in contact with a part of the side wall of the outer edge of the gate electrode where the side wall spacer is not formed, and electrically connecting the gate electrode and the well region. Semiconductor device. The semiconductor device according to claim 1,
The semiconductor device, wherein the semiconductor connection portion is formed so as to gradually increase in thickness from the element isolation region side toward the side wall side of the gate electrode. The semiconductor device according to claim 1, wherein
A semiconductor device, wherein a contact region having an impurity concentration higher than that of a region under the gate electrode is provided on a surface side of the well region electrically connected to the semiconductor connection portion. A semiconductor device according to any one of claims 1 to 3,
The semiconductor connection portion has the same conductivity type as the well region,
The semiconductor device according to claim 1, wherein the gate electrode is made of a semiconductor, and at least a part of which the side wall is in contact with the semiconductor connection portion has the same conductivity type as the semiconductor connection portion. Forming a well region and an element isolation region on a semiconductor substrate;
Forming a gate insulating film on the well region;
Forming a gate electrode on the gate insulating film;
Forming an insulating sidewall spacer so as to surround the gate electrode and to be in contact with the sidewall of the gate electrode;
Removing a part of the side wall spacer so that a part of the side wall of the gate electrode is not surrounded by the side wall spacer;
A semiconductor connection portion that electrically connects the gate electrode and the well region is formed so as to be in contact with a part of the side wall of the gate electrode that is no longer surrounded by the side wall spacer by removing a part of the side wall spacer. A method of manufacturing a semiconductor device.

Images