JP3187314B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor equipment. More particularly, the present invention is, junction leakage is low, and to a manufacturing method of the hardly elevated junction transistor of Tanchi catcher, channel effects.

[0002]

2. Description of the Related Art With the increase in the degree of integration of large-scale integrated circuits (LSIs), the size of MOS field-effect transistors (MOSFETs) constituting LSIs has been increasingly reduced. In order to further improve the degree of integration or to increase the operation speed, it is necessary to further reduce the gate length of the MOSFET. However, the conventional MO
In the SFET, the short channel effect was likely to occur because the PN junction formed between the source / drain region and the semiconductor substrate was inevitably at a position (deep position) apart from the main surface of the semiconductor substrate. The conventional MOSFET has a problem that it is difficult to shorten the gate length in order to avoid characteristic deterioration due to the short channel effect.

For the purpose of solving this problem, a MOSFET having a structure as shown in FIG. 5B has been proposed (JP-A-61-196577). The MOSF shown in FIG.
ET is manufactured as follows.

First, as shown in FIG. 5A, an active region and a field oxide film 502 are formed on a main surface of a single crystal silicon substrate 501. Although only one active region is shown in FIGS. 5A and 5B, in an actual LSI, a large number of active regions are formed on the main surface of one silicon substrate 501, and these active regions are formed. The regions are electrically separated from each other by a field oxide film 502. Next, the gate insulating film 503, the gate electrode 504, and the insulating film 505 covering the surface of the gate electrode 504 are formed by a known manufacturing technique, and the structure in FIG. 5A is obtained.

Thereafter, a semiconductor layer (silicon layer) 506 is selectively epitaxially grown on a portion of the active region of the silicon substrate 501 where the silicon surface is exposed. The semiconductor layer (epitaxially grown layer) 506 grown epitaxially is doped with an impurity, and the impurity is diffused from the epitaxially grown layer 506 to the vicinity of the surface of the silicon substrate 501. Thus, a PN junction is formed at a relatively shallow position (at a position having a depth of about 30 to 80 nm) from the main surface of the silicon substrate.

The MOSFET shown in FIG. 5B is sometimes called a “stacked diffusion layer type transistor”. This is because the diffusion layers functioning as source / drain regions
This is because it is formed by an epitaxial growth layer (stacked layer) in which impurities are diffused and a thin impurity diffusion layer near the surface of the silicon substrate 501.

[0007]

The above prior art has the following problems.

[0008] 1. Structural Problems When the epitaxial growth layer 506 is formed by using the selective epitaxial growth method, a facet is inevitably formed near the side surface of the gate electrode 504, as shown in FIG. In the portion where the facet is formed, the thickness of the epitaxial growth layer 506 is smaller than in other portions. For this reason, when an impurity is doped into the epitaxial growth layer using an impurity doping technique such as solid phase diffusion, vapor phase diffusion, or ion implantation, and a heat treatment for activating the impurity is performed, the impurity diffusion formed in the silicon substrate 501 is reduced. The impurity concentration profile of the layer changes from the design value. More specifically, the silicon substrate 50
The PN junction formed in the substrate 1 becomes locally deep immediately below the facet (for example, 100 to 15).
Therefore, the short channel effect cannot be sufficiently suppressed.

[0009] 2. Problems of the Stacked Structure Forming Method Since the silicon selective epitaxial growth technique uses a large amount of hydrogen, the scale of the apparatus is large and the manufacturing cost is high. In addition, the pre-treatment temperature of the epitaxial growth (1000
° C or higher) and the growth temperature (900 ° C to 1100 ° C) are high, so that the impurity is easily diffused deeply, and it is difficult to control the impurity concentration profile to a desired shape. Further, since relatively large thermal stress is generated, crystal defects are likely to occur near the gate electrode 504 and near the edge of the field oxide film 502, and the leak current increases.

The present invention has been made in view of the above problems, and has as its object to reduce junction leakage,
And to provide a Tanchi catcher Ne manufacturing method of hardly semiconductor equipment Le effects.

[0011]

[0012]

[0013]

[0014]

[0015]

[0016]

SUMMARY OF THE INVENTION A semiconductor device according to the present invention is manufactured.
In the fabrication method, an active region and an element isolation region are provided on the main surface.
Forming a gate insulating film on the active region on the semiconductor layer
Forming a gate electrode on the gate insulating film.
Forming a gate upper insulating film on the gate electrode
Process and an insulating sidewall on the sidewall of the gate electrode
Forming a spacer film, and forming the gate upper insulating film and
And a conductive thin film covering the sidewall spacer film.
Or a step of depositing a semiconductor film and a chemical mechanical polishing method
Selectively removes a part of the conductor thin film or semiconductor film.
To expose the gate top insulating film, thereby
Forming an L-shaped conductor layer from the conductor thin film
Polishing step of forming an L-shaped semiconductor layer from a conductor film
The polishing step uses a solution to which abrasive grains are added.
Performed, have rows with a polishing cloth has a two-layer structure of a hard pad and a soft pad grooves of 5mm in width 2 are arranged at a pitch of 40mm from 15 to surface thereby the object
Is achieved.

The method of manufacturing a semiconductor device according to the present invention mainly comprises
On semiconductor layer with active region and element isolation region on the surface
Forming a gate insulating film on the active region,
Forming a gate electrode on the gate insulating film;
Forming a gate upper insulating film on the gate electrode;
Insulating sidewall spacer film on the side wall of the gate electrode
Forming step, the gate upper insulating film and the side wall.
Conductor thin film or semiconductor covering the spacer film
The process of depositing a film and the chemistry using a solution containing abrasive grains
Of the conductor thin film or semiconductor film by a mechanical polishing method
Selectively removing a portion to expose the gate upper insulating film,
Thereby, an L-shaped conductor layer is formed from the conductor thin film.
Or forming an L-shaped semiconductor layer from the semiconductor film
And polishing step, an ion implantation step of the impurity ions of the second conductivity type is injected into the L-shaped conductor layer or the L-shaped semiconductor layer, the L-shaped conductor layer or of the L-shaped semiconductor layer the impurity-activated, and includes a heat treatment step of forming a source region and a drain region, the ion implantation step, implanting the impurity in an oblique direction to the main surface of the <br/> semiconductor layer der is, thereby the objective described above being achieved.

[0018] The heat treatment step, the L-shaped conductor layer or
Or diffusing the impurity from the L-shaped semiconductor layer into the semiconductor layer , thereby forming a shallow junction in the semiconductor layer that functions as a part of the source region and the drain region.

Preferably, in the ion implantation step, the impurity ions are implanted at an acceleration energy that does not reach the semiconductor layer.

[0020] The ion implantation process, wherein the L-shaped conductor layer the impurity ions at an angle in the range of 30 to 90 degrees to the main surface of the semiconductor layer or the L-shaped semiconductor layer <br/> It is preferable to inject the solution.

[0021] The method further comprises, after removing the upper gate insulating film, depositing a silicon nitride film on the L-shaped conductor layer or the L-shaped semiconductor layer. Preferably, the impurity ions are implanted into the L-shaped conductor layer or the L-shaped semiconductor layer via a silicon nitride film.

[0022] In certain embodiments, the L-shaped conductor layer or
Or forming the L-shaped semiconductor layer from a silicon layer, further removing the silicon nitride film, and depositing a refractory metal film on the L-shaped conductor layer or the L-shaped semiconductor layer. Process and the L-shaped conductive layer or the L-shaped semiconductor
Reacting the silicon layer of the body layer with the refractory metal film to form a refractory metal silicide layer.

In the silicidation step, a titanium film is deposited as the refractory metal film, and in one embodiment, the titanium film is reacted with the silicon layer by a first heat treatment to form a first crystal structure. first titanium silicide layer using the gate electrode and the L-shaped conductor layer having also
Forming the L-shaped semiconductor layer includes the steps of removing the unreacted portion not silicided of the titanium film, the second heat treatment, the first titanium silicide film, said Changing to a second titanium silicide film having a second crystal structure that is more stable than the first crystal structure.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Conventionally, it has been considered that a special technique of selective epitaxial growth on a portion functioning as a source / drain region in an active region must be used as a method of forming a stacked semiconductor layer. This is because it has been considered that the source region and the drain region are short-circuited by a normal CVD method, so that a separated stacked semiconductor structure cannot be formed.
However, the inventor of the present invention has found that a desired stacked semiconductor structure can be formed by using a chemical mechanical polishing method while using a normal CVD method, and has reached the present invention.

According to the present invention, a pair of L-shaped conductor layers serving as source and drain regions, which are stacked above a channel portion of a transistor, are provided on both sides of a gate electrode via insulating sidewall spacer films. ing. The present invention solves the problem of facet generation accompanying selective epitaxial growth, and makes it possible to form the PN junction depth at the gate-side drain end of the source / drain region very shallowly and with good controllability. Since such a shallow junction is provided, DIBL (Drain-Induced Ba) is caused by a two-dimensional effect at the channel-side edge of the source / drain region.
rrier Lowering), and as a result, the short channel effect can be reduced. In addition, since the source and the drain can be separated without using the selective epitaxial growth method, the problems that have conventionally been encountered, such as a large-scale manufacturing apparatus and a very high manufacturing cost, can be solved. In addition, since high-temperature treatment such as selective epitaxial growth is not required, it is easy to control the concentration profile of impurities (for example, impurities for controlling threshold voltage).

An embodiment of the present invention will be described below with reference to the drawings.

(Embodiment 1) A first embodiment of a semiconductor device according to the present invention will be described with reference to FIGS. 1 (a) to 1 (g). Here, the present invention is applied to an n-channel type MOSFET.
Will be described, but a p-channel type MO
It goes without saying that the present invention can be applied to the SFET.

First, as shown in FIG. 1A, a 400 nm-thick field oxide film (LOCOS film) is formed in an element isolation region on the main surface (plane orientation is (100)) of a p-type single crystal silicon substrate 101. 102 is selectively formed. The region where the field oxide film 102 is not formed on the main surface of the silicon substrate 101 becomes the active region 107. Although a plurality of active regions 107 are formed, only one active region is shown in the drawing for simplicity.

Next, a gate oxide film 103 having a thickness of 4 nm, a gate electrode 105 having a thickness of 100 to 150 nm, and a gate upper insulating film 104 having a thickness of 150 to 250 nm are formed by known techniques. In this embodiment, the upper gate insulating film 104 is formed from a silicon oxide film, and the gate electrode 105 is formed from a polycrystalline silicon film. In this embodiment, the gate length is set in the range of about 0.1 to 0.15 μm.

Next, low pressure chemical vapor deposition (LPCVD)
A silicon nitride film having a thickness of 20 to 50 nm is deposited by a method so as to cover the entire surface of the silicon substrate 101. afterwards,
The silicon nitride film is etched back by a reactive ion etching (RIE) technique without using an etching mask. The etch-back is performed until portions 107a and 107c of the active region 107 of the silicon substrate 101 other than the portion where the gate electrode 105 is formed (portion 107b serving as a channel region) are exposed. As a result of this etch-back, part of the silicon nitride film remains on the side walls of the gate electrode 105 and the upper gate insulating film 104, thereby forming an insulating sidewall spacer film. The width (thickness measured along the channel length direction) of the sidewall spacer film 106 is substantially equal to the thickness of the silicon nitride film. However, if the etch-back time is set relatively long, the width of the sidewall spacer film 106 can be made smaller than the thickness of the silicon nitride film immediately after deposition.

Next, the surfaces of the exposed portions 107a and 107c of the active region 107 are sequentially subjected to an ashing process using oxygen plasma, a cleaning process, an HF process, an ammonia peroxide process (silicon etching), and an HF process. Do. In order to realize low contact resistance, pretreatment such as cleaning is important. Thereafter, as shown in FIG. 1B, a polycrystalline silicon film 1 having a thickness of 100 to 150 nm is formed.
08a is deposited by the LPCVD method. In this example, the polycrystalline silicon film 108a was deposited under the following conditions.

Deposition temperature: 550-700 ° C. Gas type: SiH ₄ , Flow rate: 100-200 sccm
Pressure: 15 to 50 Pa By depositing the polycrystalline silicon film 108a in this manner, a natural oxide film is prevented from intervening at the interface between the polycrystalline silicon film 108a and the active regions (107a and 107c) of the silicon substrate 101. it can. Here, the silicon film called the polycrystalline silicon film 108a is LP
Depending on the airtightness of the CVD apparatus and the pre-deposition treatment, the film may be substantially epitaxially grown. However,
Even in such a case, a polycrystalline silicon portion is formed on the amorphous film such as the sidewall spacer film 106, and the trapezoidal shape due to the facet is not necessarily formed. Therefore, as described later, the gate electrode 10
5 must be removed by polishing.

The thickness of the polycrystalline silicon 108a is selected to be smaller than the total thickness of the gate electrode 105 and the gate upper insulating film 104. this is,
By the polishing step, “L”
This is for forming a "shaped" semiconductor layer. It is preferable that the thickness of the polycrystalline silicon film 108a be smaller than the thickness of the gate electrode 105. By using the relatively thin polycrystalline silicon film 108a as described above, the possibility that the flat portion of the polycrystalline silicon film 108a near the gate is polished is reduced. Polishing allows the polycrystalline silicon film 108
If the thickness of the flat portion a changes, the impurity diffusion layer described later cannot be formed with good reproducibility.

Next, a portion of the polycrystalline silicon film 108a located above the gate electrode 105 is selectively polished and removed by a chemical mechanical polishing method (CMP method) until the upper gate insulating film 104 is exposed. . Thus, FIG.
As shown in (c), the polycrystalline silicon film 108a is separated above the gate electrode 105. Since the cross-sectional shape of the separated polycrystalline silicon 108a resembles the letter L of the alphabet, in this specification, the separated pair of semiconductor layers (stacked semiconductor layers) are each referred to as an L-shaped semiconductor layer 108.
b.

Here, the L-shaped semiconductor layer 108b has a flat layer portion deposited on the active regions 107a and 107c, and the side wall spacer film 106 of the flat layer portion.
And a protruding portion adjacent to. The thickness of the flat layer portion is smaller than the thickness of the gate electrode 105 and has a substantially uniform thickness. Further, the tip of the protruding portion has reached a level higher than the level of the upper surface of the flat layer portion. In this embodiment, the tip of the protruding portion has reached a level higher by about 50 to 150 nm than the level of the upper surface of the flat layer portion. Here, the angle formed between the surface of the protruding portion and the surface of the flat layer portion does not necessarily need to be 90 °. The angle changes depending on the shape of the sidewall spacer film 106. FIG. 6 shows the L-shaped semiconductor layer 108b when a relatively thick sidewall spacer film 106 having a surface inclined with respect to the main surface of the substrate is provided. In FIG. 6, the angle θ formed between the surface of the protruding portion and the surface of the flat layer portion
Is greater than 90 °. Such an L-shaped semiconductor layer 1
08b, the effect of the present invention can be sufficiently obtained.

The L-shaped semiconductor layer 108b may be formed not of a complete polycrystalline silicon film but of a silicon film having both an epitaxial growth layer portion and a polycrystalline silicon portion. Also, the L-shaped semiconductor layer 108
The film to be b may be in an amorphous state immediately after its deposition.

The above-mentioned polishing step is performed by using a soft type polishing cloth (for example, SUDA5 manufactured by RODEL) used for conventional silicon polishing (mirror polishing of a silicon wafer or overall etch back for embedding a trench in polysilicon).
00), some of the MOSFETs
For the OSFET, the removal of the silicon film on the gate electrode 105 is not sufficiently completed, and the source-side L-shaped semiconductor layer 108b and the drain-side L-shaped semiconductor layer 108b are short-circuited on the gate electrode 105. This causes a problem. According to the conventional polishing technique, the polishing rate of silicon in the region where the plurality of gate electrodes 105 are densely arranged on the silicon substrate 101 and the region where the gate electrodes 105 are relatively isolated are reduced. This is because polishing is performed only insufficiently in some regions because of the difference. On the other hand, in the present invention, a hard polishing pad having a two-layer structure of hard and soft, which has been conventionally used for planarizing an oxide film, is used. The problem was improved by setting the range of 15 mm to 40 mm. More specifically, the surface has a width of 4 mm (pitch 30 m
m) A hard pad with a groove (IC1 manufactured by RODEL)
000) and a soft pad (SUDA400 manufactured by RODEL)
H) The pad having a two-layer structure (FIG. 4) was used. As a polishing solution, a solution obtained by adding colloidal silica to an alkali solution is used, and polishing is performed at a polishing pressure of 1.0 to 3.0 psi and a rotation speed of a platen of 30 to 60 rpm. As the polishing conditions, optimal conditions are appropriately set according to a polishing apparatus to be used and the like, and are not limited to these values.

The gate electrode 105 is arranged not only on the active region but also on the field insulating film 102.
Therefore, the height (level) of the upper surface of the gate electrode 105 measured from the main surface of the substrate is not constant. However,
Since the polishing cloth is elastically curved, the gate electrode 10
Regardless of the level of 5, polishing is performed equally. If a device isolation technique (for example, a trench isolation technique) in which a high protrusion is not formed with respect to the main surface of the substrate is used, a more favorable effect can be obtained on the reliability and reproducibility of the polishing process.

During the polishing process, the polycrystalline silicon film 10
It is difficult to detect whether the separation of 8a has been completed and the pair of L-shaped semiconductor layers 108b has been formed thereby. For this reason, it is necessary to carry out a polishing step under various conditions in advance, thereby setting conditions such as an optimal polishing time. However, even if the polishing time is longer than the expected value, the gate electrode 105 is not polished because the upper gate insulating film 104 disposed on the gate electrode 105 functions as a stopper.
Since the silicon nitride film has higher wear resistance than the silicon oxide film, using the silicon nitride film instead of the silicon oxide film as the material of the upper gate insulating film 104 improves the yield of the polishing process. Preferred from a viewpoint. When a silicon nitride film is used as the material of the gate upper insulating film 104, it is preferable to use a film other than the silicon nitride film (for example, a silicon oxide film) as the material of the insulating sidewall spacer film 106. Thus, the sidewall spacer film 106 and the gate upper insulating film 10
The reason for changing the material of No. 4 is to perform a step of selectively removing the gate upper insulating film 104 while leaving the sidewall spacer film 106 after the polishing step. When the selective removal of the gate upper insulating film 104 is not performed, the sidewall spacer film 106 and the gate upper insulating film 104 may be formed from the same material. The case where the selective removal of the gate upper insulating film 104 is not performed includes, for example,
Since the gate electrode 105 is already doped with a high concentration of impurities from the stage before the formation of the gate upper insulating film 104,
This is the case where it is not necessary to implant impurity ions for forming the source / drain into the gate electrode 105 or the case where it is not necessary to silicide the upper part of the gate electrode 105.

Next, as shown in FIG. 1D, the L-shaped semiconductor layer 108b is patterned into a desired shape by using known photolithography and etching techniques. This patterning allows the L of any given MOSFET to be
The semiconductor layer 108b is formed of another MOSFET (not shown).
From the L-shaped semiconductor layer 108b. In this embodiment, the L-shaped semiconductor layer 108b extends not only on the active region but also on the field oxide film 102.
It can also function as a contact pad for the upper wiring.

Next, as shown in FIG. 1E, the gate upper insulating film 104 formed of a silicon oxide film is removed by etching with hydrofluoric acid to form a gate electrode 105 formed of polycrystalline silicon. Expose the surface. Since hydrofluoric acid etches silicon oxide preferentially over silicon nitride, the sidewall spacer film 106 is hardly etched. The gate upper insulating film 1
04 is formed from a silicon nitride film and the sidewall spacer film 106 is formed from a silicon oxide film, the gate upper insulating film 10 is formed using phosphoric acid or the like instead of hydrofluoric acid.
4 can be selectively removed.

Thereafter, by a known impurity doping method (for example, gas phase diffusion, solid phase diffusion, ion implantation, etc.)
The gate electrode 105 and the L-shaped semiconductor layer 106 are doped with an n-type impurity. Thus, the resistance of the gate electrode 105 is reduced, and the pair of L-shaped semiconductor layers 106 function as part of the source / drain regions. By diffusing impurities from the L-shaped semiconductor layer 106 to the surface of the active region of the silicon substrate 101 by an impurity doping process performed at a relatively high temperature or by a heat treatment after the impurity doping process performed at a relatively low temperature, A source / drain region having a "shallow junction" can be obtained.

Thereafter, a MOSFET can be manufactured by forming an interlayer insulating film and wiring by a known method.

Hereinafter, the case where the ion implantation method is used as the impurity doping method will be described in detail.

After forming the structure shown in FIG.
As shown in (f), the conductivity type (p
Impurity ion (As ⁺ ) of the opposite conductivity type (n type)
Is implanted into the L-shaped semiconductor layer 108b. Before the ion implantation step, a cap layer which covers the L-shaped semiconductor layer 108b may be provided.

In this embodiment, impurity ions are implanted with acceleration energy that does not reach the main surface of the silicon substrate 101. More specifically, the dose amount is 1 × 10 ^{15 to} 5
Arsenic ions of × 10 ¹⁵ / cm ² are accelerated at an energy of 40 to
Inject at 60 eV. The injection angle is about 45 °. In a p-channel MOSFET, boron ions or boron fluoride ions are implanted instead of arsenic ions. In this case, as in the case of arsenic ions, 1 × 10 ^{15 to} 5 × 10 ¹⁵ with acceleration energy of 10 to 30 eV. / Cm ² of ion dose is implanted.

In any case, the range Rp in the ion implantation and the standard deviation thereof as ΔRp are given by (Rp + ΔR
p) ≦ distance between abs (2 ^1/2 d for 45 ° injection angle)
(D is the film thickness of the polycrystalline silicon film 108a).

Next, as shown in FIG. 1 (g), heat treatment is performed in a nitrogen atmosphere to activate the implanted impurity ions and at the same time to diffuse them shallowly into the active region, thereby reaching the channel region. Source / drain region 1
Form 10. The source / drain region 110 formed by this heat treatment includes an L-shaped semiconductor layer 108b,
And a thin impurity diffusion layer containing impurities diffused from the L-shaped semiconductor layer 108b into the active region 107.

In this embodiment, the heat treatment is performed at 850 ° C. for 30 minutes or at 900 ° C. for 10 minutes. This allows P
The N-junction reaches a position 30 nm directly below the point a in the vertical direction, and reaches a position 20 nm right next to the point a in the horizontal direction.

Incidentally, boron ions or boron fluoride ions implanted in the case of a p-channel MOSFET are:
Since the range Rp is larger than that of arsenic ions and thermal diffusion is easy, implantation with lower energy may be performed.

In any case, the channel side edge of the PN junction formed as a result of annealing is
1 and is preferably located immediately below the sidewall spacer film 106. It is desirable that the channel-side edge of the PN junction is located at a position directly below the edge of the gate electrode 105 (position indicated by a point c in FIG. 1G).

When there is a PN junction edge at the above position,
In general, when activation and diffusion are performed by heat treatment after ion implantation based on Gaussian distribution, the gate oxide film 103 has a depth-to-width ratio of 1: 0.7 in the impurity diffusion layer region. The depth from the interface of the silicon substrate 101 to the junction is located in the vicinity of {the thickness of the silicon nitride film on the side wall of the gate electrode / 0.7}. If a junction that is too shallower than this is formed, the effective gate length of the transistor becomes longer, and the driving current of the transistor becomes smaller. Conversely, when a deeper junction is formed, the channel-side end of the source / drain region extends below the gate electrode 105, so that the effective gate length is reduced and the short channel effect is liable to occur.

That is, according to this step, it is possible to form a diffusion layer (source and drain regions) having a shallow junction with the silicon substrate 101 and not offset with respect to the gate electrode with good control.

As described above, according to this embodiment, in order to form an L-shaped semiconductor layer, a polycrystalline silicon film having a thickness smaller than the sum of the thickness of the gate electrode and the thickness of the gate upper insulating film is deposited. Then, the polycrystalline silicon film in the vicinity of the gate electrode is polished so as not to cut the flat portion of the polycrystalline silicon film. Therefore, the thickness of the flat portion of the polycrystalline silicon film does not change during the polishing process, and a uniform thickness is provided with high reproducibility. When the thickness of the flat portion of the L-shaped semiconductor layer fluctuates, the impurity concentration profile based on the main surface of the silicon substrate fluctuates, and there is a problem that variations in element characteristics increase. According to this, such a problem does not occur.

In this embodiment, the gate electrode 105 is formed of a polycrystalline silicon film, but may be formed of another conductive material film (for example, a high melting point metal silicide film or a polycide film).

Although the L-shaped semiconductor layer is formed from a polycrystalline silicon film, it may be formed from another semiconductor film. Alternatively, instead of the L-shaped semiconductor layer, an L-shaped conductor layer made of a conductive material other than a semiconductor (for example, silicide or polycide) may be formed.

(Embodiment 2) An embodiment in which the present invention is applied to a salicide transistor will be described below.

First, the structure shown in FIG. 1E is formed by the manufacturing steps described with reference to FIGS. 1A to 1E. At this stage, the impurity doping process for forming the source / drain is not performed. In this embodiment, the gate electrode 105 is formed from a silicon film in order to form a salicide transistor.

Next, as shown in FIG.
A silicon nitride film 109 having a thickness of about 10 to 20 nm is deposited on the L-shaped semiconductor layer 108b by the D method. In this embodiment, an LPC having a cassette chamber and a load lock chamber is provided.
A silicon nitride film 109 is deposited using a VD device. When the silicon nitride film 109 is deposited using such an apparatus, a natural oxide film hardly grows at the interface between the silicon nitride film 109 and the L-shaped semiconductor layer 108b. For this reason,
At the time of implantation of impurity ions described below, the L-shaped semiconductor layer 1
The amount of oxygen knocked on in the area 08b can be reduced as much as possible, thereby preventing the silicide film from deteriorating due to oxygen.

Next, as shown in FIG. 2B, impurity ions (As) of conductivity type (n-type) opposite to the conductivity type (p-type) of silicon substrate 101 are interposed via silicon nitride film 109.
⁺ ) Is implanted into the L-shaped semiconductor layer 108b.

Also in this embodiment, impurity ions are implanted with acceleration energy that does not reach the main surface of the silicon substrate 101. More specifically, the dose amount is 1 × 10 ^{15 to} 5
Arsenic ions of × 10 ¹⁵ / cm ² are accelerated at an energy of 40 to
Inject at 60 eV. The injection angle is about 45 °. Since ions are implanted through the silicon nitride film 109, nitrogen atoms in the silicon nitride film 109 are also implanted into the L-shaped semiconductor layer 108b together with arsenic ions by a knock-on effect of arsenic ions. Note that a p-channel MOS
In the FET, boron ions or boron fluoride ions are implanted instead of arsenic ions. In this case, as in the case of arsenic ions, an acceleration energy of 10 to 30 eV and 1 × 1
Ions are implanted at a dose of 0 ^{15 to} 5 × 10 ¹⁵ / cm ² .

In any case, the range Rp in the ion implantation and its standard deviation as ΔRp are defined as (Rp + ΔR
p) ≦ distance between abs (2 ^1/2 d for 45 ° injection angle)
(D is the film thickness of the polycrystalline silicon film 108a).

Next, as shown in FIG. 2C, a heat treatment is performed in a nitrogen atmosphere to activate the implanted impurity ions and simultaneously diffuse them shallowly into the active region, thereby reaching the channel region. Source / drain region 1
Form 10. The source / drain region 110 formed by this heat treatment includes an L-shaped semiconductor layer 108b,
And a thin impurity diffusion layer containing impurities diffused from the L-shaped semiconductor layer 108b into the active region.

Also in this embodiment, the heat treatment is performed at 850 ° C. for 30 minutes or at 900 ° C. for 10 minutes. This allows P
The N-junction reaches a position 30 nm directly below the point a in the vertical direction, and reaches a position 20 nm right next to the point a in the horizontal direction.

Incidentally, boron ions or boron fluoride ions implanted in the case of a p-channel MOSFET are as follows:
Since the range Rp is larger than that of arsenic ions and thermal diffusion is easy, implantation with lower energy may be performed.

In any case, the channel side edge of the PN junction formed as a result of annealing is
1 and is preferably located immediately below the sidewall spacer film 106. It is desirable that the channel-side edge of the PN junction be located at a position directly below the edge of the gate electrode 105 (position indicated by a point c in FIG. 2C).

If there is a PN junction edge at the above position,
In general, when activation and diffusion are performed by heat treatment after ion implantation based on Gaussian distribution, the gate oxide film 103 has a depth-to-width ratio of 1: 0.7 in the impurity diffusion layer region. The depth from the interface of the silicon substrate 101 to the junction is located in the vicinity of {the thickness of the silicon nitride film on the side wall of the gate electrode / 0.7}. If a junction that is too shallower than this is formed, the effective gate length of the transistor becomes longer, so that the driving current of the transistor becomes smaller. Conversely, when a deeper junction is formed, the channel-side end of the source / drain region extends below the gate electrode 105, so that the effective gate length is reduced and the short channel effect is liable to occur.

Next, as shown in FIG. 2D, after removing the silicon nitride film 109, a titanium film 208 is deposited to a thickness of 30 nm as a refractory metal film. Titanium film 208 and silicon film (gate electrode 105 and L-shaped semiconductor layer 108)
In this example, the following apparatus was used to prevent a natural oxide film from growing on the interface with b). That is, an apparatus (including an argon sputter cleaning chamber) for removing the silicon nitride film 109 and the titanium film 2
A cluster type device connected to a device for depositing 08 (including a titanium sputtering chamber) by a vacuum transfer system was used. 1 × 1 base pressure
From 0 ^-8 to 3 × 10 ^-8 torr, the silicon nitride film 1
After completely removing 09 by argon sputtering, the silicon substrate 101 is vacuum-transported into a titanium sputtering chamber, where a titanium film 208 is deposited. After removing the silicon nitride film 109, the surfaces of the exposed silicon film (the gate electrode 105 and the L-shaped semiconductor layer 108b) are not exposed to the air. Therefore, the titanium film 20 is formed on the silicon surface which is kept clean without being adsorbed by oxygen or water vapor.
8 are performed. If there is no natural oxide film at the interface between the titanium film 208 and the silicon film (the gate electrode 105 and the L-shaped semiconductor layer 108b), silicidation is performed with good reproducibility and a silicide film with excellent heat resistance is formed. You. In this embodiment, the titanium film 208 is deposited after the source / drain formation ion implantation and silicidation is performed. Instead, the source / drain formation ion implantation is performed after the titanium film 208 is deposited. You may go. In this case, since there is no natural oxide film at the interface between the titanium film 208 and the silicon film (the gate electrode 105 and the L-shaped semiconductor layer 108b), oxygen knock-on does not occur and silicide excellent in film quality can be obtained. become. In this case, ion implantation for source / drain formation must be performed after silicidation, and at a relatively low temperature that does not thermally degrade the silicide film,
This activates the implanted impurity ions.

Next, as shown in FIG. 2E, a heat treatment is performed to form a titanium silicide film 209. In this embodiment, the titanium silicide film 209 is formed by a two-step rapid heating method (RTA). The first stage heat treatment is performed in a nitrogen atmosphere at a temperature of about 650 to 700 ° C. for a low temperature of about 10 to 30 seconds.
The silicon of the V-shaped semiconductor layer 108b reacts with titanium to form a metastable titanium silicide film TiSi ₂ C49 crystal. Thereafter, the unreacted titanium metal and the titanium nitride film formed on the titanium metal surface by the first-stage RTA treatment are selectively removed with a mixed solution of sulfuric acid and hydrogen peroxide. Next, the second heat treatment is performed at 850 to 1000 ° C. for about 10 to 30 seconds in a nitrogen atmosphere, and stable T
An iSi ₂ C54 crystal is formed. Thereafter, the MOSFET is manufactured according to a known manufacturing process.

In this embodiment, after impurity ions for forming the source / drain are implanted into the L-shaped semiconductor layer via the silicon nitride film, the silicon nitride film is removed and the refractory metal is silicided. Therefore, the knocked-on nitrogen contributes to the improvement of the heat resistance of the silicide film, and the problem of the diffusion layer leakage is improved. In particular, the following advantageous effects can be obtained by performing the implantation of impurity ions using the oblique ion implantation technique.

FIG. 7A schematically shows a distribution region (shaded area) of nitrogen knocked on the surface of the L-shaped semiconductor layer 108b. According to the oblique ion implantation, nitrogen is also knocked on the side surface of the protruding portion of the L-shaped semiconductor layer 108b. As a result, as shown in FIG. 7B, a high-quality silicide layer is also formed on the side surface of the protrusion of the L-shaped semiconductor layer 108b. If oblique ion implantation is not performed, nitrogen is not sufficiently knocked on the side surface of the protruding portion of the L-shaped semiconductor layer 108b, so that a high-quality silicide layer is not formed in that portion. In such a case, L
Titanium is dissociated from the poor-quality titanium silicide layer formed on the side surface of the protruding portion of the V-shaped semiconductor layer 108b, and the dissociated titanium diffuses to the surface of the semiconductor substrate, which may change transistor characteristics. Therefore, it is preferable to implant impurity ions obliquely from the viewpoint of forming a good quality silicide layer near the channel region.

Note that a silicide film can be formed at the bottom of the contact for connecting the source / drain region and the wiring, thereby reducing the contact resistance.

Further, by forming an insulating sidewall spacer film 106 between the L-shaped semiconductor layer 108 b and the gate electrode 105, the source / drain region 110 is formed.
And the gate electrode 105 are not short-circuited.

In this embodiment, the gate upper insulating film is formed from a silicon oxide film and the sidewall spacer film is formed from a silicon nitride film.
The upper gate insulating film may be formed from a silicon nitride film, and the sidewall spacer film may be formed from a silicon oxide film.

In the present embodiment, the semiconductor device of the present invention has been described using a salicide transistor as an example. However, it is not always necessary to silicide the gate electrode 105. Even if silicidation is performed only on the L-shaped semiconductor layer 108b, the effect of the present invention can be sufficiently obtained.

It is not necessary to silicide the entire L-shaped semiconductor layer 108b. Even if only the upper part of the L-shaped semiconductor layer 108b is silicided, a sufficiently low contact resistance can be obtained and a low diffusion layer resistance can be realized. If the entirety of the L-shaped semiconductor layer 108b is silicided, the L-shaped semiconductor layer 108b should rather be called an L-shaped conductor layer (or an L-shaped silicide layer).

(Embodiment 3) FIG. 3 shows a CMOS (complementary MO) formed by using the MOSFET described in Embodiment 2.
1 shows a cross section of an S) type semiconductor device.

In this embodiment, an N well and a P well are formed in a silicon substrate 301. A P-channel MOSFET is formed in the N-well, and an N-channel MOSFET is formed in the P-well. Each of the P-channel MOSFET and the N-channel MOSFET includes a source / drain region 306, an oxide film and an ONO.
The substrate 30 via the gate insulating film 303 formed from the film
1 and an L-shaped conductor layer 305. L-shaped conductor layer 30 of the present embodiment
5 is formed from a titanium silicide film. The L-shaped conductor layer 305 of the P-channel MOSFET and the L-shaped conductor layer 305 of the N-channel MOSFET are formed on the field oxide film 302 from the same layer as the L-shaped conductor layer 305. Connected by the local wiring 307.

These MOSFETs and local wiring 307
An interlayer insulating film 308 is deposited so as to cover the contact hole 309, and a contact hole 309 is provided in the interlayer insulating film 308. An upper wiring 310 made of, for example, a metal is formed on the interlayer insulating film 308, and the upper wiring 310 is connected to the L-shaped conductor layer 305 and the local wiring 307 via a contact hole 309.

As described above, in the semiconductor device of this embodiment, P
The L-shaped conductor layer 305 of the channel MOSFET and the L-shaped conductor layer 305 of the N-channel MOSFET are not interconnected by specially formed metal wiring, but instead are L-shaped conductive layers. They are interconnected by local wiring integrally formed from the same silicide layer as the body layer 305. Also, as is apparent from FIG. 3, in this embodiment, the source / drain region 306 and the upper wiring 31 are formed.
The contact region connecting 0 is provided not on the active region but on the wide field oxide film 302.
For this reason, it is not necessary to widen the active region in order to maintain and secure the area of the contact region, and the area of the source / drain impurity diffusion layer in the active region can be reduced, and the junction capacitance can be reduced. As a result, a large number of MOSFs can be maintained while maintaining and maintaining a highly reliable contact.
ET can be more efficiently integrated.

As is clear from the above description, in each of the above embodiments, a silicon film is deposited after forming a gate electrode,
Since the silicon film on the gate electrode is polished and removed by the MP method to form a stacked source / drain structure, unlike the conventional example, a large-scale and expensive selective silicon epitaxial growth apparatus is not required, and the cost is reduced. It does not take. In addition, as shown in FIG. 5, the problem of facet generation due to selective epitaxial growth in the vicinity of the gate electrode can be fundamentally solved. For this reason, the source / drain diffusion layers formed by ion implantation do not become deep in the vicinity of the channel region and are less susceptible to the short channel effect, so that a transistor having a short gate length can be easily formed.

In the chemical mechanical polishing technique, since the polishing rate of the silicon film on the gate electrode is not largely changed between the dense pattern and the isolated pattern, the source and the drain are short-circuited in the portion where the silicon film on the gate remains. Since there is no problem such as inconvenience, the yield is improved.

In the step of forming the source / drain regions, the position of the junction with the silicon substrate extends to just below the interface between the side wall spacer film and the gate electrode, and the source not offset from the gate electrode /
A drain diffusion layer can be formed. Further, since the shallow junction is formed, the drive current is improved while suppressing the short channel effect.

In the silicidation process, since the silicidation is performed after the gate upper insulating film is removed, the side wall spacer film prevents short-circuit between the gate electrode and the source region and between the gate electrode and the drain region, and builds up the diffusion. Silicide can be applied to the layer structure.
Further, since an impurity of the opposite conductivity type to that of the upper silicon substrate is implanted into the silicon film through the silicon nitride film, oxygen atoms are not knocked on in the silicon film, and are further knocked on in the silicon film. The crystal defects in the silicon film are recovered during the heat treatment by the action of nitrogen atoms. Thereafter, since silicidation is performed, a salicide transistor having high heat resistance and little leakage of the diffusion layer is formed.

[0085]

According to the present invention, a pair of L-shaped conductor layers serving as source and drain regions, which are stacked above a channel portion of a transistor, are provided on both sides of a gate electrode with insulating sidewall spacer films. Is formed through. If the ion implantation into the L-shaped conductor layer is performed by an oblique ion implantation technique, a very shallow junction can be formed with good controllability. For this reason, it is possible to avoid the facet problem associated with the selective epitaxial growth, and to form the source / drain region with a very shallow PN junction. By providing such a shallow junction, a drain-induced barrier lower (DIBL) caused by a two-dimensional effect at a channel-side edge portion of the source / drain region.
ing) and reduce the short channel effect.

According to the present invention, after depositing a conductor film, the conductor film is polished by chemical mechanical polishing until the gate upper insulating film is exposed, so that the source film can be formed without using the selective epitaxial growth method. / Drain region can be separated. Therefore, manufacturing costs can be reduced. In addition, since high-temperature treatment such as selective epitaxial growth is not required, it is easy to control the concentration profile of impurities (for example, impurities for controlling threshold voltage). Furthermore, the occurrence of crystal defects near the gate electrode and near the field oxide film due to the thermal stress caused by the high-temperature treatment is reduced, and the leak current is improved.

[Brief description of the drawings]

FIGS. 1A to 1G are process cross-sectional views illustrating an embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIGS. 2A to 2E are process cross-sectional views for explaining another embodiment of the method of manufacturing a semiconductor device according to the present invention.

FIG. 3 is a sectional view showing an embodiment of a semiconductor device according to the present invention.

FIG. 4 is a perspective view of a polishing cloth used in the polishing step of the present invention.

5 (a) and 5 (b) are cross-sectional views showing steps of a method for manufacturing a conventional stacked diffusion layer type MOSFET.

FIG. 6 is a sectional view showing the shape of an L-shaped semiconductor layer.

FIG. 7A is a cross-sectional view showing a distribution of nitrogen knocked on by oblique ion implantation, and FIG. 7B is a cross-sectional view showing a formed silicide layer.

[Explanation of symbols]

 101, 301 Semiconductor substrate 102, 302 Field oxide film 103, 303 Gate oxide film 104 Silicon oxide film 105, 304 Gate electrode 106 Silicon nitride film 107, 107a, 107b, 107c Active region 108a Polycrystalline silicon film 108b L-shaped semiconductor layer (L-shaped conductive layer) 109 silicon nitride film 110 source / drain region 209, 305 titanium silicide film 306 source / drain region 307 local wiring 308 interlayer insulating film 309 contact hole 310 upper wiring

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/336 H01L 29/78 H01L 21/28

Claims (8)

(57) [Claims] An active region and an element isolation region are provided on a main surface.
A gate insulating film is formed on the active region on the formed semiconductor layer.
Forming a step of forming, a step of forming a gate electrode on the gate insulating film, a gate upper insulating film on the gate electrode
And an insulating sidewall spacer on a side wall of the gate electrode.
Forming a film, the gate upper insulating film and the sidewall spacer film
Depositing a conductive thin film or a semiconductor film so as to cover
And the conductive thin film or semiconductor by a chemical mechanical polishing method.
Selectively remove a part of the film to expose the gate upper insulating film.
To form an L-shaped conductor layer from the conductor thin film.
Or forming an L-shaped semiconductor layer from the semiconductor film.
Polishing step, which is performed using a solution to which abrasive grains are added, and
Grooves with a width of 2 to 5 mm are arranged at a pitch of 15 to 40 mm.
Has a two-layer structure of hard pads and soft pads arranged
A method for manufacturing a semiconductor device using a polishing cloth . 2. An active region and an element isolation region are provided on a main surface.
A gate insulating film is formed on the active region on the formed semiconductor layer.
Forming a step of forming, a step of forming a gate electrode on the gate insulating film, a gate upper insulating film on the gate electrode
And an insulating sidewall spacer on a side wall of the gate electrode.
Forming a film, the gate upper insulating film and the sidewall spacer film
Depositing a conductive thin film or a semiconductor film so as to cover
And a chemical mechanical polishing method using a solution containing abrasive grains.
Selectively removing a part of the conductor thin film or the semiconductor film,
Exposing the gate upper insulating film, thereby forming the conductor
Forming an L-shaped conductor layer from a thin film or forming the semiconductor film
A polishing step of forming an L-shaped semiconductor layer from the L-shaped conductor layer or the second conductive type impurity ions;
An ion implantation step of implanting into the L-shaped semiconductor layer; and an impurity in the L-shaped conductor layer or the L-shaped semiconductor layer.
A heat treatment for activating and forming a source region and a drain region
The ion implantation step is performed obliquely with respect to the main surface of the semiconductor layer.
Manufacturing a semiconductor device, which is a step of injecting the impurity from the direction
How . 3. The heat treatment step includes the step of forming the L-shaped conductor layer.
Alternatively, the impurity is removed from the L-shaped semiconductor layer by the semiconductor.
Diffused into the layer, whereby said source region and drain
A shallow junction that functions as part of the semiconductor region is formed in the semiconductor layer.
3. The manufacturing of the semiconductor device according to claim 2, further comprising the step of:
Construction method. 4. The method according to claim 1, wherein the ion implantation step includes the step of:
Is implanted with acceleration energy that does not reach the semiconductor layer.
A method for manufacturing a semiconductor device according to claim 2 . 5. The method according to claim 1, wherein the ion implantation step includes the step of:
The impurity at an angle in the range of 30 to 90 degrees with respect to the main surface
The material ions to the L-shaped conductor layer or the L-shaped semiconductor
5. The semiconductor according to claim 2, wherein the semiconductor is implanted in a layer.
Device manufacturing method . 6. After removing the upper gate insulating film,
The L-shaped conductor layer or silicon is formed on the L-shaped semiconductor layer.
Depositing a silicon nitride film , wherein the ion implantation step includes the step of:
Impurity ions into the L-shaped conductor layer or the L-shaped semiconductor
6. The semiconductor device according to claim 2, wherein the semiconductor device is implanted into a layer.
Manufacturing method . 7. The L-shaped conductor layer or the L-shaped half.
Forming a conductor layer from a silicon layer and further removing the silicon nitride film ; and forming a high melting point metal on the L-shaped conductor layer or the L-shaped semiconductor layer.
Depositing a metal film, and the silicon layer of the L-shaped conductive layer or the L-shaped semiconductor layer
And the high melting point metal film to react with each other to form a high melting point metal silicide.
7. The method for manufacturing a semiconductor device according to claim 6 , further comprising a silicidation step of forming a layer.
Law. 8. The silicidation step includes a step of depositing a titanium film as the high melting point metal film, and a step of performing a first heat treatment so that the titanium film is combined with the silicon layer.
Reacting a first titanium silicide having a first crystal structure
The gate electrode and the L-shaped conductor layer or
Forming an unreacted portion of the titanium film that has not been silicided on the L-shaped semiconductor layer;
Removing the first titanium silicide film by a removing step and a second heat treatment.
Having a second crystal structure that is more stable than the first crystal structure.
8. The method of manufacturing a semiconductor device according to claim 7 , further comprising the step of changing to a second titanium silicide film .