JP4417808B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to an element structure that requires miniaturization.

  In MOSFET, a technology that can simultaneously solve the problem of forming a shallow source / drain diffusion layer and the problem of diffusion layer junction leakage current due to the silicide film formed on the diffusion layer in order to realize a fine and high-speed device. Is required. As an effective technique that satisfies this requirement, there is an elevated source / drain technique in which silicon is epitaxially grown on the source / drain diffusion layer and the surface of the source / drain diffusion layer is pushed closer than the surface of the original silicon substrate.

  A manufacturing process of a MOSFET having an elevated source / drain diffusion layer formed by this elevated source / drain technology and a silicide film will be described below.

  First, as shown in FIG. 26A, an element isolation region 11 made of a silicon oxide film is formed in the silicon substrate 10 using an STI (Shallow Trench Isolation) technique or the like. On the silicon substrate 10 in which the element isolation region 11 is not formed, a gate oxide film 12 having a thickness of, for example, 3 nm is formed using an oxidation technique.

  Next, using a CVD (Chemical Vapor Deposition) technique, a polysilicon 13 having a thickness of, for example, 150 nm is formed on the gate oxide film 12 as a dummy gate to be removed in the future. A silicon nitride film 14 having a thickness of, for example, 50 nm is formed. Thereafter, a patterned resist (not shown) is formed on the silicon nitride film 14 using a lithography technique, and the polysilicon 13 and the silicon nitride film 14 are selectively removed using an RIE (reactive ion etching) technique. Thus, a dummy gate having a laminated structure is formed. Here, the polysilicon 13 may be implanted with N-type impurities such as phosphorus (P) and arsenic (As), or P-type impurities such as boron (B).

  Next, an extension diffusion layer region 15 is formed on the surface of the silicon substrate 10 by ion implantation.

  Next, a silicon oxide film is formed on the entire surface by the CVD technique. Thereafter, as shown in FIG. 26B, the silicon oxide film is etched by the RIE technique, the surface of the silicon substrate 10 is exposed, and the side walls 16 of the silicon oxide film are formed on the side surfaces of the polysilicon 13.

  As shown in FIG. 26C, the silicon is selectively epitaxially grown only in the region where the silicon substrate 10 is exposed, and the elevated source / drain diffusion layer 17 is formed. At this time, since the side surface of the polysilicon 13 is formed of the silicon oxide film 16, the crystal growth grows by generating facets on the side surface of the polysilicon.

  As shown in FIG. 27A, the source / drain diffusion layer 18 is formed by solid-phase diffusion of impurities in the elevated source / drain diffusion layer 17.

  As shown in FIG. 27 (b), after a metal film such as cobalt or titanium is formed on the entire surface, the surface of the elevated source / drain diffusion layer 17 using the dummy gate as a mask by using a salicide process technique. A silicide film 19 such as cobalt or titanium is formed. Thereafter, the unreacted metal film is removed by wet etching or the like.

  Next, an interlayer insulating film 20 such as a silicon oxide film is formed on the entire surface by CVD. As shown in FIG. 27C, the interlayer insulating film 20 is planarized by the CMP technique, and the surfaces of the silicon nitride film 14 and the silicon oxide film side wall 16 above the dummy gate are exposed.

  As shown in FIG. 28A, the silicon nitride film 14 above the dummy gate is selectively removed from the interlayer insulating film 20 using, for example, phosphoric acid. At this time, the side wall 16 of the silicon oxide film is also etched to the height of the surface of the polysilicon 13. Thereafter, the polysilicon 13 is selectively removed from the interlayer insulating film 20 and the side wall 16 of the silicon oxide film using, for example, a CDE (Chemical Dry Etching) technique. Next, the dummy silicon oxide film 12 is removed by wet treatment with hydrofluoric acid or the like, and all the gate electrode formation portions are opened.

  As shown in FIG. 28B, a gate insulating film 21 is formed by depositing a high dielectric insulating film by oxidation of the silicon substrate 10 or a CVD method. Thereafter, for example, a titanium nitride film 22 is formed as a barrier film (reaction prevention film) which is a conductor on the entire surface, and tungsten 23 is formed as a metal film on the titanium nitride film 22.

  As shown in FIG. 28C, the titanium nitride film 22 and the tungsten 23 are planarized by using the CMP technique, and the gate electrode 24 having a laminated structure is formed.

  However, the above-described conventional method for manufacturing a semiconductor device has the following problems.

  As a first problem, in the conventional method, the RIE technique is used when the silicon oxide film is etched to expose the surface of the silicon substrate 10 and to form the side walls 16 of the silicon oxide film.

  Therefore, as shown in FIG. 29, carbon (C), hydrogen (H), oxygen (O), fluorine (F) or the like as a component of the etching gas is present on the exposed silicon substrate 10 surface. The contamination layer 25 is formed to a depth of about 5 to 30 nm.

  In addition, the silicon oxide film formed on the entire surface is selectively subjected to RIE on the silicon substrate 10. However, since the selection ratio is not infinite, the exposed surface of the silicon substrate 10 is etched back.

  Further, the element isolation region 11 is formed of a silicon oxide film. For this reason, the element isolation region 11 is also etched and receded by RIE, and as a result, the side surface of the silicon substrate 10 in the element region is exposed.

  Therefore, as shown in FIG. 30, the contamination layer 25 generated by RIE inhibits the epitaxial growth of silicon, and the low-faceted, elevated, source / drain diffusion layer 26 is formed without the epitaxial growth locally progressing. In addition, crystal defects are formed in the epitaxial layer by the contaminated layer 25, which causes problems that the facet angle varies and the deposited film thickness varies.

  Further, in addition to the above-described problem such as suppression of impurity diffusion due to the contamination layer 25, the surface of the silicon substrate 10 is etched by RIE. Further, the etching amount varies within the wafer surface or between gate patterns. Therefore, when the source / drain diffusion layer 18 is formed, the depth of the source / drain diffusion layer 18 varies. The variation in the depth of the source / drain diffusion layer 18 increases the influence on the variation in the threshold value of the MOSFET as the gate length is reduced. Accordingly, there is a problem that a stable circuit operation becomes impossible along with the miniaturization of the MOSFET, and the yield is greatly reduced.

  Next, as a second problem, in the conventional method, as shown in FIG. 26A, after the extension diffusion layer 15 is formed by ion implantation, the elevated source / drain diffusion layer 17 (FIG. 26) is formed by epitaxial growth. 26 (c)).

  For this reason, when N-type and P-type transistors are formed on the same silicon substrate, since the impurities in the source / drain diffusion layers are different, epitaxial growth on the N-type and P-type diffusion layers has the same film thickness. It is difficult to control. In addition, there is a problem that the region of the extension diffusion layer 15 is expanded by the heat treatment by epitaxial growth.

  Furthermore, as a third problem, in the conventional method, as shown in FIG. 28B, when the gate insulating film 21 is formed, the silicide film 19 is formed on the surface of the elevated source / drain diffusion layer 17. Has been.

  For this reason, when the metal in the silicide film 19 is mixed into the gate insulating film 21, the reliability of the gate insulating film 21 is deteriorated. In addition, it is extremely difficult to avoid this problem.

  Further, with this type of damascene gate formation technology, it is possible to introduce impurities by ion implantation only into the channel region when the dummy gate is removed. However, according to the conventional manufacturing method, in the thermal process of activation after ion implantation, there is a problem that the resistance of the source / drain diffusion layer rapidly increases due to agglomeration of the silicide film 19, which is combined with the above problem. Further, it becomes difficult to manufacture.

The prior art document information related to the invention of this application includes the following.
JP-A-9-172173

The present invention prevents contamination by RIE processing of the semiconductor substrate surface, it can be controlled in the thickness of elevated source and drain diffusion layers, manufacturing of a semiconductor device capable of and improve the reliability of the gate insulating film Provide a method.

  The present invention uses the following means in order to solve the above problems.

Production method of the present onset bright semi conductor arrangement includes the steps of forming a step of selectively forming a dummy gate on a semiconductor substrate, a first insulating film sidewall of the silicon nitride film on the side surfaces of the dummy gate, wherein Forming a first epitaxial layer in contact with the side wall of the first insulating film on the semiconductor substrate on which no dummy gate is formed; and implanting impurities into the first epitaxial layer to form an extension diffusion layer. A step of forming a second insulating film of a silicon oxide film on the entire surface, a step of forming a third insulating film of a silicon nitride film on the second insulating film , and the second and third steps By etching the insulating film , the second insulating film is left on a side surface of the first insulating film side wall and a part of the extension diffusion layer to form a second insulating film side wall, and the third insulating film is formed. Said Of a step of the side surface residue and the third insulating film sidewall insulating film sidewall, forming a second epitaxial layer in contact with the second insulating film sidewall on the extension diffusion layer, the second Implanting impurities into the epitaxial layer to form a source / drain diffusion layer, forming the source / drain diffusion layer, and then forming a first interlayer insulating film on the entire surface, and the first interlayer insulation Planarizing the film and exposing the surface of the dummy gate; removing the dummy gate to form a first groove; forming a gate insulating film on a bottom surface of the first groove; forming a gate electrode on the gate insulating film, said first insulating film to remove the side wall and the third insulating film sidewall, and forming the second and third groove, the second and After forming the third groove, the entire surface And forming a second interlayer insulating film.

According to the present invention, a semiconductor device capable of preventing contamination due to RIE processing on the surface of a semiconductor substrate, controlling the thickness of an elevated source / drain diffusion layer, and improving the reliability of a gate insulating film. A manufacturing method is provided.

  Embodiments of the present invention will be described below with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings.

[First embodiment]
As mentioned in the first problem of the prior art, it has been found that the underlying silicon substrate surface for selective epitaxial growth of silicon is not an ideal surface due to crystal damage or gas impurity contamination due to RIE. Yes.

  Up to now, in order to form a faceted, elevated, source / drain diffusion layer structure, it has been necessary to form an insulating film on the gate side wall with a silicon oxide film so that facet is generated when silicon is epitaxially grown. Therefore, it has been necessary to etch the silicon oxide film by RIE to form sidewalls.

  Therefore, according to the first embodiment of the present invention, the side wall of the silicon oxide film can be formed without using the RIE technique.

  In the following, two embodiments will be described as methods for solving the first problem.

[First Example (1)]
As shown in FIG. 1A, an element isolation region 101 made of an oxide film is formed in a silicon substrate 100 using an STI technique or the like. For example, the element isolation region 101 is formed by laminating a silicon nitride film (not shown) as an etching mask material on the silicon substrate 100 with a buffer oxide film (not shown) interposed therebetween. Next, a transfer resist (not shown) is patterned, and an element region pattern is formed on the silicon nitride film by RIE. Using this patterned silicon nitride film as a mask, the silicon substrate 101 corresponding to the element isolation region 101 is etched. Thereafter, the resist is removed. Next, an insulating film such as a silicon oxide film is deposited on the entire surface of the substrate 100 including the element isolation region 101, and planarized to the upper surface of the silicon nitride film as a stopper by CMP (Chemical Mechanical Polish) or the like. Is done. Thereafter, the silicon nitride film and the buffer oxide film are removed, and an element region and an element isolation region 101 are formed.

Next, a silicon nitride film 102 is formed as a gate insulating film on the silicon substrate 100 by using a CVD method or the like. Here, the thickness of the silicon nitride film 102 is preferably 10 nm or less, and preferably about 3 to 6 nm. In CVD, for example, NH ₃ / SiH ₂ Cl ₂ -based, NH ₃ / SiCl ₄ -based, or NH ₃ / Si ₂ Cl ₆ -based gas is used. At this time, the temperatures at the time of forming the silicon nitride film 102 are 780 ° C., 700 ° C., and 450 to 700 ° C., respectively, depending on the gas system used. Here, in order to prevent the nitride layer from being formed at the interface between the element isolation region 101 and the silicon substrate 100, it is necessary to suppress the penetration of ammonia into the interface between the underlying element isolation region 101 and the silicon substrate 100. Therefore, it is desirable to lower the temperature when forming the silicon nitride film 102. In addition, the base of the silicon nitride film 102 may be a natural oxide film or a silicon oxide film formed of chemicals as long as it is 3 nm or less.

  Next, polysilicon or amorphous silicon 103 having a thickness of, for example, 100 to 150 nm is formed on the silicon nitride film 102 by doping an impurity that becomes N-type or P-type such as phosphorus, arsenic, or boron. . Thereafter, a silicon oxide film 104 having a thickness of, for example, 50 nm is formed on the polysilicon 103 by CVD or the like.

  Next, a patterned resist (not shown) is formed on the silicon oxide film 104 by lithography. Thereafter, using this resist as a mask, the polysilicon 103 and the silicon oxide film 104 are etched by the RIE technique. At this time, RIE is performed at a selection ratio such that the silicon nitride film 102 remains on the entire surface of the silicon substrate 100. Thus, a gate electrode having a laminated structure of the silicon nitride film 102, the polysilicon 103, and the silicon oxide film 104 is formed.

  Thereafter, as shown in FIG. 1B, oxidation is performed, and a side wall 105 of the silicon oxide film is formed only on the side surface of the polysilicon 103. At this time, since the surface of the silicon substrate 100 is covered with the silicon nitride film 102, the silicon oxide film is not formed.

  As shown in FIG. 2A, the silicon nitride film 102 other than the lower portion of the gate electrode is removed on the silicon substrate 100 by performing etching using a heated chemical solution such as phosphoric acid. At this time, the heating temperature of the phosphoric acid treatment is in the range of room temperature to 180 ° C. and is preferably used at about 160 ° C. so that the underlying silicon substrate 100 and the oxide film forming the element isolation region 101 are not etched. By controlling the temperature to remove the silicon nitride film 102, the etching selectivity between the silicon nitride film 102 and the silicon substrate 100 or between the silicon nitride film 102 and the silicon oxide film 104 can be increased to 10 or more. Is possible.

As shown in FIG. 2B, a silicon or silicon-germanium film having an N-type or P-type impurity content of 10 ¹⁹ cm ⁻³ or less is selectively epitaxially grown to form an epitaxial silicon layer. Thereafter, N-type or P-type impurities are introduced by a method such as ion implantation so that the average impurity concentration in the epitaxial silicon layer is 10 ¹⁹ cm ⁻³ or more. Here, the epitaxial layer may be doped with impurities by increasing the temperature to 900 to 1100 ° C. at a high temperature increase of 150 ° C./sec or more and performing a heat treatment for 60 seconds or less. When the temperature of this heat treatment is lower than 900 ° C., the tail of the ion-implanted impurity distribution (portion closest to the substrate) is not steep, and 10 ¹⁹ cm ⁻ to a depth of about 50 nm for the depth of the impurity distribution. It becomes difficult to control the depth of the pn junction formed inside the silicon substrate 100 to 50 nm or less while maintaining ³ or more.

  As described above, the silicon of the silicon substrate 100 is selectively epitaxially grown, and a silicon crystal is selectively grown only on the silicon substrate 100 in a region where the source / drain is formed, and an elevated source / drain diffusion layer is formed. The The elevated source / drain diffusion layer is a faceted elevated source / drain diffusion layer 106 in which the height of the elevated source / drain diffusion layer increases as the distance from the lower end of the gate electrode increases.

  Thereafter, the extension diffusion layer region 107 is formed by solid-phase diffusion of impurities in the faceted, elevated, source / drain diffusion layer 106 by heat treatment.

  In addition, this invention is not limited to the said Example. For example, a thin silicon oxide film may be formed at the interface between the silicon nitride film 102 and the silicon substrate 100 by a thermal process at the time of forming the silicon nitride film 102, atmospheric oxygen, or chemical treatment. In such a case, when the surface of the silicon substrate 100 is exposed, after removing the silicon nitride film 102 by phosphoric acid treatment, the silicon oxide film may be removed by hydrofluoric acid treatment. However, the silicon oxide film 105 and the element isolation region 101 are simultaneously etched by this hydrofluoric acid treatment. Therefore, in order to prevent these, it is desirable that the silicon oxide film has a thickness of about 3 nm or less.

  The silicon nitride film 102 may be a metal oxide film such as a titanium oxide film. For example, since a titanium oxide film is insoluble in hydrofluoric acid and soluble in hot sulfuric acid, the same effect as a silicon nitride film can be obtained.

  As described above, according to the first embodiment (1), the insulating film such as the silicon nitride film formed on the substrate is removed not by RIE but by phosphoric acid chemical treatment. Therefore, it is possible to form a structure in which the surface of the silicon substrate on which selective epitaxial growth for source / drain is performed can be exposed without damaging and the side wall of the gate is covered with the silicon oxide film 105. In addition, since phosphoric acid is used, the element isolation region 101 is not etched unlike the prior art, so that there is almost no problem such as receding of the element isolation region 101. Therefore, even when the side wall of the gate is a silicon oxide film, the height of the elevated source / drain diffusion layer 106 increases as the distance from the lower end of the gate electrode increases. Can be formed.

[First Example (2)]
In actual mass production, it is necessary to reduce the resistance of the gate electrode and the source / drain diffusion layer, increase the dielectric constant of the gate insulating film, and make the N-type MOSFET and the P-type MOSFET separately in the same wafer.

  Therefore, in the first embodiment (2), a method of manufacturing a MOSFET in which the gate is a metal electrode, the gate insulating film is a high dielectric film, and silicide is formed on the source / drain diffusion layers will be described below.

  As shown in FIG. 3A, an element isolation region 111 made of an oxide film is formed in the silicon substrate 110 using the STI technique or the like.

  Next, a thin first silicon nitride film 112 having a thickness of, for example, 6 nm is formed on the silicon substrate 110 by using a CVD method or the like.

  Next, a polysilicon 113 having a thickness of, for example, 150 nm is formed on the first silicon nitride film 112 by a CVD method or the like, and a second silicon nitride film 114 having a thickness of, for example, 50 nm is formed on the polysilicon 113. Here, since the polysilicon 113 is a dummy gate to be removed in the future, it is not necessary to dope impurities.

  Next, a patterned resist (not shown) is formed on the second silicon nitride film 114 by lithography. Thereafter, using this resist as a mask, the polysilicon 113 and the second silicon nitride film 114 are etched by the RIE technique. At this time, RIE is performed at a selection ratio such that the first silicon nitride film 112 remains on the entire surface of the silicon substrate 110. As a result, a gate electrode structure having a laminated structure of the first silicon nitride film 112, the polysilicon 113, and the second silicon nitride film 114 is formed.

  Next, as shown in FIG. 3B, oxidation is performed, and a first silicon oxide film 115 is formed only on the side surface of the polysilicon 113. At this time, since the surface of the silicon substrate 110 is covered with the first silicon nitride film 112, the first silicon oxide film is not formed.

  In the following manufacturing process, an N-type MOSFET and a P-type MOSFET are formed separately. In FIG. 4A, a region A shows an N-type MOSFET and a region B shows a P-type MOSFET.

  As shown in FIG. 4A, a patterned resist 116 is formed only on the region B by lithography. Thereafter, the first silicon nitride film 112 is wet-etched with phosphoric acid using the resist 116 as a mask, and the surface 117 of the silicon substrate in the region A is exposed. At this time, the second silicon nitride film 114 is also etched, but the etching amount is very small because the first silicon nitride film 112 is a thin film, and there is no problem.

  Next, the resist 116 is removed with a mixed solution of sulfuric acid and hydrogen peroxide solution. At this time, a natural oxide film (not shown) is formed on the surface 117 of the silicon substrate in the region A. Thereafter, the natural oxide film is removed by annealing containing high-temperature hydrogen in an epitaxial growth apparatus. At this time, since the silicon substrate 110 in the region B is covered with the first silicon nitride film 112, the oxide film is not etched at all in the process of removing the oxide film by this annealing.

  As shown in FIG. 4B, by performing selective epitaxial growth of silicon containing an impurity that becomes an N-type semiconductor such as phosphorus or arsenic, silicon is selectively crystal-grown only on the silicon substrate 117 in the region A, Further, since the gate side surface is the first silicon oxide film 115, the gate side surface is faceted to grow a crystal, and an N-type facet, elevated, source / drain diffusion layer 118 is formed. The height of the N-type facet, elevated, source / drain diffusion layer 118 is set to be equal to or lower than the height of the dummy gate polysilicon 113. Thereafter, the resist 116 is removed.

  Next, as shown in FIG. 5A, a thin third silicon nitride film 119 having a thickness of, for example, 3 nm is formed on the entire surface.

  Next, similarly to FIG. 4A, a resist (not shown) patterned only on the region A is formed by the lithography technique. Thereafter, the third silicon nitride film 119 and the first silicon nitride film 112 are wet etched with phosphoric acid using the resist as a mask. As a result, as shown in FIG. 5B, the surface 120 of the silicon substrate in the region B is exposed. The second silicon nitride film 114 is also etched at the time of this etching, but the amount of etching is very small because the first silicon nitride film 112 is a thin film, and there is no problem.

  Next, the resist is stripped with a mixed solution of sulfuric acid and hydrogen peroxide solution. At this time, a natural oxide film (not shown) is formed on the surface 120 of the silicon substrate in the region B. Thereafter, the natural oxide film is removed by annealing containing high-temperature hydrogen in an epitaxial growth apparatus. At this time, since the region A is covered with the third silicon nitride film 119, the oxide film is not etched at all in the process of removing the oxide film by this annealing.

  As shown in FIG. 6 (a), by performing selective epitaxial growth of silicon containing an impurity that becomes a P-type semiconductor such as boron, only the surface 120 of the silicon substrate in the region B has a P-type faceted elevated source. A drain diffusion layer 121 is formed. At this time, since the region A is covered with the third silicon nitride film 119, selective epitaxial growth does not occur. Also, the height of the P-type facet, elevated, source / drain diffusion layer 121 is set to be equal to or lower than the height of the polysilicon 113 of the dummy gate, like the N-type facet, elevated, source / drain diffusion layer 118. To.

  Next, the third silicon nitride film 119 is removed. At this time, the second silicon nitride film 114 is also etched, but there is no problem because the etching amount is very small.

  As shown in FIG. 6B, a second silicon oxide film 122 having a thickness of, for example, 40 nm is formed on the entire surface by CVD.

  Next, by performing heat treatment, solid phase diffusion of impurities contained in each of the N-type facet / elevated source / drain diffusion layer 118 and the P-type facet / elevated source / drain diffusion layer 121 The extension diffusion layer 123 is formed on the silicon substrate 110. Here, when the difference in the amount of solid phase diffusion between the N-type and P-type impurities is too large to perform simultaneous heat treatment, first, for example, in the process shown in FIG. Solid phase diffusion of only N-type impurities is performed at a certain high temperature. Thereafter, P-type impurities such as boron having a high diffusion rate may be diffused in this step.

  As shown in FIG. 7A, the second silicon oxide film 122 is etched back using RIE technology, and an N-type faceted elevated source / drain diffusion layer 118 that forms silicide, which will be described later, and The upper surface of the P-type faceted elevated source / drain diffusion layer 121 is exposed. At this time, the second silicon oxide film 122 remains on the side walls of the gate and the side walls of the facet, elevated, source and drain diffusion layers 118 and 121.

  Next, a metal film such as titanium or cobalt is deposited on the entire surface. Thereafter, as shown in FIG. 7B, a silicide layer 124 is selectively formed only on the upper surfaces of the facet, elevated, source and drain diffusion layers 118 and 121 by the salicide process technique.

  Next, an interlayer insulating film 125 made of an oxide film is deposited on the entire surface by CVD. Thereafter, as shown in FIG. 8A, the interlayer insulating film 125 is planarized using, for example, a CMP method, and the surface of the second silicon nitride film 114 on the dummy gate is exposed. At this time, since the facet, elevated, source, drain diffusion layers 118, 121 are formed below the height of the dummy gate polysilicon 113, the upper surfaces of the facet, elevated, source, drain diffusion layers 118, 121 are formed. Silicide 124 is not exposed.

  As shown in FIG. 8B, the second silicon nitride film 114 is selectively removed from the interlayer insulating film 125 by a wet etching technique using phosphoric acid. Thereafter, the polysilicon 113 is selectively removed from the interlayer insulating film 125, the first silicon oxide film 115, and the first silicon nitride film 112 by wet etching such as CDE or mixed acid. Next, the first silicon nitride film 112 is selectively etched with respect to the interlayer insulating film 125 and the first silicon oxide film 115 by phosphoric acid. Thereby, the dummy gate electrode is removed and the gate electrode forming portion is opened.

  Next, as shown in FIG. 8C, a tantalum oxide film 126 having a thickness of, for example, 10 nm is formed as a high dielectric gate insulating film on the entire surface by CVD or the like. On this tantalum oxide film 126, a titanium nitride film 127 as a barrier film (reaction prevention film) which is a conductor having a thickness of, for example, 10 nm is formed. Thereafter, aluminum 128 is formed as a gate electrode on the titanium nitride film 127, and the opened gate electrode formation portion is buried.

  Thereafter, as shown in FIG. 8C, the aluminum 128, the titanium nitride film 127, and the tantalum oxide film 126 are planarized by using a CMP technique or the like, the surface of the interlayer insulating film 125 is exposed, and the gate electrode is formed. It is formed.

  As described above, it has a source / drain diffusion layer with a facet, elevated, source / drain diffusion layer structure with silicide formed on the top, a gate insulating film is a high dielectric film, and a gate electrode is a metal gate structure. N-type and P-type MOSFETs can be formed.

  In addition, this invention is not limited to the said Example. The surface of the silicon substrate 110 on which the gate insulating film is formed is formed until the first silicon nitride film 112 is removed in the step of FIG. Therefore, by applying a high-temperature heat treatment at least during the step (FIG. 8B) in which this film is removed from the step in which the first silicon nitride film 112 is formed (FIG. 3A), FIG. A silicon thermal nitride film layer is formed on the surface of the silicon substrate exposed by removing the first silicon nitride film 112 in the step 8 (b). Therefore, this thermal nitride film layer as the gate insulating film, or further oxidation is performed, and a silicon dielectric film or a high dielectric film is formed on the silicon thermal nitride film layer or the silicon thermal nitride film. It is also possible to form a stacked gate insulating film.

  The silicon nitride film 112 may be a metal oxide film such as a titanium oxide film. For example, since a titanium oxide film is insoluble in hydrofluoric acid and soluble in hot sulfuric acid, the same effect as a silicon nitride film can be obtained.

  As described above, according to the first embodiment (2), for example, silicon having a selectivity with respect to the silicon oxide film in the wet etching process without forming a thermal oxide film of silicon on the silicon substrate. A nitride film 112 is formed. Therefore, since the silicon nitride film 112 can be removed by wet etching, the surface 120 can be exposed without damaging the surface 120 of the silicon substrate 110. That is, in a process that requires removal of a silicon oxide film in a part of the region by wet etching or the like, the silicon nitride film becomes a barrier film of a silicon oxide film that does not require etching. Further, when the silicon nitride film is removed by wet processing in order to expose the silicon substrate, the silicon oxide film is not etched by performing phosphoric acid processing. Therefore, it can be applied to various processes.

[Second Embodiment]
Next, a second embodiment of the present invention will be described.

  Next, as described in the second problem of the prior art, when an elevated source / drain diffusion layer is formed by epitaxial growth after the extension diffusion layer is formed, impurities in the N-type and P-type diffusion layers are removed. It has been found that it is difficult to equalize the grown film thickness due to differences.

  In order to avoid this problem, in the second embodiment, the extension diffusion layer is formed after the elevated source / drain diffusion layer is formed by epitaxial growth.

  In the following, two embodiments will be shown as methods for solving the second problem.

[Second Embodiment (1)]
As shown in FIG. 9A, an element isolation region (not shown) is formed in the silicon substrate 200 using the STI technique.

  Next, as necessary, the impurity concentration of the channel portion of the transistor is adjusted by implanting impurities into the entire surface of the region where the transistor is to be formed.

  Next, a buffer oxide film (not shown) is formed on the silicon substrate 200, and an amorphous or polycrystalline silicon film (polysilicon) 201 is formed on the buffer oxide film. A silicon nitride film 202 is formed on the polysilicon 201. Thereafter, a patterned resist (not shown) is applied on the silicon nitride film 202, and the silicon nitride film 202 and the polysilicon 201 are selectively removed by anisotropic etching using this resist as a mask. ), A dummy gate is formed. Thereafter, the resist is removed.

  Next, after oxidizing the dummy gate as necessary, a silicon nitride film having a thickness of, for example, 10 nm is formed on the entire surface. Thereafter, as shown in FIG. 9B, the silicon nitride film is etched by anisotropic etching to form a very thin side wall 203 of the first silicon nitride film on the side surface portion of the dummy gate.

  As shown in FIG. 9C, the surface of the silicon substrate 200 in the source / drain formation region is cleaned by dilute hydrofluoric acid treatment and high-temperature hydrogen treatment (eg, 900 ° C., 5 min), and silicon is selectively epitaxially grown, for example, by 30 nm. An epitaxial silicon layer 204 is formed. At this time, since the upper surface of the dummy gate is covered with the silicon nitride film 202, silicon is not epitaxially grown. Further, since the side surface of the dummy gate is covered with the silicon nitride film 203, no facet occurs in the epitaxial silicon layer.

As shown in FIG. 10A, impurity ions are implanted, and an extension diffusion layer 205 extending from the source / drain diffusion layer is formed. The design method of the diffusion layer can be realized within the range of a normal ion implantation technique because the extension in the depth direction has a margin corresponding to the epitaxial silicon layer 204 grown epitaxially. For example, the conditions for forming the n-type diffusion layer are that the impurity is arsenic (As), the acceleration voltage is 20 KeV, and the dose is 1 × 10 ¹⁵ cm ⁻² . Here, the annealing conditions for activating the extension diffusion layer 205 are, for example, a temperature of 800 ° C. and a processing time of, for example, 10 seconds. The impurity is not limited to arsenic but may be phosphorus (P), and when forming a P-type diffusion layer, it can be realized by using boron (B), boron fluoride (BF ₂ ), or the like. Note that the ion implantation conditions for these ion species are different. Further, since the side wall 203 of the first silicon nitride film is formed thin, the extension diffusion layer 205 can be sufficiently formed up to the end portion of the dummy gate.

  Next, if necessary, a silicon oxide film is formed on the entire surface as an etching stopper, and a silicon nitride film having a thickness of, for example, 50 nm is formed on the silicon oxide film.

  As shown in FIG. 10B, the silicon oxide film is etched by anisotropic etching, and a side wall 206 of the silicon oxide film and a side wall 207 of the second silicon nitride film are formed on the side surface portion of the dummy gate.

  As shown in FIG. 10C, source / drain diffusion layers 208 are formed by ion implantation using the sidewall 207 of the second silicon nitride film as a mask. Here, the annealing conditions for activating the source / drain are a temperature of, for example, 1000 ° C. and a processing time of, for example, 10 seconds.

  Next, as shown in FIG. 11A, an interlayer insulating film 209 is formed on the entire surface. Thereafter, the interlayer insulating film 209 is planarized by CMP or the like, and the surface of the silicon nitride film 202 on the upper surface of the dummy gate is exposed. Here, CMP is used for planarization, but etch back may be used.

  As shown in FIG. 11B, the silicon nitride film 202 is removed and the surface of the polysilicon 201 is exposed by the thermal phosphoric acid treatment, and the first and first surfaces are exposed to a position where the surface of the polysilicon 201 is exposed. The side walls of the silicon nitride film 2 are removed.

  As shown in FIG. 11C, the polysilicon 201 of the dummy gate is removed by CDE, and a groove 210 is formed. Thereafter, a silicon oxide film (not shown) formed as a buffer is removed by dilute hydrofluoric acid treatment, and the surface of the silicon substrate 200 is exposed. Here, when the dummy gate is removed, local threshold adjustment can be performed by ion implantation through the buffer oxide film.

  As shown in FIG. 12A, the gate insulating film 211 is formed by oxidizing the exposed surface of the silicon substrate 200 or depositing an insulating film (for example, tantalum oxide). Here, the gate insulating film 211 is not limited to tantalum oxide, and may be an insulating film having a high dielectric constant. Next, a titanium nitride film 212 as a barrier film (reaction prevention film), which is a conductor, is formed on the entire surface, and tungsten (W) 213 is formed as a metal film on the titanium nitride film 212 to fill the groove 210. . Here, the metal film is not limited to tungsten, but may be other metals such as aluminum (Al) or copper (Cu). Further, the reaction preventing film is not limited to the titanium nitride film but may be tungsten nitride or tantalum nitride. In the case where the electrode itself is not metal but is polysilicon containing phosphorus, no reaction preventing film is required.

  Next, the gate electrode 214 is formed in the trench 210 by planarization by CMP or the like. Here, CMP is used for planarization, but etch back may be used. As for the gate portion, the gate electrode may be formed by patterning and etching without performing planarization by CMP.

  Thereafter, a normal transistor formation process may be followed, but as will be described later, a higher-performance transistor can be formed by adding a process of removing the side wall.

  First, as shown in FIG. 12B, the side walls 203 and 204 of the first and second silicon nitride films are removed. Thereafter, an interlayer insulating film 218 such as TEOS is formed on the entire surface.

  Here, when the height of the gate electrode 214 is, for example, 30 nm and the thickness of the sidewall 203 of the first silicon nitride film is, for example, 20 nm (condition 1), as shown in FIG. Almost embedded by the membrane 218. In addition, when the height of the gate electrode 214 is, for example, 100 nm and the thickness of the side wall 203 of the first silicon nitride film is, for example, 10 nm (condition 2), the aspect ratio is 10, and therefore, as shown in FIG. As described above, the trench 217 is not completely filled with the interlayer insulating film 218, and a cavity 219 is formed. Thus, by forming the cavity 219, a low dielectric constant can be realized and the dielectric characteristics can be improved.

  Further, as shown in FIG. 14A, when the side wall 207a of the silicon oxide film is formed on the side wall 206a of the silicon nitride film, the side walls 203 and 206a of the silicon nitride film are removed, and FIG. A groove 217a is formed as shown in FIG. Here, in the case of condition 1, the groove 217a is buried by the interlayer insulating film 218 as shown in FIG. 15A, and in the case of condition 2, the cavity 219a is formed as shown in FIG. 15B. Thus, by forming the cavity 219a, the dielectric constant can be reduced and the dielectric characteristics can be improved.

  In addition, this invention is not limited to the said Example. For example, after the step shown in FIG. 5 and before ion implantation, the extension diffusion layer 205 is selectively epitaxially grown to form epitaxial silicon 215 and 216 as shown in FIGS. 16A and 17A. Also good. Thereafter, as shown in FIGS. 16B and 17B, a source / drain diffusion layer 208 is formed by ion implantation.

  Here, when the silicide layer is formed in the source / drain diffusion layer 208 portion, the silicide reaction is performed by consuming silicon. Therefore, as in the above-described embodiment, there is an aim of raising the source / drain diffusion layer 208 portion in advance. Even when the silicide layer is not formed, since the source / drain diffusion layer 208 has a sufficient depth, impurities can be ion-implanted at a high concentration, which is effective in reducing contact resistance.

  As described above, according to the second embodiment (1), the epitaxial silicon layer is formed before the extension diffusion layer is formed. Therefore, when N-type and P-type transistors are formed on the same substrate, it becomes easy to control the epitaxial growth on the N-type and P-type to the same film thickness. Further, the extension diffusion layer can be prevented from spreading due to the epitaxial growth heat treatment.

[Second Embodiment (2)]
The second embodiment (2) relates to a transistor using a normal polysilicon gate electrode without using a damascene process.

  First, as shown in FIG. 18A, similarly to the second embodiment (1), an element region and an element isolation region (not shown) are formed in the silicon substrate 220. As necessary, impurity ions are implanted into a predetermined region, and the threshold value of the transistor to be formed is adjusted.

  Next, the surface of the silicon substrate 220 is oxidized, a gate oxide film 221 is formed on the element region, and polysilicon 222 is formed on the entire surface. Thereafter, a patterned resist (not shown) is formed on the polysilicon 222.

  Thereafter, as shown in FIG. 18A, using the resist as a mask, the polysilicon 222 is selectively removed by anisotropic etching to form a gate electrode. Here, the gate electrode is not limited to polysilicon (polycrystalline silicon) but may be amorphous silicon. Further, it may be polycrystalline silicon doped with impurities such as phosphorus in advance, or a laminated film in which tungsten is further deposited thereon.

  Next, the gate electrode is oxidized by about 5 nm, for example, and etching damage is removed. Thereafter, a silicon nitride film having a thickness of, for example, 10 nm is formed on the entire surface. Next, as shown in FIG. 18B, the silicon nitride film is etched by anisotropic etching, and side walls 223 of the first silicon nitride film are formed on the side surfaces of the polysilicon 222.

  Next, dilute hydrofluoric acid treatment and hot hydrogen treatment are performed, and the silicon substrate 220 in the source / drain portions is exposed and cleaned at the same time.

  As shown in FIG. 18C, silicon is selectively epitaxially grown, for example, by 30 nm, and an epitaxial silicon layer 224 is formed on the substrate 200. Although silicon may grow on the upper surface of the polysilicon 222, it does not affect the transistor characteristics. Here, since the side wall of the polysilicon 222 is formed of the silicon nitride film 223, no facet occurs in the epitaxial silicon layer 224.

As shown in FIG. 19A, impurity ions are implanted into the epitaxial silicon layer 224 to form an extension diffusion layer 225 extending from the source / drain diffusion layer. The design method of the diffusion layer can be realized within the range of a normal ion implantation technique because the extension in the depth direction has a margin corresponding to the epitaxial silicon layer 224 on which silicon is epitaxially grown. For example, the conditions for forming the N-type diffusion layer are, for example, that the impurity is arsenic (As), the acceleration voltage is 20 KeV, and the dose is 1 × 10 ¹⁵ cm ⁻² . Here, the annealing conditions for activating the extension diffusion layer 225 are performed at a temperature of, for example, 800 ° C. and a processing time of, for example, 10 seconds.

  Next, if necessary, a silicon oxide film as an etching stopper is formed on the entire surface, and a silicon nitride film having a thickness of, for example, 50 nm is formed on the silicon oxide film.

  As shown in FIG. 19B, a side wall portion 226 of the silicon oxide film and a side wall 227 of the second silicon nitride film are formed on the side surface portion of the polysilicon 222 by anisotropic etching.

  As shown in FIG. 19C, a source / drain diffusion layer 228 is formed by ion implantation using the side wall 227 of the second silicon nitride film as a mask. Here, the annealing conditions for activating the source / drain diffusion layer 228 and the gate electrode are a temperature of 1000 ° C. and a processing time of 10 seconds, for example.

  The present invention is not limited to the above embodiment. For example, after the step shown in FIG. 19B and before ion implantation, the extension diffusion layer 225 may be selectively epitaxially grown to further form epitaxial silicon. That is, when a silicide layer is formed in the source / drain diffusion layer 228, the silicide reaction is performed by consuming silicon. For this reason, as described above, there is an aim of preventing the shortage of silicon during the silicidation by raising the source / drain diffusion layer 228 in advance. In addition, the gate electrode formed of polysilicon is implanted with impurities at this point, and can be used as a gate wiring.

  As described above, according to the second embodiment (2), the epitaxial silicon layer is formed before the extension diffusion layer is formed. Therefore, when N-type and P-type transistors are formed on the same substrate, it becomes easy to control the epitaxial growth on the N-type and P-type to the same film thickness. Further, the extension diffusion layer can be prevented from spreading due to the epitaxial growth heat treatment.

[Third embodiment]
Next, a third embodiment of the present invention will be described.

  Next, as described in the third problem of the prior art, when the gate insulating film is formed after the silicide film is formed, the reliability of the gate insulating film is obtained by mixing the metal in the silicide film into the gate insulating film. It has been found that sex degradation occurs.

  In order to avoid this problem, in the third embodiment, the silicide film is formed after the gate insulating film is formed. That is, in the third embodiment, a gate insulating film is formed before forming a silicide film on a source / drain diffusion layer, and a MOSFET having a metal single layer gate structure using a damascene gate forming process is used. A manufacturing method is shown.

  First, as shown in FIG. 20A, an element isolation region 301 is formed in a semiconductor substrate 300, and a gate oxide film 301 having a thickness of, for example, 6 nm is formed on the semiconductor substrate 300 as a dummy gate to be removed in the future. It is formed. A polysilicon 303 having a thickness of, for example, 250 nm is formed on the gate oxide film 301, and a first silicon nitride film 304 having a thickness of, for example, 50 nm is formed on the polysilicon 303. Thereafter, a patterned resist (not shown) is formed. Using this resist as a mask, the polysilicon 303 and the first silicon nitride film 304 are selectively removed, and a dummy gate having a laminated structure is formed. Next, extension diffusion layer regions 305 are formed in the semiconductor substrate 300 by implanting impurity ions. Thereafter, a silicon nitride film is formed on the entire surface, and a sidewall 306 of a second silicon nitride film having a width of, for example, 40 nm is formed on the sidewall of the dummy gate by anisotropic etching.

  As shown in FIG. 20B, the gate oxide film on the substrate is removed by hydrofluoric acid treatment, and the semiconductor substrate 300 is exposed only on the source / drain regions. Silicon is selectively epitaxially grown only in the exposed region of the semiconductor substrate 300 to form an elevated source / drain diffusion layer 307 having a height of about 70 nm from the surface of the semiconductor substrate 300. Here, since the side wall of the dummy gate is formed of the silicon nitride film 306, no facet is generated in the elevated source / drain diffusion layer 307. Thereafter, a source / drain diffusion layer region (not shown) is formed by an ion implantation technique. At this time, the extension diffusion layer region 305 was formed in the step shown in FIG. 20A, but this was not performed, and the extension diffusion layer region 305 was formed by solid phase diffusion of impurities during the formation of the source / drain diffusion layer region in this step. There is no problem even if it is formed.

  As shown in FIG. 20C, an interlayer insulating film 308 is formed on the entire surface, and this interlayer insulating film 308 is planarized by the CMP technique, and the first silicon nitride film 304 and the second silicon on the upper surface of the dummy gate. The surface of the nitride film 304 is exposed. Here, the upper surface of the elevated source / drain diffusion layer 307 is not exposed because it is lower than the upper surface of the dummy gate.

  Next, the first silicon nitride film 304 is removed by phosphoric acid, and the polysilicon 303 is removed by wet etching such as CDE or mixed acid. Further, the dummy gate oxide film 302 is removed by hydrofluoric acid treatment, and a gate formation portion is opened.

  As shown in FIG. 21A, a gate insulating film 309 is formed in the opening of the gate forming portion by oxidation or deposition of a high dielectric insulating film by a CVD method. Here, since the silicide film is not formed on the source / drain, the gate insulating film can be formed without any metal. In addition, when the gate forming portion is opened, even if ion implantation and its activation process are added, there is no problem of a decrease in reliability of the gate insulating film due to metal mixing as in the prior art. Therefore, if the channel region is ion-implanted after opening the gate, there is no high-temperature thermal process such as source / drain diffusion layer formation after this process, so the channel has a very steep impurity depth profile. Structure formation is also possible.

  As shown in FIG. 21B, for example, a titanium nitride film 310 as a barrier film (reaction prevention film) that is a conductor is formed on the entire surface, and a gate electrode material is formed on the titanium nitride film 310 by a CVD method. For example, aluminum 311 is formed as the metal.

  As shown in FIG. 21C, the sidewalls 306 of the aluminum 311, the titanium nitride film 310, the gate insulating film 309, and the second silicon nitride film are planarized by CMP, and the elevated source / drain diffusion is performed. The upper surface of the layer 307 is exposed and the gate electrode 312 is formed.

  As shown in FIG. 22A, oxidation is performed, an aluminum oxide film 313 and a titanium oxide film 314 are formed on the gate electrode 312, and a silicon oxide film 315 is formed on the elevated source / drain diffusion layer 307. Is formed.

  As shown in FIG. 22B, the silicon oxide film 315 on the elevated source / drain diffusion layer 307 is removed by hydrofluoric acid. At this time, the aluminum oxide film 313 and the titanium oxide film 314 are not removed because they are insoluble in hydrofluoric acid.

  As shown in FIG. 22C, a metal film 316 is formed on the entire surface. Here, the metal film 316 is a metal made of any one of noble metals (palladium, nickel, platinum, cobalt) that forms silicide at a temperature lower than the melting point of aluminum, or an alloy containing at least one of them.

  Thereafter, a silicide film 317 having a thickness of, for example, 40 nm is formed on the surface of the elevated source / drain diffusion layer 307 by heat treatment. At this time, since the aluminum oxide film 313 and the titanium oxide film 314 are formed on the surface of the gate electrode 312, the silicide reaction does not occur. Therefore, the silicide reaction selectively occurs only in the elevated source / drain diffusion layer 307 region. In order to prevent leakage current, the silicide film 317 needs to be formed at least 60 nm above the bottom surface of the extension diffusion layer region 305. At this time, the depth of the extension diffusion layer region 305 from the surface of the silicon substrate 300 is set to 50 nm to 60 nm.

  As shown in FIG. 23, the unreacted metal 316 that has not undergone the silicide reaction is removed. At this time, wet etching or the like can be considered as a removal method. However, since the unreacted metal 316 is formed on a flat surface, the unreacted metal 316 can be removed using a planarization process such as CMP.

  As described above, the selective removal of the unreacted metal in the salicide process can be removed by a planarization process such as CMP, instead of the chemical treatment by the wet process as in the prior art. Therefore, there is no problem of remaining metal, disappearance of the gate electrode, dissolution of silicide, etc. due to loss of selectivity in the conventional wet etching method, and various unreacted metals can be easily removed.

  Therefore, since selective etching in the wet process is difficult so far, metals such as palladium that have not been used in products can also be used.

  This palladium silicide has advantages over silicide, such as titanium silicide and cobalt silicide, which are currently mass-produced.

That is, when palladium is silicided, palladium silicide (Pd ₂ Si) is formed. The ratio of the silicon film thickness Dsi consumed during the silicide process to the silicide film thickness Dsilicide film formed is A, that is, A = Dsi / Dsilide. Then, titanium silicide and cobalt silicide currently mass-produced have A≈1, while palladium silicide has A≈0.5.

  That is, noble metals such as palladium consume less silicon when forming silicide than titanium and cobalt consume when forming silicide. Here, in the formation of silicide by thermal reaction, as the amount of silicon consumed increases, the morphology of the interface between silicon and silicide deteriorates as shown in FIG. For this reason, the problem that the leakage current of a diffusion layer increases arises. Therefore, such a leakage current can be prevented by performing planarization such as CMP that can use palladium silicide or the like that consumes less silicon.

  Note that platinum (A≈0.7, PtSi) is a metal that consumes less silicon during silicide, such as palladium.

  Further, the structure according to the third embodiment has the following advantages in the contact hole forming step after the step shown in FIG.

  First, since the upper surface is flat, RIE of the interlayer insulating film is facilitated, and the interlayer insulating film can be formed thin. As a result, since the aspect ratio of the contact hole is reduced, the contact hole can be embedded easily. Further, a planarization step such as CMP and a reflow step of the interlayer insulating film can be omitted.

  As described above, according to the third example, the following results were obtained.

  FIG. 25 shows the results of reliability data of the gate insulating film obtained by TDDB (Time Dependent Dielectric Breakdown) as a Weibull plot. The horizontal axis represents the amount of charge injected into the gate insulating film, and the vertical axis represents the degree of breakdown voltage failure. The data of the conventional example and this example are compared.

  As shown in FIG. 25, in the Weibull plot of the conventional example, the total charge amount causing the breakdown voltage failure varies between chips in the wafer surface. This indicates that there is a chip that is probable that the breakdown voltage of the gate electrode is probable in the plane, and it is understood that the reliability of the product is low. It is clear that this breakdown voltage failure of the gate electrode is a failure due to the probability that metal is mixed in the gate oxide film or at the oxide film interface.

  On the other hand, the Weibull plot of this example shows that the total amount of charge that causes a breakdown voltage failure of the gate electrode is almost constant in any chip on the wafer surface. Therefore, stochastic metal contamination can be prevented and the reliability of the product can be improved.

  In the third embodiment, aluminum 311 is used as the electrode material for the metal gate. However, titanium, zirconium, hafnium, tantalum, niobium, vanadium, or nitrides thereof can also be used. . In this case, titanium oxide, zirconium oxide, hafnium oxide, tantalum oxide, niobium oxide, and vanadium oxide are formed in the oxidation instead of the aluminum oxide 313.

  The third embodiment can be applied not only to a damascene MOSFET but also to a normal MOSFET.

  As described above, according to the third embodiment, the silicide film 317 is formed after the formation of the gate insulating film 309 using the damascene gate formation process, so that the silicide metal is mixed into the gate electrode. Can be prevented.

Sectional drawing of the manufacturing process of the semiconductor device concerning 1st Example (1) of this invention. Sectional drawing of the manufacturing process of the semiconductor device concerning the 1st Example (1) of this invention following FIG. Sectional drawing of the manufacturing process of the semiconductor device concerning 1st Example (2) of this invention. FIG. 4 is a cross-sectional view of the semiconductor device manufacturing process according to the first embodiment (2) of the present invention, following FIG. 3; Sectional drawing of the manufacturing process of the semiconductor device concerning the 1st Example (2) of this invention following FIG. Sectional drawing of the manufacturing process of the semiconductor device concerning the 1st Example (2) of this invention following FIG. Sectional drawing of the manufacturing process of the semiconductor device concerning the 1st Example (2) of this invention following FIG. Sectional drawing of the manufacturing process of the semiconductor device concerning the 1st Example (2) of this invention following FIG. Sectional drawing of the manufacturing process of the semiconductor device concerning 2nd Example (1) of this invention. Sectional drawing of the manufacturing process of the semiconductor device concerning the 2nd Example (1) of this invention following FIG. FIG. 11 is a cross-sectional view of the semiconductor device manufacturing process according to the second embodiment (1) of the present invention, following FIG. 10; Sectional drawing of the manufacturing process of the semiconductor device concerning the 2nd Example (1) of this invention following FIG. Sectional drawing of the manufacturing process of the semiconductor device concerning the 2nd Example (1) of this invention following FIG. Sectional drawing of the manufacturing process of the semiconductor device concerning the other Example of 2nd Example (1) of this invention. Sectional drawing of the manufacturing process of the semiconductor device concerning the other Example of the 2nd Example (1) of this invention following FIG. Sectional drawing of the manufacturing process of the semiconductor device concerning the other Example of 2nd Example (1) of this invention. Sectional drawing of the manufacturing process of the semiconductor device concerning the other Example of 2nd Example (1) of this invention. Sectional drawing of the manufacturing process of the semiconductor device concerning 2nd Example (2) of this invention. FIG. 19 is a cross-sectional view of the semiconductor device manufacturing process according to the second embodiment (2) of the present invention, following FIG. 18; Sectional drawing of the manufacturing process of the semiconductor device concerning the 3rd Example of this invention. FIG. 21 is a cross-sectional view of the manufacturing process of the semiconductor device according to the third example of the invention, following FIG. 20. FIG. 22 is a cross-sectional view of the manufacturing process of the semiconductor device according to the third example of the invention, following FIG. 21. FIG. 23 is a cross-sectional view of the manufacturing process of the semiconductor device according to the third example of the present invention, following FIG. 22. FIG. 6 is a cross-sectional view of a semiconductor device showing deterioration in morphology at the interface between silicon and silicide. The figure which shows the reliability of a gate insulating film. Sectional drawing of the manufacturing process of the semiconductor device by a prior art. FIG. 27 is a cross-sectional view of the manufacturing process of the semiconductor device according to the conventional technique continued from FIG. 26; FIG. 28 is a cross-sectional view of the manufacturing process of the semiconductor device according to the related art, following FIG. 27; Sectional drawing of the semiconductor device which shows the problem by a prior art. Sectional drawing of the semiconductor device which shows the problem by a prior art.

Explanation of symbols

  100, 110, 200, 220, 300 ... silicon substrate, 101, 111, 301 ... element isolation region, 102, 202 ... silicon nitride film, 103, 113, 201, 222, 303 ... polysilicon, 104, 115 ... first Silicon oxide film, 105, 122 ... second silicon oxide film, 106 ... faceted, elevated, source / drain diffusion layer, 107, 123, 205, 225, 305 ... extension diffusion layer, 112, 304 ... first Silicon nitride film, 114 ... second silicon nitride film, 116 ... resist, 117 ... silicon substrate surface, 118 ... N-type faceted, elevated, source / drain diffusion layer, 119 ... third silicon nitride film, 120 ... silicon Substrate surface, 121 ... P-type faceted elevated source / drain Spread layer 124, 317 ... Silicide film, 125, 209, 218, 308 ... Interlayer insulating film, 126 ... Tantalum oxide film, 127, 212, 310 ... Titanium nitride film, 128, 311 ... Aluminum, 203, 206a, 223 ... Side walls of the first silicon nitride film, 204, 215, 216, 224 ... Epitaxial silicon layer, 206, 207a, 226 ... Side walls of the silicon oxide film, 207, 227, 306 ... Side walls of the second silicon nitride film, 208, 228 ... Source / drain diffusion layer, 210, 217, 217a ... groove, 211, 221, 309 ... gate insulating film, 213 ... tungsten, 214, 312 ... gate electrode, 219, 219a ... cavity, 302 ... gate oxide film, 307 ... Elevated source / drain diffusion layer, 313 ... Aluminum oxide film, 314 Titanium oxide film, 315 ... silicon oxide film, 316 ... metal.

Claims (1)

Forming a dummy gate selectively on a semiconductor substrate;
Forming a first insulating film sidewall of a silicon nitride film on a side surface of the dummy gate;
Forming a first epitaxial layer in contact with the side wall of the first insulating film on the semiconductor substrate on which the dummy gate is not formed;
Implanting impurities into the first epitaxial layer to form an extension diffusion layer;
Forming a second insulating film of silicon oxide over the entire surface;
Forming a third insulating film of a silicon nitride film on the second insulating film ;
By etching the second and third insulating film, and said second side surface of the insulating film of the first insulating film sidewall and a portion on the left second insulating film sidewall of the extension diffusion layer, a step of the third insulating film sidewall and remaining said third insulating film on the side surface of the second insulating film sidewall,
Forming a second epitaxial layer in contact with the side wall of the second insulating film on the extension diffusion layer;
Implanting impurities into the second epitaxial layer to form source / drain diffusion layers;
Forming a first interlayer insulating film on the entire surface after forming the source / drain diffusion layers ;
Planarizing the first interlayer insulating film and exposing a surface of the dummy gate;
Removing the dummy gate and forming a first trench;
Forming a gate insulating film on the bottom surface of the first groove;
Forming a gate electrode on the gate insulating film;
Removing the first insulating film side wall and the third insulating film side wall to form second and third grooves;
Forming a second interlayer insulating film on the entire surface after forming the second and third grooves, and a method for manufacturing a semiconductor device.

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