KR20090083671A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
KR20090083671A
KR20090083671A KR1020080009609A KR20080009609A KR20090083671A KR 20090083671 A KR20090083671 A KR 20090083671A KR 1020080009609 A KR1020080009609 A KR 1020080009609A KR 20080009609 A KR20080009609 A KR 20080009609A KR 20090083671 A KR20090083671 A KR 20090083671A
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South Korea
Prior art keywords
layer
forming
silicon
gate
contact hole
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KR1020080009609A
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Korean (ko)
Inventor
고민구
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주식회사 하이닉스반도체
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Priority to KR1020080009609A priority Critical patent/KR20090083671A/en
Publication of KR20090083671A publication Critical patent/KR20090083671A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The present invention relates to a method for manufacturing a semiconductor device, and discloses a technology capable of reducing contact resistance by forming a buffer layer of germanium having a bandgap energy smaller than silicon between a silicon substrate and a landing plug to reduce the energy barrier of the MS junction. do. To this end, the present invention comprises the steps of forming a gate on the semiconductor substrate; Forming source / drain regions in the semiconductor substrate on both sides of the gate; And forming a landing plug including a buffer layer and a metal silicide layer on a surface of the source / drain region.

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. In particular, a semiconductor device capable of reducing contact resistance by forming a buffer layer of germanium having a bandgap energy smaller than silicon between a silicon substrate and a landing plug to reduce the energy barrier of the MS junction. It is a technique relating to the manufacturing method of.

As semiconductor devices become more integrated and faster, the size of the overall device is smaller, and as a result, the size of the contact plug in contact with the source / drain regions of the transistor is also reduced. As the size of the contact plug decreases, the contact resistance Rc between the silicon substrate and the contact plug increases. This deteriorates the current characteristics of the device and becomes a factor that inhibits the speed of the device.

There are the following ways to solve this problem. First, the size of the contact plug is increased. This is a difficult aspect since the space margin is decreasing as the device is highly integrated. Second, there is a method of increasing the impurity doping concentration on the contact surface between the silicon substrate and the contact plug. Third, there is a method of reducing the height of the energy barrier layer between the contact plug and the silicon substrate.

1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

Referring to FIG. 1A, an isolation layer 14 defining an active region 12 is formed in a semiconductor substrate 10 in an NMOS region.

Next, a screen oxide film (not shown) is formed on the semiconductor substrate 10 on which the device isolation film 14 is formed.

Here, the screen oxide film serves to protect the semiconductor substrate 10 during the subsequent ion implantation process.

Next, a well ion implantation process is performed to form a well region (not shown) in the semiconductor substrate 10 on which the screen oxide film is formed.

Referring to FIG. 1B, a gate insulating layer 16 is formed on the semiconductor substrate 10, and a gate polysilicon layer 18a, a gate electrode layer 18b, and a gate hard mask layer 18c are disposed on the gate insulating layer 16. To form.

Here, the gate insulating film 16 is formed of an oxide film, the gate electrode layer 18b is formed of a tungsten silicide (WSix) layer, and the gate hard mask layer 18c is formed of a nitride film.

Next, the stacked structure is etched by a photolithography process using a gate mask to form a gate 18.

Then, the LDD ion implantation process is performed to form the LDD region 20 in the semiconductor substrate 10 on both sides of the gate 18.

Thereafter, an insulating film for spacers is deposited on the semiconductor substrate 10 including the gate 18, and then the spacer insulating film is etched to form spacers 22 on both side walls of the gate 18.

Next, a source / drain ion implantation process is performed to form the source / drain regions 24 in the semiconductor substrate 10 on both sides of the gate 18 on which the spacers 22 are formed.

Referring to FIG. 1C, an interlayer insulating layer 26 is formed on the semiconductor substrate 10 on which the gate 18 and the spacer 22 are formed.

Referring to FIG. 1D, the interlayer insulating layer 26 is selectively etched to form contact holes 28 exposing the active regions 12 on both sides of the gate 18.

Next, the barrier metal layer 30 is formed on the entire surface of the interlayer insulating layer 26 including the contact hole 28. Here, the barrier metal layer 30 forms a titanium (Ti) film with a thickness of 100 μs.

Next, a titanium silicide (TiSi 2) film 32 is formed on the bottom of the contact hole 28 by performing a heat treatment process on the resultant product on which the barrier metal layer 30 is formed.

Referring to FIG. 1E, a landing plug (not shown) is formed by forming a conductive layer 34 on the barrier metal layer 30 and planarizing the conductive layer 34 until the interlayer insulating layer 26 is exposed in a subsequent process. To form. Here, the conductive layer 34 is formed of a tungsten (W) layer.

The tungsten (W) layer has a relatively high resistivity of about 20 mu OMEGA cm or more and thus has a limit in lowering contact resistance. In general, since the contact resistance is proportional to the specific resistance ρ / contact area Ac, it is necessary to decrease the specific resistance ρ or increase the contact area Ac to lower the contact resistance.

Here, the specific resistance is proportional to exp (height of energy barrier / sqrt (impurity concentration)), and in the above-described prior art, the height of the energy barrier is reduced by using a titanium silicide layer formed between the landing plug and the active region. Due to this, although the contact resistance is lowered, as the high integration of the device is intensified, a lower contact resistance is required.

An object of the present invention is to reduce the contact resistance by forming a buffer layer of germanium having a bandgap energy smaller than silicon between the silicon substrate and the landing plug to reduce the energy barrier of the M-S junction.

Method of manufacturing a semiconductor device according to the present invention comprises the steps of forming a gate on the semiconductor substrate; Forming source / drain regions in the semiconductor substrate on both sides of the gate; And forming a landing plug including a buffer layer and a metal silicide layer on a surface of the source / drain region.

Here, the buffer layer is formed of a germanium (Ge) layer having a thickness of 50 ~ 150Å, the metal silicide layer comprises a titanium silicide (TiSi2) layer, and the landing plug forming step is the surface of the source / drain region Forming the buffer layer and the silicon layer; Forming an interlayer insulating film over the entire surface; Selectively etching the interlayer insulating film to form a contact hole exposing the silicon layer; Forming a barrier metal layer on the entire surface including the contact hole; Reacting the silicon layer and the barrier metal layer to form the metal silicide layer by a heat treatment process; And embedding a tungsten layer in the contact hole and planarizing the tungsten layer until the interlayer insulating film is exposed.

Here, the thickness of the silicon layer is formed in a ratio of 2: 1 to the barrier metal layer, the silicon layer is formed to a thickness of 200Å, the barrier metal layer is formed of a titanium (Ti) layer to a thickness of 100Å The buffer layer and the silicon layer are formed by a selective epitaxial growth method, the heat treatment process is performed by a rapid heat treatment (RTA) method, and the heat treatment process is performed at a temperature of 700 to 900 ° C. for 20 seconds to 1 degree. Characterized in that it is carried out for minutes.

The forming of the landing plug may include forming an interlayer insulating layer on the entire surface of the landing plug; Selectively etching the interlayer insulating layer to form a contact hole exposing the source / drain region; Forming the buffer layer and the silicon layer on the bottom of the contact hole; Forming a barrier metal layer on the contact hole sidewalls; Reacting the silicon layer and the barrier metal layer to form the metal silicide layer by a heat treatment process; And embedding a tungsten layer in the contact hole and planarizing the tungsten layer until the interlayer insulating film is exposed.

The present invention provides the effect of reducing the contact resistance by forming a buffer layer of germanium having a bandgap energy smaller than silicon between the silicon substrate and the landing plug to reduce the energy barrier of the M-S junction.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

2A through 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

Referring to FIG. 2A, an isolation layer 104 defining an active region 102 is formed in an NMOS region of the semiconductor substrate 100.

Next, a screen oxide film (not shown) is formed on the semiconductor substrate 100 on which the device isolation film 104 is formed.

Here, the screen oxide film serves to protect the semiconductor substrate 100 during the subsequent ion implantation process.

Then, a well ion implantation process is performed to form a well region (not shown) in the semiconductor substrate 100 on which the screen oxide film is formed.

Referring to FIG. 2B, a gate insulating layer 106 is formed on the semiconductor substrate 100, and a gate polysilicon layer 108a, a gate electrode layer 108b, and a gate hard mask layer 108c are disposed on the gate insulating layer 106. To form.

The gate insulating film 106 is formed of an oxide film, the gate electrode layer 108b is formed of a tungsten silicide (WSix) layer, and the gate hard mask layer 108c is formed of a nitride film.

Next, the stacked structure is etched by a photolithography process using a gate mask to form a gate 108.

Next, the LDD ion implantation process is performed to form the LDD region 110 in the semiconductor substrate 100 on both sides of the gate 108.

Thereafter, an insulating film for spacers is deposited on the semiconductor substrate 100 including the gate 108, and then the spacer insulating film is etched to form spacers 112 on both side walls of the gate 108.

A source / drain ion implantation process is then performed to form source / drain regions 114 in the semiconductor substrate 100 on both sides of the gate 108 on which the spacers 112 are formed.

Referring to FIG. 2C, a buffer layer 116 is formed on the active region 102 exposed on both sides of the gate 108, and a silicon (Si) layer 118 is formed on the buffer layer 116.

Here, the buffer layer 116 is formed of a material having a work function similar to that of silicon (Si) with a Group 4 element identical to that of silicon (Si) and having a smaller energy band gap than that of silicon (Si). That is, the buffer layer 116 preferably forms a germanium (Ge) layer having a thickness of 50 to 150 kPa, preferably 100 kPa.

In addition, the thickness of the silicon layer 118 is preferably formed in a ratio of 2: 1 to the barrier metal layer to be formed in a subsequent process. When the barrier metal layer is formed to a thickness of 100 GPa, the silicon layer 118 may be 200 μs. It is preferable to form in thickness.

In addition, the process of forming the buffer layer 116 and the silicon layer 118 is preferably performed by a selective epitaxial growth (SEG) method.

Referring to FIG. 2D, an interlayer insulating film 120 is formed over the entire surface.

Referring to FIG. 2E, the landing plug contact hole 122 exposing the silicon layer 118 is selectively formed by selectively etching the interlayer insulating layer 120.

Next, the barrier metal layer 124 is formed on the entire surface including the landing plug contact hole 122.

Here, the barrier metal layer 124 preferably forms a titanium (Ti) film with a thickness of 100 GPa.

Next, a titanium silicide (TiSi 2) film 126 is formed by performing a heat treatment process on the resultant material on which the barrier metal layer 124 is formed.

Here, the titanium silicide layer 126 is formed by reaction of titanium (Ti) atoms of the barrier metal layer 124 and silicon (Si) atoms of the silicon layer 118. That is, the silicon layer 118 is converted into the titanium silicide film 126.

In addition, the heat treatment process for forming the titanium silicide film 126 uses a Rapid Thermal Annealing (RTA) method, and the heat treatment temperature is 700 to 900 ° C., and the heat treatment time is 20 seconds to 1 minute. More preferably, heat processing temperature is 860 degreeC and heat processing time is 20 second.

Referring to FIG. 2F, a landing plug (not shown) is formed by forming a conductive layer 128 on the barrier metal layer 124 and planarizing the conductive layer 128 until the interlayer insulating layer 120 is exposed in a subsequent process. To form. Here, the conductive layer 128 is preferably formed of a tungsten (W) layer.

3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

Referring to FIG. 3A, an isolation layer 204 defining an active region 202 is formed in a semiconductor substrate 200 in an NMOS region.

Next, a screen oxide film (not shown) is formed on the semiconductor substrate 200 on which the device isolation film 204 is formed.

Here, the screen oxide film serves to protect the semiconductor substrate 200 during the subsequent ion implantation process.

Next, a well ion implantation process is performed on the semiconductor substrate 200 on which the screen oxide film is formed to form a well region (not shown) in the semiconductor substrate 100.

Referring to FIG. 3B, a gate insulating layer 206 is formed on the semiconductor substrate 200, and a gate polysilicon layer 208a, a gate electrode layer 208b, and a gate hard mask layer 208c are disposed on the gate insulating layer 206. To form.

The gate insulating film 206 is formed of an oxide film, the gate electrode layer 208b is formed of a tungsten silicide (WSix) layer, and the gate hard mask layer 208c is formed of a nitride film.

Next, the stacked structure is etched by a photolithography process using a gate mask to form a gate 208.

Next, an LDD ion implantation process is performed on the semiconductor substrate 200 on which the gate 208 is formed to form the LDD region 210 in the semiconductor substrate 200 on both sides of the gate 208.

Next, after depositing a spacer insulating film on the semiconductor substrate 200 including the gate 208, the spacer insulating film is etched to form spacers 212 on both side walls of the gate 208.

Next, a source / drain ion implantation process is performed on the semiconductor substrate 200 on which the spacers 212 are formed to form the source / drain regions 214 in the semiconductor substrate 200 on both sides of the gate 208 on which the spacers 212 are formed. Form.

Referring to FIG. 3C, an interlayer insulating layer 216 is formed on the semiconductor substrate 200 on which the spacers 212 are formed.

Referring to FIG. 3D, the interlayer insulating layer 216 is selectively etched to form a landing plug contact hole 218 exposing the active regions 202 on both sides of the gate 208.

Next, a buffer layer 220 and a silicon (Si) layer 222 are formed on the bottom of the landing plug contact hole 218.

Here, the buffer layer 220 preferably forms a germanium (Ge) layer having a thickness of 50 to 150 kPa, preferably 100 kPa.

In addition, the thickness of the silicon layer 222 is preferably formed in a ratio of 2: 1 to the barrier metal layer to be formed in a subsequent process. When the barrier metal layer is formed to a thickness of 100 GPa, the silicon layer 222 is 200 GPa. It is preferable to form in thickness.

In addition, the process of forming the buffer layer 220 and the silicon layer 222 may be performed by a selective epitaxial growth (SEG) method.

Referring to FIG. 3E, the barrier metal layer 224 is formed on the entire surface of the interlayer insulating layer 216 including the landing plug contact hole 218.

Here, the barrier metal layer 224 preferably forms a titanium (Ti) film with a thickness of 100 GPa.

Next, a titanium silicide (TiSi 2) film 226 is formed by performing a heat treatment process on the resultant product on which the barrier metal layer 224 is formed.

Here, the titanium silicide layer 226 is formed by reaction of titanium (Ti) atoms of the barrier metal layer 224 and silicon (Si) atoms of the silicon layer 222. That is, the silicon layer 222 is converted into the titanium silicide layer 226.

In addition, the heat treatment process for forming the titanium silicide film 226 uses a rapid thermal treatment (RTA) method, the heat treatment temperature is 700 ~ 900 ℃, the heat treatment time is preferably 20 seconds to 1 minute. More preferably, heat processing temperature is 860 degreeC and heat processing time is 20 second.

Referring to FIG. 3F, the conductive layer 228 is formed on the barrier metal layer 224, and the landing layer (228) is planarized by planarizing the conductive layer 228 until the interlayer insulating layer 216 is exposed in a subsequent process. To form. Here, the conductive layer 228 is preferably formed of a tungsten (W) layer.

4 is a diagram illustrating the effect of the present invention, and shows an energy band of an NMOS transistor.

Referring to FIG. 4, both silicon (Si) and germanium (Ge) have a work function similar to titanium silicide (TiSi 2) as a Group 4 element. That is, titanium silicide (TiSi2) has a work function of 4.9V and silicon (Si) and germanium (Ge) of about 4.8V.

The energy bandgap Eg of silicon (Si) is 1.12V and the energy bandgap Eg of germanium (Ge) is 0.67V, and the energy bandgap of germanium (Ge) is about 0.5V smaller than that of silicon (Si).

Due to this characteristic, an MS junction is formed between germanium (Ge) and titanium silicide (TiSi2) as compared to the formation of a metal junction (silicon junction) (silicon junction) between silicon (Si) and titanium silicide (TiSi2). The height H and the width W of the energy barrier are reduced.

That is, the energy barrier is reduced by 0.25V from the height H1 of 0.6V to the height H2 of 0.35V, and thus the width W is also reduced to increase the tunneling current. In addition, as the height decreases, the current due to thermal emission also increases. Accordingly, the contact resistance Rc may be reduced as a whole by reducing the specific resistance ρ of the contact.

1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

4 is a view for explaining the effect of the present invention.

Claims (10)

Forming a gate over the semiconductor substrate; Forming source / drain regions in the semiconductor substrate on both sides of the gate; And Forming a landing plug including a buffer layer and a metal silicide layer on a surface of the source / drain region Method of manufacturing a semiconductor device comprising a. The method of claim 1, wherein the buffer layer is formed of a germanium (Ge) layer having a thickness of about 50 to about 150 microns. The method of claim 1, wherein the metal silicide layer comprises a titanium silicide (TiSi 2) layer. The method of claim 1, wherein the landing plug forming step Forming the buffer layer and the silicon layer on a surface of the source / drain region; Forming an interlayer insulating film over the entire surface; Selectively etching the interlayer insulating film to form a contact hole exposing the silicon layer; Forming a barrier metal layer on the entire surface including the contact hole; Reacting the silicon layer and the barrier metal layer to form the metal silicide layer by a heat treatment process; And Embedding a tungsten layer in the contact hole and planarizing the tungsten layer until the interlayer insulating film is exposed; Method of manufacturing a semiconductor device comprising a. The method of claim 4, wherein the silicon layer is formed to have a thickness of 2: 1 with the barrier metal layer. The method of claim 5, wherein the silicon layer is formed to a thickness of 200 kPa, and the barrier metal layer is formed of a titanium (Ti) layer to a thickness of 100 kPa. The method of claim 4, wherein the buffer layer and the silicon layer are formed by a selective epitaxial growth method. The method of claim 4, wherein the heat treatment is performed by a rapid heat treatment (RTA) method. The method of claim 4, wherein the heat treatment is performed at a temperature of 700 to 900 ° C. for 20 seconds to 1 minute. The method of claim 1, wherein the landing plug forming step Forming an interlayer insulating film over the entire surface; Selectively etching the interlayer insulating layer to form a contact hole exposing the source / drain region; Forming the buffer layer and the silicon layer on the bottom of the contact hole; Forming a barrier metal layer on the contact hole sidewalls; Reacting the silicon layer and the barrier metal layer to form the metal silicide layer by a heat treatment process; And Embedding a tungsten layer in the contact hole and planarizing the tungsten layer until the interlayer insulating film is exposed; Method of manufacturing a semiconductor device comprising a.
KR1020080009609A 2008-01-30 2008-01-30 Method for manufacturing semiconductor device KR20090083671A (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102569144A (en) * 2010-12-22 2012-07-11 中芯国际集成电路制造(上海)有限公司 Through hole etching method
US8558316B2 (en) 2011-01-06 2013-10-15 Samsung Electronics Co., Ltd. Semiconductor device including metal silicide layer and fabrication method thereof
US9331080B2 (en) * 2014-09-23 2016-05-03 Samsung Electronics Co., Ltd. Semiconductor device having contact plug and method of forming the same
US9899379B2 (en) 2015-05-21 2018-02-20 Samsung Electronics Co., Ltd. Semiconductor devices having fins
CN109979949A (en) * 2017-12-27 2019-07-05 瑞萨电子株式会社 Semiconductor device and its manufacturing method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102569144A (en) * 2010-12-22 2012-07-11 中芯国际集成电路制造(上海)有限公司 Through hole etching method
US8558316B2 (en) 2011-01-06 2013-10-15 Samsung Electronics Co., Ltd. Semiconductor device including metal silicide layer and fabrication method thereof
US9331080B2 (en) * 2014-09-23 2016-05-03 Samsung Electronics Co., Ltd. Semiconductor device having contact plug and method of forming the same
US9899379B2 (en) 2015-05-21 2018-02-20 Samsung Electronics Co., Ltd. Semiconductor devices having fins
CN109979949A (en) * 2017-12-27 2019-07-05 瑞萨电子株式会社 Semiconductor device and its manufacturing method

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