JP3778156B2 - Semiconductor device - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a semiconductor manufacturing apparatus in which contact resistance between an impurity diffusion layer formed on a semiconductor substrate and a wiring layer is reduced.
[0002]
[Prior art]
Integration of semiconductor devices is accompanied by miniaturization of device patterns. Accordingly, the contact area between the impurity diffusion layer formed on the semiconductor substrate and the wiring layer connected to the impurity diffusion layer is inevitably reduced. Miniaturization of the contact area leads to an increase in contact resistance and a burden on the device. Therefore, a new measure to reduce the contact resistance has become necessary.
[0003]
Generally, the contact resistivity value ρ between the impurity diffusion layer and the wiring layer_cAnd contact resistance value R_CIs given by the following two equations.
[0004]
[Expression 1]
ρ_c∝exp {4π (ε_c・ M^*)^1/2・ Φ_B/ ((N_D)^1/2・ Q ・ h)}
[0005]
[Expression 2]
R_C= Ρ_c/ A_C
In the above formula, Φ_BIs the height of the Schottky barrier between the metal which is the wiring material and the semiconductor forming the impurity diffusion layer, N_DIs the carrier concentration, m^*Is the effective mass of the carrier, ε_cIs the dielectric constant of the semiconductor, h is Planck's constant, A_CIs the contact area.
[0006]
From the above two formulas, contact resistance value R_C1) Contact area A_C2) Schottky barrier height Φ_B2) Carrier concentration N_DMeasures such as increasing
[0007]
Contact area A_CAs the miniaturization progresses, it tends to decrease. In addition, considering that there is a limit to the concentration of impurities that can be dissolved in the Si substrate, in addition, the shallowness of the impurity diffusion layer that accompanies miniaturization, and the lowering of the process further reduces the solid solution limit of impurities. , Carrier concentration N_DI can not expect much to increase.
[0008]
Schottky barrier height Φ_BAs a method of reducing the_BIt is conceivable to select a metal material having a small size. However, in general, in the case of metal, a material having a small Schottky barrier for an n-type semiconductor tends to have a high Schottky barrier for a p-type semiconductor. This property is attributed to the relationship between the metal and the semiconductor represented by the following formula.
[0009]
[Equation 3]
Eg ≒ Φ_Bn + Φ_Bp
Where Eg is the semiconductor bandgap, Φ_BnIs the value of Schottky barrier for n-type semiconductor, Φ_BpIndicates a Schottky barrier value for a p-type semiconductor.
[0010]
Since the wiring layer is connected to the impurity diffusion layer containing Si, Eg in the above formula is a value that is substantially close to the Si band gap of 1.12 eV. For example, Φ_BnIs selected to be as small as 0.2 eV, Eg is 1.05 eV, Φ_BpBecomes 0.85 eV. When Ti is selected, Eg is 1.10 eV, Φ_BnIs 0.50 eV, Φ_BpIs 0.60 eV (E.H.Rhoderick, Metal Semiconductor Contacts, Oxford Press, London, 1980).
[0011]
In many cases, both p-type and n-type impurity diffusion layers exist on the device. Φ for each conductivity type_BIn order to make the value small, it was necessary to select a different wiring material for each conductivity type. However, from the viewpoint of increasing the efficiency of the process, it is desired to select one material that can handle both conductivity types.
[0012]
The band gap of Ge is 0.67 eV, which is considerably smaller than that of Si. Therefore, by sandwiching Ge, which is a semiconductor, on the connection surface between the wiring material and the impurity diffusion layer, Φ_Bn, Φ_BpBoth can be reduced. That is, the use of Ge makes it possible to reduce the contact resistance for either conductivity type.
[0013]
As a method using Ge for the contact portion between the semiconductor layer and the wiring layer so far, there is a method of forming a Ge single layer film on the impurity diffusion layer by sputtering or CVD (vapor phase growth method). there were. However, the deposition of a Ge monolayer on the Si film may generate a defect that causes current leakage at the interface due to a mismatch in lattice constant.
[0014]
Therefore, it has been studied to adjust the composition stepwise and continuously as a SiGe layer instead of Ge alone. Although it is possible to adjust the composition of Si / Ge by using a CVD method or a sputtering method, SiGe in which the Ge / Si ratio changes continuously in the depth direction more easily by using an ion implantation method. A layer can be formed.
[0015]
When the ion implantation method is used, Ge ions are implanted into the impurity diffusion Si layer to form a SiGe layer on the surface layer. There are also advantages such that the implantation layer can be selectively formed using a mask, and the ion implantation depth can be adjusted with good controllability by adjusting the dose, ion acceleration voltage, and the like.
[0016]
[Problems to be solved by the invention]
A SiGe layer is formed on the surface of the impurity diffusion Si layer into which Ge is ion-implanted. In order to reduce the contact resistance with the wiring, it is desirable to increase the Ge concentration on the contact surface as much as possible. As the ratio of Ge to Si increases, the band gap decreases and Φ_BThis is because the value can be reduced.
[0017]
However, the Ge ion implantation layer formed by the ion implantation method has a high concentration at a position deeper than the surface under any condition, although the concentration distribution in the depth direction changes depending on the conditions of the ion acceleration voltage and the dose amount. Concentration distribution close to a Gaussian shape with a peak is shown. Further, depending on conditions, the Ge concentration on the surface of the impurity diffusion layer may be considerably low.
[0018]
An object of the present invention is to provide a semiconductor device in which a high-concentration Ge layer is reliably formed on the surface of an impurity diffusion layer connected to a wiring layer.
[0019]
[Means for Solving the Problems]
According to one aspect of the present invention, a first impurity diffusion layer having a conductivity type opposite to the first conductivity type formed in a predetermined surface region of the crystal region having the first conductivity type of the Si substrate; A second impurity diffusion layer having the same conductivity type as the first conductivity type formed in another predetermined surface layer region of the crystal region, and a first impurity layer formed so as to be connected to the first impurity diffusion layer And a second wiring layer formed so as to be connected to the second impurity diffusion layer, and the Si substrate connected to the first and second wiring layers. The surfaces of both the first and second impurity diffusion layers are etched, and Ge is added to the surface portions of the first and second impurity diffusion layers. A semiconductor device is provided which is the highest and decreases continuously in the depth direction.
[0020]
[Action]
Since ion-implanted Ge has a concentration distribution close to a Gaussian shape in the depth direction, a highly concentrated Ge layer can be exposed on the surface by etching to an appropriate position. When Ge is implanted into the Si crystal region, the higher the Ge / Si ratio, the smaller the band gap of SiGe, and Φ_BCan also be lowered. Moreover, the shape of the connection surface can be made concave by etching, and the contact area can be effectively expanded by the side surface portion. These all lower the contact resistance between the impurity diffusion layer and the wiring layer.
[0021]
Further, Ge ion implantation performed before impurity ion implantation makes the implanted region amorphous. Impurity ion implantation is performed on the amorphous layer, so that channeling is suppressed and the impurity diffusion layer can be formed shallow.
[0022]
When a Ge single layer film is used for the first layer of the wiring layer, the contact resistance between the impurity diffusion layer and the wiring layer can be further reduced.
[0023]
【Example】
Embodiments of the present invention will be described below with reference to the drawings. First, the formation method of the first embodiment will be described by taking out, in particular, the n channel portion of the CMOS semiconductor device.
[0024]
First, B is about 3 × 10¹⁵atoms / cm^ThreeThe added p-type plane orientation (100) Si substrate 1 is prepared. As shown in FIG. 2A, about 30 nm of SiO is formed on the substrate surface by thermal oxidation.₂After the film 2 is formed, ion implantation of B ions is performed. The ion implantation conditions at this time are SiO₂Conditions under which the ion-implanted layer 3 ′ can be formed through the layer of the film 2, for example, an ion acceleration voltage of 30 KeV and a dose of 1.5 × 10¹³ions / cm²The following conditions are used.
[0025]
Thereafter, for example, heat treatment is performed at 1150 ° C. for 240 minutes to activate the ion-implanted layer and to deeply diffuse (drive-in) the implanted B. This diffusion layer forms the p-type well 3 shown in FIG. In addition, SiO₂The film 2 is used as an ion implantation mask when forming a p-type well and an n-type well not shown in the figure.
[0026]
Next, the first SiO₂Etch film 2 and thermally oxidize the substrate again to re-apply about 15 nm of SiO₂A film 2a is formed. SiO₂SiN having a thickness of about 140 nm is formed on the film 2a by CVD (vapor phase growth)._xA film is formed. SiN_xA resist film is formed on the entire surface of the film, and a resist mask 5 is formed through exposure and development. Using this resist mask 5 as an etching mask, SiN_xEtch the film and add SiN_xA film pattern 4 is formed.
[0027]
As shown in FIG. 2 (B), SiN_xB ions are implanted using the film pattern 4 and the resist mask 5 as an ion implantation mask to form an ion implantation layer 6 for forming a channel stop region. For example, an ion acceleration voltage of 100 KeV and a dose of 1.5 × 10¹³ions / cm²The following conditions are used. Thereafter, the resist mask is removed.
[0028]
Next, SiN_xThermal oxidation is performed using the film pattern 4 as a mask to form a field oxide film 7 having a thickness of about 400 nm as shown in FIG. The ion implantation layer 6 is activated by this thermal oxidation process, and a high concentration p-type channel stop region 8 is formed under the field oxide film. After this SiN_xThe film pattern 4 is removed by etching.
[0029]
As shown in FIG. 2C, B ion implantation is performed using the field oxide film 7 as an ion implantation mask to form an ion implantation layer 9. The ion implantation conditions at this time are thin SiO₂A condition is selected in which the film 2a passes but cannot exceed the thick field oxide film 7. For example, an ion acceleration voltage of 15 KeV and a dose of 1.5 × 10¹²ions / cm²This is the condition. This ion implantation layer 9 functions as threshold voltage control.
[0030]
Next, a gate electrode is formed. A two-layer film of a polycrystalline Si film and a WSi film is deposited on the entire surface of the substrate by, for example, 150 nm each by sputtering. Such a two-layer film structure in which metal silicide is formed on a polycrystalline Si film is called a polycide structure. A resist film is formed on the entire surface of the WSi film, and a resist mask pattern is obtained by exposure and development.
[0031]
Using this resist mask as an etching mask, Cl₂, O₂, He mixed gas or HBr, SF₆ Using a mixed gas of polycide layer and SiO₂The film 2a is dry etched. When the resist that is no longer needed is removed, the gate electrode 11 shown in FIG. 3D is obtained.
[0032]
Next, as shown in FIG. 3E, P ions are implanted using the field oxide film 7 and the gate electrode 11 as an ion implantation mask to form an ion implantation layer 12 in a very shallow region. For example, the ion implantation conditions at this time include an ion acceleration voltage of 80 KeV and a dose amount of 4.0 × 10.¹³ions / cm²An injection angle of 45 degrees is used. The ion implantation layer 12 forms an LDD (Lightly doped drain) region.
[0033]
Subsequently, SiO having a thickness of about 200 nm is formed by a CVD method using TEOS (tetraethoxysilane) on the entire surface.₂A film is formed. Using RIE (reactive ion etching), this SiO₂The film is etched, and SiO 2 is formed only on the side wall of the gate electrode 11 as shown in FIG.₂Region 13 is formed. This SiO₂The region 13 is generally called a side spacer or sidewall oxide.
[0034]
Next, the step of ion implanting Ge will be described. Conventionally, the Ge layer or SiGe layer formed for the purpose of reducing the contact resistance between the impurity diffusion layer and the wiring layer has been formed after the formation of the impurity diffusion layer. In this embodiment, as will be described below, Ge ion implantation is performed before an impurity ion implantation step, which is a step of forming an impurity diffusion layer.
[0035]
As shown in FIG. 4G, ion implantation of Ge ions is performed using the field oxide film 7, the gate electrode 11, and the side spacers 13 formed on both walls thereof as a mask to form an implantation layer 21. The ion implantation conditions are set so that the Ge distribution range is shallower than the impurity distribution depth obtained by impurity ion implantation performed after this step. For example, ion acceleration voltage 30 to 150 KeV, dose amount 5.0 × 10¹³~ 5.0 × 10¹⁵ions / cm²Preferably ion acceleration voltage 30-80 KeV, dose amount 1.0-5.0 × 10¹⁴ions / cm²More preferably, the ion acceleration voltage is 30 KeV and the dose amount is 2.0 × 10.¹⁴Select the conditions.
[0036]
Subsequently, as shown in FIG. 4H, P ions, which are ions that impart conductivity, are ion-implanted to form the ion-implanted layer 22. As ion implantation conditions at this time, for example, an ion acceleration voltage of 20 KeV and a dose of 5.0 × 10¹⁵ions / cm²If an ion implantation condition of 45 ° is used, an impurity distribution having a depth of about 0.12 μm is obtained immediately after the ion implantation.
[0037]
Thereafter, an RTA (rapid thermal annealing) apparatus is used and the substrate is made N.₂The temperature is raised to 800-1000 ° C. in 10 seconds in an atmosphere, and annealing is performed under the condition that this temperature is maintained for 10 seconds. The impurities in the ion implantation layer 22 are activated, and the implantation layer is recrystallized to form an impurity diffusion layer 23 shown in FIG.
[0038]
As performed in this example, Ge ion implantation before impurity ion implantation is not only for forming a Ge mixed layer in the surface region of the impurity diffusion layer, but also for impurity diffusion as described below. The effect of shallowing the layer (bonding) is brought about.
[0039]
FIG. 6 shows the impurity distribution in the depth direction of the impurity diffusion layer. The horizontal axis represents the depth, and the vertical axis represents the impurity concentration imparting conductivity. As devices are highly integrated, it is desired that the impurity distribution width be as shallow as possible because the impurity diffusion layer, so-called junction shallowing, is required. A solid line indicates the impurity concentration distribution immediately after impurity ion implantation when Ge ion implantation is performed before impurity ion implantation corresponding to this embodiment. An impurity concentration distribution in the case where impurity ions are directly implanted into a crystal substrate without performing Ge ion implantation is indicated by a broken line. By performing Ge ion implantation in advance, the impurity concentration distribution width becomes considerably shallow.
[0040]
When impurity ions are directly ion-implanted into the crystal substrate, channeling occurs in which the implanted ions penetrate deeply into the substrate through the gaps of the substrate crystal lattice without causing major collisions with the substrate atoms. However, the ion implantation of Ge having an atomic weight of 16 or more performed before impurity ion implantation can make the substrate surface amorphous. Since there is no regular crystal lattice in the amorphous layer, channeling of impurities implanted into this amorphous layer is suppressed. Thus, in this embodiment, Ge ion implantation suppresses P channeling, and a shallow junction as shown in FIG. 6 can be formed.
[0041]
Subsequently, a process after the formation of the impurity diffusion layer will be described. As shown in FIG. 4 (I), a two-layer film of a PSG film (phosphosilicate glass) having a film thickness of about 100 nm and a BPSG film (boron phosphosilicate glass) having a film thickness of about 600 nm is formed using atmospheric pressure CVD. An interlayer insulating film 24 is formed on the entire surface.
[0042]
Thereafter, a resist film is formed on the interlayer insulating film 24, and a resist mask is formed by exposure and development. By using this resist mask as an etching mask, etching is performed to form a contact hole in the interlayer insulating film 24 for connecting the impurity diffusion layer and the wiring layer. The resist film is removed at this time or after the subsequent etching step of the impurity diffusion layer.
[0043]
Further, as shown in FIG. 5J, the exposed surface of the impurity diffusion layer is etched so that a high concentration region of Ge is exposed using the interlayer insulating film 24 in which the contact holes are formed as a mask. Etching conditions include, for example, a parallel plate type reactive ion etching apparatus that enables trench etching, for example, HBr of 10 to 15 sccm, preferably 12 sccm, Cl₂Is 25 to 30 sccm, preferably 27 sccm, and the pressure is 100 to 150 mtorr, preferably 125 mtorr, and the RF output is 300 to 500 W, preferably 400 W.
[0044]
FIG. 7 shows the concentration distribution of Ge in the depth direction before and after the etching process on the surface of the impurity diffusion layer. FIG. 7A shows the Ge concentration distribution immediately before etching. It has a density distribution close to a Gaussian type having the highest density Cmax at the depth of Dc from the substrate surface.
[0045]
The etching depth is most preferably the depth Dc at which the Ge concentration is the highest. For example, in the case of dry etching, the etching depth can be controlled by monitoring the Ge emission spectrum and ending the etching at the point where the emission intensity is highest. It can also be dealt with by controlling the etching time by measuring the Ge impurity distribution and the etching rate in advance.
[0046]
When the surface of the impurity diffusion layer is etched to an ideal depth Dc in this way, a region having the highest Ge concentration can be brought to the surface of the impurity diffusion layer as shown in FIG. 7B. As will be described later, this etching step can be performed on the n channel and the p channel simultaneously. Both channels can bring the region with the highest Ge concentration to the surface of the impurity diffusion layer.
[0047]
Furthermore, as shown in FIG. 5J, the etched surface portion of the impurity diffusion layer is concave. With this shape, the contact area can be effectively expanded, and the contact resistance can be further reduced.
[0048]
Thereafter, as shown in FIG. 5K, a so-called barrier metal layer 31 such as a TiN or WSi film is formed by sputtering to about 50 nm. Subsequently, an Al alloy layer 32 made of, for example, an Al—Si—Cu 3 composition is formed by sputtering to about 800 nm.
[0049]
A resist film is formed on the entire surface of the substrate, and a resist mask having an electrode / wiring pattern is formed by exposure and development. Using this resist mask as an etching mask, the barrier metal layer 31 and the Al alloy layer 32 are etched. The resist that is no longer needed is removed, and desired wiring is formed as shown in FIG. Further, a PSG film having a film thickness of 100 to 500 nm, preferably 150 nm, and a SiN film having a film thickness of 500 to 1500 nm, preferably 1000 nm, are formed on the entire surface of the substrate using plasma CVD._xA continuous passivation film 33 made of a film is formed.
[0050]
A resist film is formed on the entire surface of the substrate, and a resist mask having openings corresponding to bonding pads, scribe lines and the like is formed by exposure and development. Using this resist mask as an etching mask, the passivation film is etched, and a window for a bonding pad or the like for leading out the wiring is formed. In addition, this window opening is abbreviate | omitted in drawing.
[0051]
Finally, the substrate is annealed at 400 ° C. for 30 minutes in a hydrogen atmosphere, and charges generated in the gate oxide film are neutralized due to damage in various processes. In the above embodiment, only the formation process of the n-channel portion of the CMOS transistor has been described. Of course, the p-channel is also formed in the CMOS manufacturing process. A cross-sectional view of a CMOS semiconductor device having both channels is shown in FIG. An n channel formed by the above-described process and a p channel are formed on the n type well 41 on the p type well 3 on the Si crystal substrate 1, respectively. When a p-channel is formed, a portion unnecessary for the n-channel region or the like is covered with a resist mask, and ion implantation or the like is performed. Examples of conductivity imparting ions include B and BF.₂Select and inject. Steps such as Ge ion implantation and impurity diffusion layer etching are common to both channels and can be performed simultaneously.
[0052]
Next, the forming method of the second embodiment will be described. The second embodiment is different from the first embodiment in the surface etching process of the impurity diffusion layer. The process up to the annealing step of the impurity diffusion layer is common to the first embodiment. A process after the formation of the impurity diffusion layer will be described below with reference to FIG.
[0053]
As shown in FIG. 8A, the p-type well layer 3, the field oxide film 7, the channel stop region 8, the gate electrode 11, the impurity diffusion layer 23, and the like are formed through the same process as in the first embodiment. SiO on the entire surface of the substrate₂The film is formed by CVD or sputtering. Further, a resist film is formed on the entire surface, and a resist mask is formed through exposure and development processes. Using this resist mask as an etching mask, this SiO₂The film is dry etched. Wet etching may be used.
[0054]
Thus, SiO other than the impurity diffusion layer, particularly on the gate electrode₂A film etching mask 51 is formed. The material of the etching mask is SiN_xA film or the like may be used.
[0055]
Next, as shown in FIG.₂, O₂, SF₆, Dry etching is performed using a mixed gas such as HBr. The entire surface of the impurity diffusion layer not covered with the etching mask is etched. As in the first embodiment, etching is performed to a depth at which the Ge concentration is almost the highest.
[0056]
As shown in FIG. 8C, an interlayer insulating film 24 is formed on the entire surface of the substrate. Since the etching mask 51 is made of the same material as that of the interlayer insulating film, it is not particularly necessary to remove it by etching. The subsequent process steps for forming contact holes, wiring layers, passivation films, etc. use the same process conditions as in the first embodiment. Of course, the etching of the impurity diffusion layer after the contact hole is formed in the interlayer insulating film in the first embodiment is omitted because it has already been performed in the above process. FIG. 9 shows a cross-sectional view of the n-channel portion of the CMOS semiconductor device that has undergone the final process.
[0057]
Thus, in the second embodiment, when etching the impurity diffusion layer, a relatively wide region is etched, so that the isotropic etching conditions can be used without being limited to the trench etching conditions. . Therefore, wet etching can also be performed.
[0058]
As shown in FIG. 8B, when the entire surface of the impurity diffusion layer is etched, the connection portion of the wiring layer is flat, but only the connection portion of the impurity diffusion layer and the wiring is opened. If an etching mask is used, a concave etching shape can be formed in the connection portion as in the first embodiment, and the contact area can be expanded.
[0059]
The etching may be performed immediately after impurity ion implantation. In this case, the ion implantation layer is annealed after the etching is completed. A third embodiment will be described. FIG. 10 shows a cross-sectional structure of the n-channel portion of the CMOS semiconductor device. A Ge single layer film 61 is provided as a first layer of the wiring layer below the barrier metal layer 31. The forming method conforms to the method of the first embodiment described above, but before the barrier metal forming step, a step of forming a single-layer thin film of several tens to several hundreds of Ge by sputtering or CVD is added to this. . In this embodiment, a Ge layer having a small band gap can be reliably formed at the connection portion between the impurity diffusion layer and the wiring layer.
[0060]
A fourth embodiment will be described with reference to FIG. As shown in FIG. 11, so-called well contacts are formed on both sides of the n channel portion and p channel portion of the CMOS semiconductor device already shown in FIG. (The part indicated by α in the figure). This well contact portion can also form a low resistance connection portion in the same manner as the connection portion between the source / drain portion and the wiring layer shown in the first embodiment.
[0061]
For example, Ge is implanted into the surface layer portion of each well. Thereafter, ion doping of impurities having the same conductivity type as each well is performed, and an annealing process is further performed. Thus, an impurity diffusion layer 71 having a higher concentration than the surrounding well concentration is formed in the well surface layer. Thereafter, the surface portion of the well is etched to expose a high concentration region of Ge on the surface. The wiring layer is connected to the surface layer of high concentration Ge through a contact hole.
[0062]
The well contact is manufactured in parallel with the source and drain portions of the first embodiment, and those that can be formed simultaneously are formed simultaneously. Therefore, specific manufacturing conditions such as ion implantation conditions, impurity materials, and wiring materials may be the same as those in the first embodiment.
[0063]
Although the four embodiments have been described above, each wiring forming process may be combined with a flattening process such as Al reflow using a high-temperature sputtering method or a W film creation using a CVD method. In addition, this invention is not restrict | limited to an above-described Example. It will be apparent to those skilled in the art that various materials can be changed, improved, combined, and the like.
[0064]
【The invention's effect】
According to the present invention, the contact surface between the impurity diffusion layer and the wiring layer in the Si substrate has a high Ge / Si ratio, that is, Φ._Bn, Φ_BpCan be reduced. Moreover, the contact surface can be concave, and the contact area can be effectively expanded. These effects can also reduce the contact resistance between the impurity diffusion layer and the wiring layer.
[0065]
At the same time, the Ge ion implantation layer can suppress channeling that occurs during impurity ion implantation and can reduce the depth of the impurity diffusion layer.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a CMOS semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view showing a manufacturing process of the CMOS semiconductor device according to the first embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a process for manufacturing a CMOS semiconductor device according to the first embodiment of the present invention;
FIG. 4 is a cross-sectional view showing a process of manufacturing a CMOS semiconductor device according to the first embodiment of the present invention.
FIG. 5 is a cross-sectional view showing a manufacturing process of the CMOS semiconductor device according to the first embodiment of the present invention.
FIG. 6 is a graph showing a concentration distribution of impurities in a depth direction in an impurity diffusion layer.
FIG. 7 is a graph showing the concentration distribution of Ge in the depth direction in the impurity diffusion layer.
FIG. 8 is a cross-sectional view showing a manufacturing process of a CMOS semiconductor device according to a second embodiment.
FIG. 9 is a sectional view showing a CMOS semiconductor device according to a second embodiment.
FIG. 10 is a sectional view showing a CMOS semiconductor device according to a third embodiment.
FIG. 11 is a sectional view showing a CMOS semiconductor device according to a fourth embodiment.
[Explanation of symbols]
1 ... Si substrate, 2, 2a ... SiO₂Membrane, 3 '... ion implantation layer, 3 ... p-type well, 4 ... SiN_xFilm pattern, 5 ... resist mask, 6 ... ion implantation layer, 7 ... field oxide film, 8 ... channel stop region, 9 ... ion implantation layer, 11 ... gate electrode, 12 ... Ion implantation layer, 13 ... Side spacer, 21 ... Ion implantation layer, 22 ... Ion implantation layer, 23 ... Diffusion layer, 24 ... Interlayer insulating film, 31 ... Barrier Metal, 32 ... Al alloy, 33 ... passivation film, 41 ... n-type well, 51 ... etching mask, 61 ... Ge film, 71 ... impurity diffusion layer, α ... Well contact.

Claims (3)

A first impurity diffusion layer having a conductivity type opposite to the first conductivity type formed in a predetermined surface region of the crystal region having the first conductivity type of the Si substrate, and another predetermined surface layer of the crystal region; A second impurity diffusion layer having the same conductivity type as the first conductivity type formed in the region; a first wiring layer formed so as to be connected to the first impurity diffusion layer; In a configuration having a second wiring layer formed so as to be connected to the impurity diffusion layer,
The surfaces of the first and second impurity diffusion layers of the Si substrate connected to the first and second wiring layers are both etched, and the surface layers of the first and second impurity diffusion layers A semiconductor device in which Ge is added to the portion, the Ge concentration distribution is almost highest on the surface, and continuously decreases in the depth direction. The semiconductor device according to claim 1, wherein surfaces of the first and second impurity diffusion layers to which the first and second wiring layers are connected are etched in a concave shape. 3. The semiconductor device according to claim 1, wherein the first layer on the side connected to the first and second impurity diffusion layers of the first and second wiring layers is a Ge single layer film.

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