JP2006190822A - Method for manufacturing insulated gate field effect transistor and insulated gate field effect transistor - Google Patents

Method for manufacturing insulated gate field effect transistor and insulated gate field effect transistor Download PDF

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JP2006190822A
JP2006190822A JP2005001609A JP2005001609A JP2006190822A JP 2006190822 A JP2006190822 A JP 2006190822A JP 2005001609 A JP2005001609 A JP 2005001609A JP 2005001609 A JP2005001609 A JP 2005001609A JP 2006190822 A JP2006190822 A JP 2006190822A
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JP5007488B2 (en
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Tsutomu Imoto
努 井本
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Sony Corp
ソニー株式会社
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Abstract

An extension portion having an optimum junction depth cannot be formed corresponding to the shortening of the gate length.
Two source / drain regions are formed in a P-well by impurity ion implantation and activation annealing using a spacer having a predetermined width made of a gate stack and a sidewall insulating film as a mask. By removing the sidewall insulating film 9 and forming a thinner partition insulating film 11, both sides of the spacer in the width direction are retreated. As a result, the edge of the spacer is separated from the edges of the two source / drain regions 10 on both sides in the width direction. In this state, a semiconductor material is grown by selective epitaxial growth in the well region including the two source / drain regions 10 exposed on both sides in the width direction of the receded spacer, and two extension portions 12 separated by the receded spacer are formed. To do. In this manufacturing method, the impurities in the extension portion 12 are not thermally diffused into the P well 3 by the ion implantation activation annealing.
[Selection] Figure 3

Description

  The present invention relates to a method for manufacturing an insulated gate field effect transistor having an extension portion and source / drain regions on both sides of a portion where a gate electrode is formed, and the transistor.

In a MOS integrated circuit, the main factors that determine the operation speed of a circuit are the on-current of the MOSFET and the size of the load capacitance charged and discharged by the on-current. The on-current generally increases as the channel resistance decreases as the gate length decreases. Therefore, if the gate length is shortened, the on-current increases and the operation speed of the integrated circuit can be increased.
However, since the gate length is shorter than 100 nm, it is not easy to obtain an increase in on-current that corresponds to the shortening of the gate length. One of the causes will be described below with reference to FIG.

FIG. 11A is a schematic diagram of a cross-sectional structure of a conventional planar type MOSFET.
In the structure of FIG. 11A, a source region and a drain region are regions for providing a connection hole with an external wiring, and impurities having a conductivity type opposite to that of the substrate (well if there is a well) are introduced at a high concentration. A low-resistance semiconductor region. In order to reduce the contact resistance between the semiconductor region and the electrode plug (not shown) of the connection hole, an alloy layer (silicide layer) of Co or Ni and a substrate material (Si) is usually formed on the surface of the source region and the drain region. Is provided. The alloy layer grows toward the inside of the substrate. However, if the alloy layer is too close to the PN junction with the substrate, the junction breakdown voltage is reduced and the substrate leakage current is increased. Therefore, the source region and the drain region are usually formed sufficiently thick with respect to the thickness of the alloy layer. For example, when forming CoSi 2 , the junction depth needs to be 60 nm or more, preferably 100 nm or more.

  An extension portion is provided between the source or drain region and the gate. A part of the extension portion overlaps with the gate electrode with the gate insulating film interposed therebetween to form an overlap region. The channel inversion layer is formed between two extension portions on the source side and the drain side.

  In the structure shown in FIG. 11A, when the gate length is shortened, a so-called short channel effect (SCE) becomes obvious, and the threshold voltage is increased by a depletion layer extending from the source region, the drain region, or the extension portion toward the channel. Decrease, subthreshold slope decrease, and DIBL (Drain Induced Barrier Lowering) increase.

In order to suppress the short channel effect, it is necessary to sufficiently reduce the junction depth of the source region and the drain region and the junction depth of the extension portion (Xj in the drawing) as the channel length is shortened. However, in such a shallow diffusion layer, even if the impurity concentration is increased to the solid solution limit, the current cross-sectional area is small and the resistance is high, which is one of the factors that limit the on-current.
To solve this problem, a structure has been proposed in which the source region and the drain region or the extension portion are positioned at the same depth as or higher than the inversion layer of the channel. Their structures are schematically shown in FIGS. 11B and 11C.

FIG. 11B is a schematic diagram of a structure called “groove gate” or “recess gate”.
The above-described positional relationship between the extension portion and the inversion layer is realized by adopting a gate electrode structure in which a channel is formed at the bottom of a trench or recess (hereinafter referred to as a recess) formed in the substrate (for example, a patent 1st-3rd and 7th embodiment of literature 1, and nonpatent literature 1 and 2 reference).

Here, in Patent Document 1, the inner wall of the recess adjacent to the gate is formed obliquely, the first source / drain region is formed in the gate side portion of the recess, and the second source / drain region deeper than that is formed in the gate. It is formed in the position away from. This first source / drain region is considered to correspond to a so-called extension portion.
In another embodiment of Patent Document 1, for example, in the fourth and fifth embodiments, those in which the first and second source / drain regions are formed in an epitaxial growth layer are disclosed.

On the other hand, FIG. 11C is a schematic diagram showing a raised extension structure.
In this structure, a channel inversion layer is formed on the surface of the substrate, an insulating layer is positioned on both sides of the gate, an extension portion is formed by an epitaxial growth layer on the substrate, and the gate side end of this extension portion is opposite to the gate side. A technique is known in which source / drain regions are formed by ion implantation from above an extension portion in a portion separated from the substrate and a substrate surface portion below the portion (see, for example, Non-Patent Document 3).
JP 2000-82813 A JP 2001-144290 A Nishimatsu, et al .: Groove Gate MOSFET, 8th Conf. On Solid State Devices, pp.179-183 (1976) K. Matsuo, et al, High Performance Damascene Gate CMOS FETs with Recessed Channel Formed by Plasma Oxidation and Etching Method (RC-POEM), IEDM 2002 Uchino, et al: A Raised Source / Drain Technology Using In-situ P-doped SiGe and B-doped Si for 0.1μm CMOS ULSIs, IEDM 1997, pp.479-482 (1977)

  According to the technique described in Non-Patent Document 3, the junction depth Xj of the extension portion with respect to the substrate surface is a depth at which impurities in the epitaxial layer diffuse into the substrate surface portion due to the thermal history after epitaxial growth. This is reduced from the junction depth of the extension formed by ion implantation. Even if the junction depth is reduced, the resistance of the extension portion is determined by the thickness and concentration of the epitaxial growth layer. Therefore, by setting them sufficiently large, it is possible to avoid increasing the resistance of the extension portion. On the other hand, in the formation of the extension portion by ion implantation, if the junction depth is reduced, the resistance value increases and it becomes difficult to achieve the required on-current.

  However, the junction depth Xj required as the gate length is shortened in recent years is becoming increasingly smaller. For this reason, even if the method described in Non-Patent Document 3 without using ion implantation is used, it is not sufficient to reduce the junction depth Xj of the extension portion with respect to the substrate surface. In other words, with the technology described in Non-Patent Document 3 alone, it is expected that the miniaturization of the MIS transistor will progress to a situation where the on-current is not sufficient, which is a factor that hinders further miniaturization of the MIS transistor. It is one.

  The problem to be solved by the present invention is that an extension portion having an optimum junction depth cannot be formed as the gate length is shortened.

  An insulated gate field effect transistor according to the present invention includes a region of a semiconductor substrate in which a channel is formed facing a gate electrode through a gate insulating film, and two extension portions formed in contact with the region and spaced apart from each other. A method of manufacturing an insulated gate field effect transistor having two source / drain regions formed further away from the opposite ends of the two extension portions in a direction away from each other, wherein a spacer having a predetermined width is formed on a semiconductor Forming on the substrate; forming the two source / drain regions in the semiconductor substrate by ion implantation of impurities using the spacer as a mask and activation annealing; and retreating both sides in the width direction of the spacer; The edge of the spacer and the edges of the two source / drain regions on both sides in the width direction And two extension portions that are exposed on both sides of the receded spacer in the width direction and grow a semiconductor material by selective epitaxial growth on the semiconductor substrate region including the two source / drain regions, and are separated by the receded spacer. Forming a step.

  The insulated gate field effect transistor according to the present invention includes a region of a semiconductor substrate in which a channel is formed opposite to a gate electrode through a gate insulating film, and two extension portions formed in contact with the region and spaced apart from each other. , An insulated gate field effect transistor having two source / drain regions formed further away from the opposing ends of the two extension portions in directions away from each other, wherein each of the two extension portions is Each of the two source / drain regions is formed by an impurity region having a conductivity type opposite to that of the semiconductor substrate, and is formed by an epitaxially grown layer on the semiconductor substrate. The impurity as the source / drain region Alloy layer to reach the range is formed on each of the two extension portions.

  According to the insulated gate field effect transistor and the manufacturing method thereof according to the present invention, there is an advantage that an extension portion having an optimum junction depth can be formed even if the gate length is extremely short.

  The best mode for carrying out the present invention will be described with reference to the drawings, taking an N-type MIS transistor as an example. Note that a P-type MIS transistor can be manufactured by a method similar to the following description by appropriately reversing the conductivity type.

[First Embodiment]
1A to 4D are cross-sectional views in the channel direction of a MIS transistor manufactured by applying the method according to the first embodiment.
First, the basic structure of the completed MIS transistor will be described with reference to FIG.

In the illustrated MIS transistor, an element isolation insulating layer, for example, STI (Shallow Trench Isolation) 2 is formed on the surface portion of a substrate 1 made of, for example, a silicon wafer. A P-type region in which a channel inversion layer is formed, for example, a P well 3 is formed in a region (active region) where the STI 2 is not formed.
A stacked body (gate stack) 7 including the gate insulating film 4 and the gate electrode 5 is formed on the P well 3, and the side surface thereof is covered with the partition insulating film 11 and the sidewall insulating film 13. The extension portion 12 is formed on the P well 3 by epitaxial growth in which the formation position is determined in the partition insulating film 11. Further, silicide layers 14A and 14B as alloy layers are formed on the extension portion 12 and the gate electrode 5 by a salicide (Self-aligned silicide) process in which the formation position is determined by the sidewall insulating film 13, respectively. N-type source / drain regions 10 are formed on the surface portion of the P well 3 in contact with the lower surface of the extension portion 12. The entire surface of the transistor is covered with an interlayer insulating film 15, and a connection layer 16 in contact with the silicide layer 14 </ b> A is formed in the interlayer insulating film 15.
In FIG. 4D, the above structure is formed symmetrically in the channel direction with the gate as the center, and one side functions as a source and the other side functions as a drain depending on bias application conditions.

  In the present embodiment, the horizontal position of the gate side end of the source / drain region 10 is preferably positioned between the gate side end of the extension portion 12 and the gate side end of the silicide layer 14A thereon, This position is optimized from the standpoint of reducing the source resistance or drain resistance, and further the leakage between the source and drain. Further, an inclined end surface is provided at the gate side end of the extension portion 12, and the inclined end surface is covered with the sidewall insulating film 13, thereby reducing the parasitic capacitance between the gate and the source or between the gate and the drain.

  The extension portion 12 is a layer that supplies current to a portion (effective channel region) immediately below the gate of the P well 3. Without the extension portion 12, the source / drain region 10 must be brought close to the effective channel region. In this case, the electric field is concentrated particularly on the drain side, the short channel effect becomes remarkable, and the leakage current increases. In addition, when the depletion layer extends greatly in the channel current path and carriers are depleted, the channel resistance increases at that part, and when the channel traveling carrier reaches the saturation speed at that part, the on-current value is limited thereby. The

  In the present embodiment, the existence of the extension portion 12 allows the source / drain region 10 to be separated from the effective channel region. The extension portion 12 is an epitaxial layer into which an N-type impurity is introduced, and has a so-called lifting extension structure. The extension portion 12 has a lower concentration than the source / drain region 10 here, but may have an N-type impurity concentration equal to or higher than that of the source / drain region 10 in order to reduce the resistance value.

Although details will be described later, when the extension portion is formed by ion implantation, the concentration distribution in the depth direction is narrowed, and it is difficult to form a steep PN junction at the boundary with the substrate.
In contrast, in the present embodiment, a steep PN junction is formed at the interface between the extension portion 12 and the substrate (P well 3), for example, by introducing impurities during the epitaxial growth (In-suit doping). The extension of the depletion layer from the portion 12 is suppressed.
Further, since the extension portion 12 is lifted above the substrate surface, the PN junction depth from the well surface can be reduced without increasing the series resistance of the extension portion 12 when operating bias is applied. The influence of the depletion layer extending from the extension portion 12 on the effective channel region and electric field concentration can be suppressed.

  As a result, in this embodiment, the short channel effect is suppressed, and an increase in leakage current and a local increase in channel resistance are prevented.

Note that the N-type impurity in the extension portion 12 is diffused into the P well 3 to some extent by heating during the epitaxial growth and subsequent thermal history.
However, in the present embodiment, this thermal diffusion is suppressed to the minimum necessary by applying a manufacturing method described later. Thereby, although not appearing in FIG. 4D, the depth of the thermal diffusion portion of the extension portion 12 is several nm and about 10 nm at the maximum. Further, although depending on the width of the partition insulating film 11, the width is reduced to, for example, 2 nm, and a part of the thermal diffusion portion overlaps the gate electrode 5 due to thermal diffusion in the lateral direction from the extension portion 12. It is desirable. In this embodiment, since the amount of thermal diffusion is relatively small, the overlap width is also controlled to the minimum necessary.
In this overlap portion, a carrier accumulation layer is formed by an electric field generated by the gate electrode 5 particularly on the source side, thereby reducing the resistance. For this reason, the presence of the overlap portion itself is preferable. However, if the overlap amount is too large, the gate parasitic capacitance is increased and the operation speed of the logic gate is lowered. In addition, the influence (depletion of carriers) of the depletion layer extending from the overlap portion increases, and the short channel effect increases as the effective channel length decreases. For this reason, there is a trade-off in the overlap amount. However, in the conventional structure, the width of the overlap portion is excessively large, which often leads to deterioration in characteristics.
In the present embodiment, the amount of overlap can be controlled by the film thickness of the partition insulating film 11, so that optimization is easy and characteristic deterioration does not occur.

In the present embodiment, as will be described later, the source / drain region 10 is formed before the extension portion 12, and the thermal annealing from the extension portion 12 does not occur excessively by the activation annealing.
For this reason, impurities in the source / drain region 10 exist only up to the vicinity of the boundary with the extension portion 12, and the concentration on the surface side of the extension portion 12 immediately after growth is lower than the concentration in the source / drain region 10. There is. When the connection layer 16 is brought into direct contact with the extension portion 12 having such a low concentration, the contact resistance increases.
Therefore, although the silicide layer 14A is provided, in this embodiment, the silicide layer 14A penetrates the epitaxial growth layer in the thickness direction and reaches the high-concentration source / drain region 10, thereby providing good contact. It has been realized. On the other hand, when the silicide layer 14A reaches too deep, junction leakage of the source / drain region 10 increases.
The depth control of the silicide layer 14A greatly depends on the alloy material and the conditions at the time of alloying, but also depends on the thickness of the extension portion 12. The thickness and concentration distribution of the extension portion 12 are determined in consideration of this viewpoint, the viewpoint of reducing the series resistance of the source or drain, and the inclined end face shape (particularly inclination).

Next, a method for manufacturing the MIS transistor in the present embodiment will be described with reference to the drawings.
In the CMOS process, a P-type MIS transistor is formed in another portion (not shown) of the substrate. In the following, for simplicity of description, the procedure of the N-type MIS transistor is extracted and described. However, in the CMOS process, the same process as described below is repeated each time when necessary, so that the N-type MIS transistor is repeated. A transistor and a P-type MIS transistor are formed on the same substrate.

First, as shown in FIG. 1A, an STI 2 for element isolation is formed on a substrate 1 using a known method.
Next, the substrate 1 is thermally oxidized to form, for example, an 8 nm oxide film (not shown) on the surface. Subsequently, a resist (not shown) having a pattern that exposes the substrate portion where the STI 2 serving as the active region of the transistor is not formed is formed. Thereafter, when ion implantation is performed and the activation annealing is performed after removing the resist, a P well 3 is formed as shown in FIG. The ion species for ion implantation for forming the P well is, for example, boron B. The conditions for the activation annealing are, for example, 1010 ° C. and 10 seconds in the RTA (Rapid Thermal Anneal) method.
Note that channel implantation for adjusting the threshold voltage may be performed before or after the formation of the P well. In the case of a CMOS process, an N well (not shown) may be formed in the same procedure before and after the P well formation (and its channel implantation). In this case, the impurity of the N well is, for example, phosphorus P. In this case, the activation annealing may be performed collectively after forming the P well and the N well.

As shown in FIG. 1C, a gate insulating film 4 and a gate layer 5a are sequentially formed on the substrate surface. The gate insulating film 4 is formed by thermal oxidation, and the thickness thereof is, for example, 1 to 3 nm. The gate insulating film 4 may be modified to an oxynitride film by exposure to nitrogen plasma after oxidation.
The gate layer 5a is a polysilicon layer deposited by, for example, a thermal CVD method, and has a thickness of 100 to 150 nm.
Subsequently, as shown in the figure, impurities are introduced into the gate layer 5a by ion implantation, and then activation annealing is performed to activate the impurities implanted into the gate layer 5a. The impurity introduced into the gate layer 5a is, for example, phosphorus P.

As shown in FIG. 1D, a hard mask layer 6a is stacked on the gate layer 5a. The hard mask layer 6a is, for example, a two- layer film in which a 30 nm SiO 2 film and a 30 nm SiN film are sequentially deposited, and the film formation is performed by a thermal CVD method.

A resist (not shown) is deposited on the hard mask layer 6a, and a gate pattern is formed on the resist by optical lithography, electron beam lithography, or a combination thereof. Next, the patterned resist is isotropically thinned with oxygen plasma to obtain a desired pattern dimension, and then reactive ion etching (RIE) is performed to transfer the resist pattern to the hard mask layer 6a. 6 is formed. Subsequently, the gate layer 5a is patterned by RIE using the hard mask 6 as a mask.
When the resist is removed, as shown in FIG. 2A, a gate stack 7 including a gate insulating film 4, a gate electrode 5 including a gate layer 5a, and a hard mask 6 is formed on the substrate. . In FIG. 2A, the gate insulating film 4 is etched off in the region around the gate stack 7, but the etching conditions are determined so that the gate insulating film 4 remains in this region during the RIE of the gate layer 5a. It is preferable.

  As shown in FIG. 2B, an insulating film 8 with good coverage is deposited, and the gate stack 7 is completely covered with the insulating film 8. As the insulating film 8, for example, a SiN film formed by a thermal CVD method can be selected.

By etching back the insulating film 8 by RIE, side wall insulating films 9 are formed on both sides of the gate stack 7 as shown in FIG. As shown in the figure, the periphery of the gate electrode 5 is covered with the insulating film by the sidewall insulating film 9, the gate insulating film 4 and the hard mask 6.
Since the structure including the gate stack 7 and the side wall insulating film 9 defines the distance D1 (see FIG. 3B) between the two source / drain regions 10 to be formed next, the “spacer” in the present invention. This is a specific example. This embodiment differs from some other embodiments (described later) in that the gate electrode 5 is embedded from the beginning in this spacer.
The width of the sidewall insulating film 9 has an optimum value due to the relationship between the gate length (the width of the gate stack 7) and the junction depth Xj1 (see FIG. 3A) of the source / drain region 10 formed in the next step. It is decided. For example, when the gate length is 20 nm and the junction depth Xj1 of the source / drain region 10 is 150 nm, the width of the bottom surface of the sidewall insulating film 9 is preferably about 70 nm.

After covering the P-type MIS transistor side with a resist (not shown), ion implantation is performed using the gate stack 7 and the sidewall insulating film 9 as a mask as shown in FIG. The introduction region 10 a is formed in the P well 3. The impurity is, for example, phosphorus P. In this case, for example, a condition in which the ion implantation dose is 5 × 10 15 / cm 2 and the implantation energy is 5 keV can be selected.

  After removing the resist, activation annealing is performed to activate the impurities introduced into the P well 3 in the step shown in FIG. The activation annealing is performed by spike annealing with a peak temperature of 1050 ° C., for example. At this time, the distribution slightly changes due to thermal diffusion, and as shown in FIG. 3A, the gate stack 7 and the side wall insulating film 9 are used as spacers and are separated by a distance D1 corresponding to the width (see FIG. 3B). The two source / drain regions 10 having junction depths Xj1 are formed in the P well 3.

The substrate 1 is immersed in heated phosphoric acid, and the sidewall insulating film 9 and the SiN film constituting the hard mask 6 are etched and removed. Since the hard mask 6 is composed of the lower SiO 2 film and the upper SiN film, in the gate stack 7 after this etching, as shown in FIG. Two films 6b) are left on the gate electrode 5. Further, the side surface of the gate electrode 5 is exposed after the etching.

  The insulating film is deposited and etched back in the same procedure as in FIGS. 2B and 2C, and the partition insulating film 11 is formed on both sides of the gate stack 7 as shown in FIG. 3C. The partition insulating film 11 is made of an insulating material such as SiN having a higher etching selectivity than the side wall insulating film 13 (see FIG. 4C), which is an additional spacer to be added before silicide formation described later. If the anisotropy is increased by the etch back at this time, the width of the partition insulating film 11 is substantially determined by the SiN film thickness immediately after deposition. For this reason, the controllability of the isolation width between the gate electrode 5 and the extension portion 12 to be formed next is improved, and as a result, the overlap width between the extension portion 12 and the gate electrode 5 can be easily optimized.

The step shown in FIG. 3C and the previous step shown in FIG. 3B correspond to the step of retracting the edge of the spacer formed in FIG. 3A in the width direction.
The method for retracting the spacer is not limited to the illustrated method, but once the sidewall portion of the spacer is removed and a new thin film is formed as described above, the control of the receding width is good and the material of the sidewall portion is changed. It is preferable in the sense that it can be.

After cleaning the surfaces of the semiconductor layer and insulating layer formed on the substrate 1, the extension portion 12 is epitaxially grown at a temperature of 800 ° C. or lower. The material of the epitaxial growth layer is a single crystal of Si or a mixed crystal of silicon Si and germanium Ge, carbon C, or both.
As shown in FIG. 3D, the epitaxial growth layer grows from the exposed semiconductor layer, that is, the P well 3 in which the source / drain regions 10 are formed, but is protected by the SiO 2 film 6 b and the partition insulating film 11. Thus, no growth occurs from the gate electrode 5. The partition insulating film 11 functions as a partition between the epitaxial growth layer (extension portion 12) and the gate electrode 5. Epitaxial growth grows only on one side (semiconductor layer side) at the boundary portion between the insulating film and the semiconductor layer. Therefore, although depending on the crystal structure and conditions of the semiconductor layer, the end portion of the epitaxial growth usually extends upward. It becomes an inclined inclined end surface away from
Impurities are introduced into the extension portion 12 by supplying an impurity-containing gas during epitaxial growth. The impurities are, for example, arsenic As or phosphorus P.

By depositing an insulating film on the substrate 1 and etching it back by RIE, sidewall insulating films 13 as additional spacers are formed on both sides of the gate stack 7 as shown in FIG. The sidewall insulating film 13 is, for example, a SiO 2 film formed by a thermal CVD method using TEOS as a source gas, and the film thickness considers gate sidewall capacitance (parasitic capacitance between source and gate or drain and gate). For example, it is arbitrarily selected between 10 and 60 nm.

As shown in FIG. 4B, a resist (not shown) is applied to the substrate 1, and the resist is etched back to expose only the uppermost portion of the gate stack 7, and then reactive ion etching is performed. The SiO 2 film 6b left on the uppermost layer of the gate stack 7 is removed.

As shown in FIG. 4C, a silicide layer 14A and a silicide layer 14B are simultaneously formed on the extension portion 12 and the gate electrode 5, respectively. Silicide layers 14A and 14B are, for example, CoSi 2 or NiSi 2 . This silicide layer is formed by forming a cobalt Co or nickel Ni metal film and then heat-treating it, alloying the part that contacts the semiconductor material, and removing the non-alloyed part (part contacting the insulating material) by chemical treatment. To do. Of these, the silicide layer 14 </ b> A is in direct contact with the source / drain region 10.

As shown in FIG. 4D, the connection layer 16 is formed on the silicide layer 14A. More specifically, the interlayer insulating film 15 is deposited, the surface thereof is planarized by chemical mechanical polishing (CMP), and a resist (not shown) having a pattern opening above the silicide layer 14A is formed by lithography. Form on top. A connection hole reaching the silicide layer 14A is formed by RIE using this resist as a mask, and after removing the resist, the connection hole is filled with metal and planarized to form the connection layer 16 as shown.
Thereafter, although not particularly shown, wiring is formed on the connection layer 16. In addition, the connection with the upper layer wiring with respect to the silicide layer 14B on the gate electrode 5 is similarly achieved by using the connection layer in a portion not shown.

[Second Embodiment]
The present embodiment relates to a structure of a MIS transistor in which a gate electrode is partially overlapped with an inclined inclined end face of an extension portion with high accuracy, and a method for forming the same.
FIG. 5A to FIG. 6D are cross-sectional views in the channel direction of the MIS transistor manufactured by applying the method in the second embodiment.
First, the basic structure of the completed MIS transistor will be described with reference to FIG.

  The illustrated MIS transistor is different from the MIS transistor in the first embodiment (see FIG. 4D) in that the gate electrode 19 is partially connected to the obliquely inclined end surface of the extension portion 12 via the gate insulating film 17. , The silicide layer is not formed on the upper portion of the gate electrode 19, and the partition insulating film 11 (see FIG. 4D) is not formed on both side surfaces of the gate electrode 19. It is. Since other configurations are common, description is omitted here. In the following description, the same material and configuration as those in the first embodiment are denoted by the same reference numerals, and the description will be simplified.

In manufacturing the MIS transistor, the steps up to the step shown in FIG. 4A are the same as those described in the first embodiment.
In this embodiment, a silicide layer is formed without removing the uppermost SiO 2 film 6b of the gate stack 7 shown in FIG. As a result, as shown in FIG. 5A, the silicide layer 14A is formed on the extension portion 12, and the silicide layer is not formed on the gate electrode 5.

An interlayer insulating film 15 is deposited and the surface thereof is planarized by etching and polishing until the SiO 2 film 6b is exposed by CMP. FIG. 5B shows a cross section of the element after the planarization. The interlayer insulating film 15 is a SiO 2 film formed by plasma CVD.

The SiO 2 film 6b exposed on the surface of the sidewall insulating film 13 and the underlying gate electrode 5 are removed by etching. More specifically, the SiO 2 film 6b of the gate stack 7 is removed by etching using a solution containing hydrofluoric acid, and wet etching with an alkaline solution such as a TMAH (tetramethylammonium hydroxide) aqueous solution, or silane CF 4 and The gate electrode 5 is removed by chemical dry etching using a mixed gas of oxygen O 2 . FIG. 5C shows the gate opening 7a formed by this etching.
Subsequently, the gate insulating film 4 and the partition insulating film (SiN film) 11 in the gate opening 7a are removed by etching using a solution containing hydrofluoric acid, and the surface of the P well 3 is formed on the bottom of the gate opening 7a. To expose. FIG. 5D shows a cross section of the element after this etching. By this etching, part of the sidewall insulating film 13 is also etched, and the inclined end face of the extension portion 12 is exposed at the bottom of the gate opening 7a.

As shown in FIG. 6A, a gate insulating film 17 is formed on the inclined end faces of the P well 3 and the extension portion 12 exposed in the gate opening 7a. The gate insulating film 17 is a SiO 2 film formed by thermal oxidation, a SiON film formed by plasma nitriding the SiO 2 film, or an HfO 2 film formed by an ALD (Atomic Layer Deposition) method.

  As shown in FIG. 6B, the gate metal 18 is formed thick, and the gate opening 7 a is filled with the gate metal 18. The formation of the gate metal 18 can be performed, for example, by PVD of a Cu seed layer and subsequent electroless plating of Cu.

  Excess gate metal 18 is removed by CMP, leaving gate metal 18 only in gate opening 7a. As a result, the gate electrode 19 embedded in the interlayer insulating film 15 and the sidewall insulating film 13 is formed as shown in FIG.

By a method similar to the step shown in FIG. 4D, a connection layer 16 which is in contact with the silicide layer 14A and embedded in the interlayer insulating film 15 is formed as shown in FIG. 6D.
Thereafter, if necessary, upper layer wiring (not shown) and the like are formed to complete the MIS transistor.

  In the MIS transistor having such a structure, a storage layer is formed during operation at the inclined end portion of the extension portion 12 that overlaps the gate electrode 19 through the gate insulating film 17. By this accumulation layer, the channel and the source / drain region 10 are connected with low resistance, and a further increase in on-current is realized.

In the manufacture of the MIS transistor shown in the second embodiment described above, the spacer functioning as the ion implantation mask of the source / drain region 10 is removed, and a new gate insulating film 17 and gate electrode 19 are embedded. Form by process.
Assuming that this embedded gate process is adopted, it is not always necessary to form the spacer with the gate stack 7, that is, the stacked body including the conductive gate electrode 5 as described in the second embodiment. An insulating spacer can be used.

The following third and fourth embodiments show examples using insulating sidewall spacers. Of these, the third embodiment shows the case where the gate electrode is not overlaid on the extension part, and the fourth embodiment shows the case over which the gate electrode is overlaid.
In the following embodiment, as in the second embodiment, only points different from the above will be described for the sake of brevity, and the already-described configuration will be given the same reference numeral and only illustrated.

[Third Embodiment]
7A to 9C are cross-sectional views in the channel direction of the MIS transistor manufactured by applying the method according to the third embodiment.
In manufacturing the MIS transistor, the steps up to the step shown in FIG. 1B are the same as the method described in the first embodiment.

As shown in FIG. 7A, a SiO 2 film 20 as a pad layer is formed in the active region (P well 3) by thermal oxidation or the like. An insulating film having a higher etching selectivity than the pad layer, for example, a SiN film is deposited thereon by CVD, a resist is formed on the SiN film, and this is patterned by lithography. Next, RIE is performed using the patterned resist as a mask, and the resist pattern is transferred to the SiN film.
When the resist is removed, a spacer 21 having a predetermined width is formed on the SiO 2 film 20 as shown. The optimum width of the spacer 21 is determined by the relationship between the gate length and the junction depth Xj1 (see FIG. 7C) of the source / drain region 10 formed in the next step.

  After the P-type MIS transistor side is covered with a resist (not shown), ion implantation is performed using the spacer 21 as a mask as shown in FIG. Form in well 3. As the ion implantation conditions, the same process as that shown in FIG. 2D can be selected.

  After the resist is removed, activation annealing is performed to activate the impurities introduced into the P well 3 in the step shown in FIG. The activation annealing is performed by spike annealing with a peak temperature of 1050 ° C., for example. At this time, the distribution slightly changes due to thermal diffusion, and two source / drain regions 10 each having a depth Xj1 are formed in the P well 3 with a distance D1 corresponding to the width of the spacer 21.

Next, the spacer 21 is thinned by, for example, plasma dry etching, and the edges on both sides in the width direction that define the positions where the source / drain regions 10 are formed are retracted. Subsequently, the SiO 2 film 20 around the spacer 21 is removed by etching using a solution containing hydrofluoric acid. As a result, as shown in FIG. 8A, the stacked body of the SiO 2 film 20 and the spacer 21 is adjusted to a predetermined width as a separation layer during epitaxial growth. In order to accurately control the width, the spacer 21 is previously formed with a double structure of insulating materials having different etching rates, for example, a structure including a central portion and side wall portions formed on both side surfaces thereof. The sidewall portions may be selectively removed after the ion implantation of the source / drain regions 10.
Subsequently, the same material is epitaxially grown by the same method as in FIG. 3D to form two extension portions 12. FIG. 8A shows a cross section of the element after the extension portion is formed.

  A thick insulating film 22 covering the formed extension portion 12 and spacer 21 is deposited, and the surface thereof is planarized by CMP or the like until the upper surface of the spacer 21 is exposed. FIG. 8B shows a cross section of the element after the planarization.

The spacer 21 is removed by etching by immersing the substrate 1 in a solution containing heated phosphoric acid, and then the SiO 2 film 20 on the surface of the substrate is removed by etching using a solution containing hydrofluoric acid. As a result, as shown in FIG. 8C, a gate opening 22a is formed in the insulating film 22, and the substrate surface (the surface of the P well 3) is exposed in the gate opening 22a.

After the exposed well surface is washed, a gate insulating film 17 is formed as shown in FIG.
Subsequently, the gate electrode 19 embedded in the gate opening 22a is formed by the same method as in FIG. 6B in the second embodiment. Note that the gate electrode 19 in the present embodiment does not overlap the extension portion 12.

The gate electrode 19 and the underlying gate insulating film 17 are obtained by replacing the spacer 21 and the SiO 2 film shown in FIG. 8A. Next, the side wall insulating film 13 as an additional spacer is formed as shown in FIG. By the same method as (A), the gate electrode 19 is formed in contact with both side surfaces and covering the inclined end surface of the extension portion 12. FIG. 9C shows an element cross section after the sidewall insulating film 13 is formed.

Thereafter, although not particularly shown, silicide layers are simultaneously formed on the extension portion 12 and the gate electrode 19 by the same method as in FIG. 4C in the first embodiment.
Further, an interlayer insulating film is deposited and a connection layer is formed by a method similar to that shown in FIG. 4D, and then necessary wirings are formed to complete the MIS transistor.

[Fourth Embodiment]
FIG. 10A to FIG. 10C are cross-sectional views in the channel direction of the MIS transistor manufactured by applying the method in the fourth embodiment.
This MIS transistor manufacturing method is a partial modification of the manufacturing method in the third embodiment, and is the same as the method described in the third embodiment up to the step shown in FIG. .

  As shown in FIG. 10A, after the width of the gate opening 22a formed in the insulating film 22 is widened by dry etching, the P well 3 exposed on the bottom surface of the gate opening 22a and the inclined end face of the extension 12 A gate insulating film 17 is formed thereon.

Thereafter, the gate electrode 19 embedded in the gate opening 22a is formed by the same method (FIG. 10B), and the sidewall insulating film 13 is formed (FIG. 10C).
Similarly, an interlayer insulating film is deposited and a connection layer is formed, and then necessary wirings are formed to complete the MIS transistor.
This completes the description of the structure and the manufacturing method.

By the way, in the above-mentioned Non-Patent Document 3, the extension portion is formed by epitaxial growth layer (P-doped SiGe) on the substrate before ion implantation and activation annealing (RTA) for forming a deep source / drain. Is achieved by forming
However, when the source / drain regions are formed after the formation of the epitaxial growth layer as in Non-Patent Document 3, thermal diffusion of impurities from the epitaxial growth layer occurs due to activation annealing of the introduced impurities.

  Further, as in Patent Document 1, when forming a source / drain region (second source / drain region) and an extension portion (first source / drain region) in an epitaxial growth layer, ion implantation and subsequent activation annealing are performed. In this case also, thermal diffusion of impurities occurs.

  Incidentally, on the International Semiconductor Technology Roadmap (ITRS), for example, in the technology node hp32, the physical gate length is expected to be 13 nm (in this case, the effective gate length is around 10 nm).

The present inventor conducted a simulation for such an ultrafine gate transistor when devising the present invention. As a result, the allowable junction depth of the extension portion 12 with an effective gate length of about 10 nm is several nm. The knowledge that it is about 10 nm was acquired.
Further, it has been found that the above-described thermal diffusion of impurities in the extension portion does not become a problem when the gate length is large, but becomes a serious problem when the effective gate length is reduced to about 10 nm. That is, in an MIS transistor having an effective gate length of about 10 nm, a sharp PN junction having an impurity concentration higher than the electron concentration of the inversion layer is formed between the substrate and the extension portion due to the thermal diffusion of the impurity in the extension portion. It was difficult to form and it was concluded that this had a decisive influence on device characteristics.

The discussion that led to this conclusion is described below.
First, the impurity distribution by ion implantation is a Gaussian distribution even in an ideal case, and usually causes a tail by channeling. Therefore, it is difficult to obtain a steep profile on the scale of several nm.
Next, when the temperature is set, for example, around 1000 ° C. so that a sufficient activation rate can be obtained by the subsequent activation annealing, redistribution of impurities occurs. At this time, the higher the concentration, the larger the inclination of the profile.

  If a steep PN junction cannot be achieved, the top and bottom of the PN junction surface between the extension portion and the substrate are widely depleted in a situation where no bias is applied. In the depleted region, an accumulation layer having a sufficiently high concentration is not formed when a gate bias is applied, so that the parasitic resistance of the overlap region between the extension portion and the gate cannot be sufficiently lowered. Therefore, it is substantially equivalent to an increase in the gate length, and a high on-current cannot be obtained.

Furthermore, even when impurities are introduced into the extension portion sharply at a sufficiently high concentration, redistribution of impurities occurs in the subsequent activation annealing of the source / drain regions, and the impurities in the extension portion and the substrate diffuse to each other. It is difficult to maintain a high concentration and steep PN junction with the substrate and obtain a high on-current.
For these reasons, depending on the background art, it is difficult to form an extremely shallow extension portion 12 having a junction depth of about several nanometers to 10 nm from the substrate surface where the channel is formed.

  In contrast, in the MIS transistor manufacturing method according to the present embodiment, after forming gate stack 7 and sidewall insulating film 9 (or insulating spacer 21) as spacers, deep source / drain regions 10 are ionized using these as masks. The extension portion 12 is formed by implantation and activation annealing, and then selectively epitaxially grown while doping impurities.

In this manufacturing method, in the formation of the extension portion 12, by doping impurities during epitaxial growth, a high concentration and steep PN junction that cannot be obtained by ion implantation is formed between the substrate (P well 3) and the extension portion 12. It can be formed.
Further, by performing the high-temperature activation annealing for forming the deep source / drain regions 10 before the extension portion 12 is formed, the redistribution of impurities at the boundary between the extension portion 12 and the substrate can be suppressed mutually. It is possible to maintain a steep impurity profile.
The short channel effect is suppressed by reducing the diffusion depth of the extension portion 12. At the same time, since the PN junction between the substrate and the extension portion 12 is highly concentrated and steep, the depletion of the extension portion 12 is suppressed, and the effective increase in the gate length due to the resistance of the depleted region is prevented. , Thereby reducing the decrease in on-current.

  The present invention can be widely applied to semiconductor products having MIS type field effect transistors and their manufacture.

(A)-(D) is sectional drawing of the channel direction of the MIS transistor manufactured by applying the method in 1st Embodiment, and shows even formation of a hard mask layer. It is the same sectional view following FIG. 1 (D), and shows to ion implantation for forming a source / drain region. It is the same sectional view following Drawing 2 (D), and shows to formation of an extension part. It is the same sectional view following Drawing 3 (D), and shows to formation of a connection layer. (A)-(D) are sectional drawings of the channel direction of the MIS transistor manufactured by applying the method in the second embodiment, and show the process up to the formation of the gate opening. It is the same sectional view following Drawing 5 (D), and shows to formation of a connection layer. (A)-(C) are sectional drawings of the channel direction of the MIS transistor manufactured by applying the method in the third embodiment, and show the process up to the formation of the source / drain regions. FIG. 8 is a cross-sectional view subsequent to FIG. 7D, showing the formation of the gate opening. FIG. 9D is a cross-sectional view subsequent to FIG. (A)-(C) are sectional drawings of the channel direction of the MIS transistor manufactured by applying the method in the fourth embodiment, and show up to the formation of the sidewall insulating film. (A) is a schematic diagram of a cross-sectional structure of a conventional planar MOSFET. (B) is a schematic diagram of a structure called “groove gate” or “recess gate”. (C) is a schematic diagram showing a lifting extension structure.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Substrate, 3 ... P well, 4 ... Gate insulating film, 5 ... Gate electrode, 7 ... Gate stack, 10 ... Source / drain region, 11 ... Partition insulating film, 12 ... Extension part, 13 ... Side wall insulating film, 14A , 14B ... Silicide layer, 17 ... Gate insulating film, 19 ... Gate electrode

Claims (9)

  1. A region of the semiconductor substrate that is opposed to the gate electrode through the gate insulating film and in which a channel is formed, two extension portions that are in contact with the region and are spaced apart from each other, and an opposite end of the two extension portions from each other A method of manufacturing an insulated gate field effect transistor having two source / drain regions formed further apart in a separating direction,
    Forming a spacer having a predetermined width on a semiconductor substrate;
    Forming the two source / drain regions in the semiconductor substrate by ion implantation of impurities using the spacer as a mask and activation annealing;
    Retreating both sides in the width direction of the spacer, and separating the edge of the spacer and the edges of the two source / drain regions on both sides in the width direction;
    A step of growing a semiconductor material by selective epitaxial growth on a semiconductor substrate region including the two source / drain regions exposed on both sides in the width direction of the receded spacer, and forming two extension portions separated by the receded spacer; When,
    A method of manufacturing an insulated gate field effect transistor comprising:
  2. Forming additional spacers on both sides of the retracted spacer in the width direction, and increasing the width of the entire spacer;
    Forming two alloy layers connected to the source / drain regions in the depth direction in each of the two extension portions by forming a metal film and heat-treating the entire spacer including the additional spacer as a separation layer. When,
    The method for producing an insulated gate field effect transistor according to claim 1, further comprising:
  3. The insulated gate field effect according to claim 1, wherein an impurity having a conductivity type opposite to that of a region of the semiconductor substrate in which the channel is formed is introduced into the growing layer during the epitaxial growth for forming the two extension portions. A method for manufacturing a transistor.
  4. 2. The insulated gate according to claim 1, wherein a stacked body of the gate insulating film and the gate electrode is formed, and the periphery of the stacked body is covered with an insulating film and used as the spacer having the predetermined width when the source / drain regions are formed. A method of manufacturing a field effect transistor.
  5. Forming an interlayer insulating film covering the extension part on the side surface side of the spacer, and selectively removing the spacer from the surface of the interlayer insulating film;
    Forming the gate insulating film in a region of the semiconductor substrate exposed at a location where the spacer is removed, and embedding the gate electrode in a space on the gate insulating film at the location where the spacer is removed;
    The method for producing an insulated gate field effect transistor according to claim 1, further comprising:
  6. Expanding the width-removed portion of the spacer in the width direction and further exposing a part of the inclined end surface of the extension portion formed during the epitaxial growth;
    The gate insulating film is formed on the exposed inclined end face and the surface of the semiconductor substrate, and the space above the gate insulating film is filled with a gate electrode, whereby a part of the gate electrode is overlapped with the inclined end face of the extension portion. Item 6. A method for manufacturing an insulated gate field effect transistor according to Item 5.
  7. A region of the semiconductor substrate that is opposed to the gate electrode through the gate insulating film and in which a channel is formed, two extension portions that are in contact with the region and are spaced apart from each other, and an opposite end of the two extension portions from each other An insulated gate field effect transistor having two source / drain regions formed further apart in a separating direction,
    Each of the two extension portions is formed by an epitaxial growth layer on the semiconductor substrate,
    Each of the two source / drain regions is formed of an impurity region having a conductivity type opposite to that of the semiconductor substrate, which is in contact with the lower surface of the epitaxial growth layer,
    An insulated gate field effect transistor, wherein an alloy layer that penetrates the epitaxial growth layer in the thickness direction and reaches the impurity region as the source / drain region is formed in each of the two extension portions.
  8. The insulated gate according to claim 7, wherein a distance from a gate side end of the epitaxial growth layer to a gate side end of the alloy layer is determined by a width of a side wall spacer in contact with a side surface side of the gate electrode on the epitaxial growth layer. Field effect transistor.
  9. The gate side end portion of the epitaxial growth layer is provided with an inclined end surface that is farther from the gate electrode toward the upper side, and the gate electrode partially overlaps the inclined end surface via the gate insulating film. 8. The insulated gate field effect transistor according to 7.
JP2005001609A 2005-01-06 2005-01-06 Method for manufacturing insulated gate field effect transistor Expired - Fee Related JP5007488B2 (en)

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JP2007142036A (en) * 2005-11-16 2007-06-07 Sony Corp Semiconductor device and manufacturing method thereof
JP2008066548A (en) * 2006-09-08 2008-03-21 Sony Corp Semiconductor device and manufacturing method of semiconductor device

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JPH0786579A (en) * 1993-09-14 1995-03-31 Toshiba Corp Semiconductor device
JPH07131007A (en) * 1993-11-02 1995-05-19 Tadahiro Omi Semiconductor device
JPH08298328A (en) * 1995-04-27 1996-11-12 Hitachi Device Eng Co Ltd Semiconductor device and its manufacture
JP2000223709A (en) * 1999-02-04 2000-08-11 Toshiba Corp Semiconductor device and its manufacture
JP2000269495A (en) * 1999-03-18 2000-09-29 Toshiba Corp Semiconductor device and its manufacture
JP2004031753A (en) * 2002-06-27 2004-01-29 Renesas Technology Corp Manufacturing method of semiconductor device

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JPH0677246A (en) * 1990-10-12 1994-03-18 Texas Instr Inc <Ti> Transistor and manufacturing method therefor
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JP2007142036A (en) * 2005-11-16 2007-06-07 Sony Corp Semiconductor device and manufacturing method thereof
JP4706450B2 (en) * 2005-11-16 2011-06-22 ソニー株式会社 Semiconductor device and manufacturing method thereof
JP2008066548A (en) * 2006-09-08 2008-03-21 Sony Corp Semiconductor device and manufacturing method of semiconductor device

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