JP2006066757A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can simplify a manufacturing process when a gate electrode is formed, while suppressing depletion of the gate electrode. <P>SOLUTION: The semiconductor device includes a pair of n-type source/drain regions 6a, a gate electrode 8a formed on a channel region 5a with a gate insulating film 7a disposed therebetween, a pair of p-type source/drain regions 6b, and a gate electrode 8b formed on a channel region 5b with a gate insulating film 7b disposed therebetween. The gate electrode 8a includes a TaN layer 9a formed on the gate insulating film 7a, and a polysilicon layer 10a formed on the TaN layer 9a. The gate electrode 8b includes a TaN layer 9b formed on the gate insulating film 7b, and a polysilicon layer 10b formed on the TaN layer 9b. The TaN layers 9a and 9b form an identical layer. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a first conductivity type source / drain region and a second conductivity type source / drain region.

  Conventionally, it has an n-channel MOS transistor having an n-type source / drain region and a gate electrode made of an n-type polysilicon layer, and a gate electrode made of a p-type source / drain region and a p-type polysilicon layer. A dual gate CMOS (Complementary Metal Oxide Semiconductor) composed of a p-channel MOS transistor is known. In this conventional dual gate CMOS, the gate electrodes of the n-channel MOS transistor and the p-channel MOS transistor are formed of the polysilicon layer, so that the gate electrode is depleted. Therefore, a dual gate CMOS capable of solving the problem of depletion of the gate electrode has been proposed (for example, see Patent Document 1).

In the dual gate CMOS proposed in Patent Document 1, the gate electrode of the n-channel MOS transistor and the p-channel MOS transistor is formed of a metal layer, thereby depleting the gate electrode made of semiconductor (polysilicon). It has been resolved. Further, in the dual gate CMOS proposed in the above-mentioned Patent Document 1, in order to set the Fermi level of the gate electrodes of the n-channel MOS transistor and the p-channel MOS transistor to appropriate energy levels, the n-channel MOS transistor and the p-channel MOS transistor are used. The gate electrodes of the channel MOS transistors are each formed by a different kind of metal layer having an appropriate work function.
JP 2004-165346 A

  However, in the dual gate CMOS proposed in Patent Document 1, the gate electrodes of the n-channel MOS transistor and the p-channel MOS transistor are formed by different types of metal layers, respectively. And the gate electrode of the p-channel MOS transistor must be formed separately. As a result, there is a problem in that the manufacturing process for forming the gate electrode is complicated.

  The present invention has been made to solve the above-described problems, and one object of the present invention is to simplify a manufacturing process when forming a gate electrode while suppressing depletion of the gate electrode. It is an object of the present invention to provide a semiconductor device that can be used.

Means for Solving the Problems and Effects of the Invention

  In order to achieve the above object, a semiconductor device according to one aspect of the present invention includes a pair of first conductivity type first electrodes formed at a predetermined interval so as to sandwich a first channel region on a main surface of a semiconductor region. One source / drain region, a first gate electrode formed on the first channel region via a first gate insulating layer, and a predetermined interval so as to sandwich the second channel region on the main surface of the semiconductor region A pair of second source / drain regions of the second conductivity type formed, and a second gate electrode formed on the second channel region with a second gate insulating layer interposed therebetween. A first metal layer formed on the first gate insulating layer; a first semiconductor layer formed on the first metal layer; and a second gate electrode formed on the second gate insulating layer. Metal layer and second semiconductor layer formed on second metal layer Wherein the first metal layer and the second metal layer is composed of the same layer. In addition, the 1st metal layer and 2nd metal layer of this invention are a wide concept including not only the layer which consists of a metal simple substance but the layer which consists of a metal compound.

  In the semiconductor device according to this aspect, as described above, the first metal layer in which the first gate electrode is formed on the first gate insulating layer and the first semiconductor layer formed on the first metal layer are provided. And the second gate electrode includes a second metal layer formed on the second gate insulating layer and a second semiconductor layer formed on the second metal layer. Unlike the case where the first and second gate electrodes are configured only by the semiconductor layer formed on the gate insulating layer, depletion of the first and second gate electrodes can be suppressed. In addition, by configuring the first metal layer of the first gate electrode and the second metal layer of the second gate electrode to be made of the same layer, the first metal layer and the second metal layer are patterned by the same layer. Since it can form simultaneously, the manufacturing process at the time of forming a 1st and 2nd metal layer can be simplified. Thereby, the manufacturing process at the time of forming the 1st gate electrode containing a 1st metal layer and the 2nd gate electrode containing a 2nd metal layer can be simplified. The stacked metal layer and the semiconductor layer are processed (patterned) in the same etching step, whereby the first gate electrode including the first metal layer and the first semiconductor layer, the first metal layer, and the first semiconductor are formed. It is also possible to form the second gate electrode made of layers simultaneously. The first gate electrode includes a first metal layer and a first semiconductor layer formed on the first metal layer, and the second gate electrode includes a second metal layer and a second metal layer. By including the second semiconductor layer formed on the metal layer, the metal layer (first layer) can be formed as compared with the case where the gate electrode having the same thickness as the first and second gate electrodes is formed only by the metal layer. The thickness of the first metal layer and the second metal layer can be reduced. This facilitates processing (patterning) by etching the metal layer, so that the gate electrode can be easily patterned even when the gate electrode including the metal layer is used. In addition, since the thickness of the metal layer can be reduced as compared with the case where the gate electrode having the same thickness as the first and second gate electrodes is formed only by the metal layer, the metal layer, the gate insulating layer, and the semiconductor region It is possible to reduce the stress caused by the difference in the thermal expansion coefficient. Thereby, compared with the case where the gate electrode having the same thickness as the first and second gate electrodes is formed only by the metal layer, the electron mobility caused by the stress acting between the metal layer, the gate insulating layer, and the semiconductor region. Can be reduced.

  In the semiconductor device according to the aforementioned aspect, the first metal layer and the second metal layer preferably have an average film thickness smaller than the film thickness of the first semiconductor layer and the second semiconductor layer. With this configuration, the metal layer can be easily processed (patterned) by etching, so that the gate electrode can be easily patterned. In addition, since the first and second metal layers are configured to have an average film thickness smaller than the film thickness of the first and second semiconductor layers, the thickness of the metal layer can be easily reduced. It is possible to easily reduce the deterioration of electron mobility due to the stress acting between the metal layer, the gate insulating layer, and the semiconductor region.

  In this case, preferably, the first metal layer and the second metal layer have an average film thickness of less than 2.5 nm. If comprised in this way, the film thickness of a 1st and 2nd metal layer can be made small easily. Further, if the first metal layer and the second metal layer are formed so as to have an average film thickness of less than 2.5 nm, the first metal layer and the second metal layer can be easily aggregated in the heat treatment step. Therefore, the first metal layer and the second metal layer can be easily formed in a dot shape.

  In the semiconductor device according to the aforementioned aspect, the first metal layer and the second metal layer are preferably formed so as to partially cover the first gate insulating layer and the second gate insulating layer, respectively. The semiconductor layer and the second semiconductor layer are in contact with a portion of the first gate insulating layer that is not covered with the first metal layer and a portion of the second gate insulating layer that is not covered with the second metal layer, respectively. Is formed. With this configuration, the contact area between the first and second metal layers and the gate insulating layer can be reduced, and accordingly, the interface reaction between the first and second metal layers and the gate insulating layer is caused. The Fermi level pinning of the metal layer is less likely to occur. As a result, it is possible to suppress the difficulty in adjusting the work function of the gate electrode due to pinning. Further, the first semiconductor layer and the second semiconductor layer are respectively formed in a portion not covered by the first metal layer of the first gate insulating layer and a portion not covered by the second metal layer of the second gate insulating layer. By forming so as to be in contact with each other, the contact area between the first and second semiconductor layers and the gate insulating layer can be reduced. Accordingly, the first and second semiconductor layers are formed of the material containing silicon, and the gate insulating layer is also formed of the high-k material containing metal, which is included in the first and second semiconductor layers. Since pinning due to the reaction between silicon and the metal contained in the high-k material of the gate insulating layer is less likely to occur, it is difficult to adjust the work function of the gate electrode due to pinning in this case as well. Can be suppressed.

  In this case, preferably, the first metal layer and the second metal layer are formed in a dot shape. If comprised in this way, since a 1st metal layer and a 2nd metal layer can be easily formed in a discontinuous layer, it becomes difficult to adjust the work function of a gate electrode easily. Can be suppressed. In this case, the work function of the gate electrode can be easily adjusted by doping the first and second semiconductor layers in contact with the gate insulating layer with impurities of a predetermined conductivity type.

  The first metal layer and the second metal layer are formed to partially cover the first gate insulating layer and the second gate insulating layer, respectively, and the first semiconductor layer and the second semiconductor layer are respectively The first gate insulating layer is formed so as to be in contact with a portion of the first gate insulating layer that is not covered with the first metal layer and a portion of the second gate insulating layer that is not covered with the second metal layer. The second gate insulating layer may be made of a high dielectric constant insulating film having a relative dielectric constant greater than 3.9. Thus, when the first and second gate insulating layers are made of a high dielectric constant insulating film having a relative dielectric constant greater than 3.9, the metal layer of the gate electrode formed on the gate insulating layer Since the Fermi level is easily pinned, the metal layer is formed so as to partially cover the gate insulating layer as in the present invention, and the semiconductor layer is in contact with the portion of the gate insulating layer not covered by the metal layer. If comprised in this way, generation | occurrence | production of pinning can be suppressed easily. This makes it difficult to adjust the work function of the gate electrode even when the first gate insulating layer and the second gate insulating layer are made of a high dielectric constant insulating film having a relative dielectric constant greater than 3.9. Can be suppressed.

  In the semiconductor device according to the above aspect, the first semiconductor layer preferably includes a silicon layer containing a first conductivity type impurity, and the second semiconductor layer includes a silicon layer containing a second conductivity type impurity. Including. If comprised in this way, the 1st gate electrode which has a 1st conductivity type silicon layer and a 1st metal layer, and the depletion containing the 2nd conductivity type silicon layer and a 2nd gate electrode which has a 2nd metal layer It is possible to obtain a dual gate semiconductor device capable of suppressing the above.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, a CMOS as an example of a semiconductor device according to the present invention will be described as an example.

  FIG. 1 is a cross-sectional view illustrating a structure of a CMOS according to an embodiment of the present invention. FIG. 2 is an enlarged cross-sectional view showing the structure of the n-channel MOS transistor portion of the CMOS according to the embodiment shown in FIG. First, the structure of a CMOS according to an embodiment of the present invention will be described with reference to FIGS.

In the CMOS according to the present embodiment, a buried oxide film 2 having a thickness of about 200 nm is formed on a silicon substrate 1 as shown in FIG. In a predetermined region on the buried oxide film 2, a single crystal silicon layer 3 as an SOI (Silicon on Insulator) layer having a thickness of about 100 nm is formed. The single crystal silicon layer 3 is an example of the “semiconductor region” in the present invention. An element isolation insulating film 4 made of an SiO ₂ film reaching the buried oxide film 2 is formed so as to surround the single crystal silicon layer 3.

Further, in the formation region of the n-channel MOS transistor 50a constituting the CMOS according to the present embodiment, the single crystal silicon layer 3 has a pair of n-type sources spaced apart from each other by a predetermined distance so as to sandwich the p-type channel region 5a. / Drain region 6a is formed. The p-type channel region 5a is an example of the “first channel region” in the present invention, and the n-type source / drain region 6a is an example of the “first source / drain region” in the present invention. . A gate insulating film 7a is formed on the p-type channel region 5a. The gate insulating film 7a is an example of the “first gate insulating layer” in the present invention. The gate insulating film 7a is formed of an SiO ₂ film or an HfO ₂ film that is a high dielectric constant (High-k) insulating film. This HfO ₂ film has a relative dielectric constant higher than 3.9. When the gate insulating film 7a is made of an SiO ₂ film, the SiO ₂ film has a thickness of about 6 nm or less. Further, when the gate insulating film 7a is made of an HfO ₂ film, the HfO ₂ film has a thickness of about 6 nm or less in terms of oxide film (SiO ₂ film). A gate electrode 8a is formed on the gate insulating film 7a. The gate electrode 8a is an example of the “first gate electrode” in the present invention.

  Here, in the present embodiment, the gate electrode 8a includes a TaN layer 9a formed on the gate insulating film 7a and a polysilicon layer 10a formed on the TaN layer 9a. The TaN layer 9a is an example of the “first metal layer” in the present invention, and the polysilicon layer 10a is an example of the “first semiconductor layer” in the present invention. The TaN layer 9a has an average film thickness (during film formation) of less than about 2.5 nm, which is smaller than the average film thickness (about 150 nm) of the polysilicon layer 10a. Further, as shown in FIG. 2, the TaN layer 9a is formed in a dot shape so as to partially cover the gate insulating film 7a. Thereby, the polysilicon layer 10a formed on the TaN layer 9a is in contact with the gate insulating film 7a through the region between adjacent dots of the TaN layer 9a having an average film thickness of less than about 2.5 nm. . Thus, in the present embodiment, the gate electrode 8a is composed of a TaN layer 9a having a very small thickness (less than about 2.5 nm) and a polycrystal having a large thickness (about 150 nm) constituting most of the gate electrode 8a. And a silicon layer 10a. The TaN layer 9a has a work function corresponding to a silicon midgap. That is, the Fermi level of the TaN layer 9a is located at an intermediate energy level between the conduction band and the valence band of silicon. Further, the polysilicon layer 10a is n-type by containing n-type impurities. The p-type channel region 5a, the pair of n-type source / drain regions 6a, the gate insulating film 7a and the gate electrode 8a constitute an n-channel MOS transistor 50a.

On the other hand, in the formation region of the p-channel MOS transistor 50b constituting the CMOS according to the present embodiment, the single crystal silicon layer 3 has a pair of p-type sources spaced apart from each other by a predetermined distance so as to sandwich the n-type channel region 5b. / Drain region 6b is formed. The n-type channel region 5b is an example of the “second channel region” in the present invention, and the p-type source / drain region 6b is an example of the “second source / drain region” in the present invention. . A gate insulating film 7b having the same composition (SiO ₂ or HfO ₂ ) and thickness (about 6 nm or less) as the gate insulating film 7a of the n-channel MOS transistor 50a is formed on the n-type channel region 5b. Has been. The gate insulating film 7b is an example of the “second gate insulating layer” in the present invention. A gate electrode 8b is formed on the gate insulating film 7b. The gate electrode 8b is an example of the “second gate electrode” in the present invention.

  Here, in this embodiment, the gate electrode 8b includes a TaN layer 9b having an average film thickness of less than about 2.5 nm formed on the gate insulating film 7b and an average of about 150 nm formed on the TaN layer 9b. The polysilicon layer 10b has a film thickness. The TaN layer 9b is an example of the “second metal layer” in the present invention, and the polysilicon layer 10b is an example of the “second semiconductor layer” in the present invention. The TaN layer 9b is formed in a dot shape so as to partially cover the gate insulating film 7b, like the TaN layer 9a of the n-channel MOS transistor 50a. The TaN layer 9b is formed by patterning the same layer as the TaN layer 9a. The polysilicon layer 10b is p-type because it contains p-type impurities. The n-type channel region 5b, the pair of p-type source / drain regions 6b, the gate insulating film 7b, and the gate electrode 8b constitute a p-channel MOS transistor 50b.

Further, an interlayer insulating film made of a SiO ₂ film having a thickness of about 200 nm so as to cover the element isolation region 4, the n-type source / drain region 6a, the p-type source / drain region 6b, and the gate electrodes 8a and 8b. 11 is formed. The interlayer insulating film 11 has contacts reaching the pair of n-type source / drain regions 6a, the pair of p-type source / drain regions 6b, the n-type polysilicon layer 10a, and the p-type polysilicon layer 10b, respectively. Holes 11a, 11b, 11c, 11d, 11e and 11f are formed. Plugs 12a, 12b, 12c, 12d, 13a and 13b made of tungsten are buried in the contact holes 11a, 11b, 11c, 11d, 11e and 11f, respectively.

  A wiring 14 is formed on the interlayer insulating film 11 so as to be connected to the plug 12a, and a wiring 15 is formed so as to connect the plugs 12b and 12c. Thus, one source / drain region 6a of n channel MOS transistor 50a and one source / drain region 6b of p channel MOS transistor 50b are connected via plugs 12b and 12c and wiring 15. A wiring 16 is formed on the interlayer insulating film 11 so as to be connected to the plug 12d. On the interlayer insulating film 11, wirings 17a and 17b are formed so as to be connected to the plugs 13a and 13b, respectively. The gate electrode 8a of the n-channel MOS transistor 50a and the gate electrode 8b of the p-channel MOS transistor 50b are connected through plugs 13a and 13b and wirings 17a and 17b.

  3 to 8 are cross-sectional views illustrating a CMOS manufacturing process according to an embodiment of the present invention. Next, with reference to FIG. 1 and FIGS. 3 to 8, a CMOS manufacturing process according to an embodiment of the present invention will be described.

First, as shown in FIG. 3, an SOI substrate is prepared in which a single crystal silicon layer 3 having a thickness of about 100 nm is formed on a silicon substrate 1 via a buried oxide film 2 having a thickness of about 200 nm. Then, the photolithography technique and the etching technique are used to remove the single crystal silicon layer 3 located in the element isolation region, and then an SiO ₂ film (not shown) is formed. Then, by removing the excessive deposited portion of the SiO ₂ film by a CMP (Chemical Mechanical Polishing) method or an etch back method, an element isolation insulating film 4 made of the SiO ₂ film as shown in FIG. 3 is formed. .

Next, as shown in FIG. 4, a gate insulating film 7 is formed on the top surfaces of the single crystal silicon layer 3 and the element isolation insulating film 4 using a CVD (Chemical Vapor Deposition) method or a sputtering method. At this time, in this embodiment, the gate insulating film 7 is formed of a high dielectric constant (High-k) insulating film such as a SiO ₂ film or a HfO ₂ film. When the gate insulating film 7 is formed by the SiO ₂ film, the SiO ₂ film is formed to have an approximately 6nm or less in thickness. On the other hand, in the case where the gate insulating film 7 is formed by the HfO ₂ film, the HfO ₂ film is formed to have an oxide film (SiO ₂ film) in terms of film about 6nm or less in thickness in thickness.

  Thereafter, in this embodiment, a TaN layer 9 having an average film thickness of less than about 2.5 nm is formed on the gate insulating film 7 by using the CVD method. Then, an amorphous silicon layer 10 having a thickness of about 150 nm is deposited on the TaN layer 9 using the CVD method. The TaN layer is deposited by deposition of the amorphous silicon layer 10 by this CVD method, heat treatment for activating impurities introduced into the source / drain regions 6a and 6b and the amorphous silicon layer 10 described later, and heat applied in other steps. No. 9 agglomerates in a dot shape due to the small average film thickness. Thereby, the TaN layer 9 is formed in a dot shape so as to partially cover the gate insulating film 7, and the amorphous silicon layer 10 is formed in the gate insulating film via the region between adjacent dots of the TaN layer 9. 7 is formed so as to contact 7. Thereafter, a resist layer 20 is formed on the region of the amorphous silicon layer 10 where the gate electrodes 8a and 8b (see FIG. 1) are to be formed using photolithography.

  Next, as shown in FIG. 5, the amorphous silicon layer 10, the TaN layer 9, and the gate insulating film 7 are etched using the resist layer 20 as a mask. Etching at this time is performed by RIE (Reactive Ion Etching). In the etching process by RIE, if the thickness of the TaN layer 9 is large, the TaN layer 9 is difficult to etch. In particular, vertical processing by etching of the TaN layer 9 becomes difficult. However, in the present embodiment, the TaN layer 9 is formed so as to have a small average film thickness of less than about 2.5 nm. Therefore, the TaN layer 9 can be easily etched by RIE. And the part corresponding to the gate electrodes 8a and 8b (refer FIG. 1) of the amorphous silicon layer 10 is formed by said etching. Further, TaN layers 9a and 9b constituting gate electrodes 8a and 8b (see FIG. 1) are respectively formed, and gate insulating films 7a and 7b corresponding to gate electrodes 8a and 8b (see FIG. 1) are respectively formed. The Thereafter, the resist layer 20 is removed.

Next, as shown in FIG. 6, in order to suppress damage in the vicinity of the edge portions of the gate insulating films 7a and 7b due to ion implantation, a protective film 21 made of a SiO ₂ film is formed so as to cover the entire surface. Then, using a photolithography technique, a resist layer 22 is formed so as to cover the region corresponding to the formation region of the p-channel MOS transistor 50b (see FIG. 1) of the protective film 21. Thereafter, phosphorus (P) is ion-implanted under the conditions of implantation energy: about 30 kev and implantation amount: about 3 × 10 ¹⁵ cm ⁻² . As a result, phosphorus (P) is introduced into the amorphous silicon layer 10 in the formation region of the n-channel MOS transistor 50a (see FIG. 1) and the source / drain region 6a in the single crystal silicon layer 3 through the protective film 21. Thereafter, the resist layer 22 is removed.

Next, as shown in FIG. 7, a resist layer 23 is formed using a photolithography technique so as to cover the region corresponding to the formation region of the n-channel MOS transistor 50 a (see FIG. 1) of the protective film 21. Thereafter, BF ₂ is ion-implanted under the conditions of implantation energy: about 35 kev and implantation amount: about 3 × 10 ¹⁵ cm ⁻² . As a result, BF ₂ is introduced into the amorphous silicon layer 10 in the formation region of the p-channel MOS transistor 50 b (see FIG. 1) and the source / drain region 6 b in the single crystal silicon layer 3 through the protective film 21. Thereafter, the resist layer 23 is removed.

Next, as shown in FIG. 8, by CVD, on the protective film 21 made of SiO ₂ film, by depositing a SiO ₂ film, an interlayer insulating film 11 having a thickness of about 200 nm. Thereafter, a heat treatment (about 950 ° C., about 20 seconds) by an RTA (Rapid Thermal Annealing) method is performed to electrically activate the impurities implanted into the source / drain regions 6 a and 6 b and the amorphous silicon layer 10. The amorphous silicon layer 10 is polycrystallized by this heat treatment. Thus, n-type polysilicon layer 10a is formed in the formation region of n-channel MOS transistor 50a, and p-type polysilicon layer 10b is formed in the formation region of p-channel MOS transistor 50b. In the formation region of the n-channel MOS transistor 50a, the gate electrode 8a is formed by the TaN layer 9a and the n-type polysilicon layer 10a formed on the TaN layer 9a. In the formation region of the p-channel MOS transistor 50b, the gate electrode 8b is formed by the TaN layer 9b and the p-type polysilicon layer 10b formed on the TaN layer 9b.

  During the above heat treatment, the Fermi level of the TaN layers 9a and 9b is pinned to the silicon midgap by the reaction that occurs at the interface between the TaN layer 9a (9b) and the gate insulating film 7a (7b). Further, during this heat treatment, the stress caused by the difference in thermal expansion coefficient between the TaN layer 9a (9b) and the gate insulating film 7a (7b) and the single crystal silicon layer 3 is caused by the TaN layer 9a (9b), It works between the gate insulating film 7a (7b) and the single crystal silicon layer 3.

  Next, as shown in FIG. 1, contact holes 11a are formed in regions corresponding to the source / drain regions 6a and 6b of the interlayer insulating film 11 and the polysilicon layers 10a and 10b by using a photolithography technique and an etching technique. , 11b, 11c, 11d, 11e and 11f. Thereafter, a CVD method is used to form a tungsten layer embedded in the contact holes 11a, 11b, 11c, 11d, 11e, and 11f, and then an extra deposited portion of the tungsten layer is removed using a CMP method. Thus, plugs 12a, 12b, 12c, 12d, 13a and 13b are formed. Finally, wirings 14, 15, 16, 17a and 17b are formed in predetermined regions on the upper surface of the interlayer insulating film 11. As described above, the CMOS according to the present embodiment shown in FIG. 1 is formed.

  In the present embodiment, as described above, the gate electrode 8a (8b) includes the TaN layer 9a (9b) formed on the gate insulating film 7a (7b) and the polysilicon formed on the TaN layer 9a (9b). Unlike the case where the gate electrode 8a (8b) is composed only of the polysilicon layer formed on the gate insulating film 7a (7b), the gate electrode 8a (8b) is depleted by being composed of the layer 10a (10b). Can be suppressed.

  In the present embodiment, the TaN layer 9a of the gate electrode 8a of the n-channel MOS transistor 50a and the TaN layer 9b of the gate electrode 8b of the p-channel MOS transistor 50b are formed of the same layer, so that the n-channel Since TaN layer 9a of MOS transistor 50a and TaN layer 9b of p-channel MOS transistor 50b can be simultaneously formed by patterning the same layer, gate electrode 8a of n-channel MOS transistor 50a and p-channel MOS transistor 50b The manufacturing process for forming the gate electrode 8b can be simplified.

  The gate electrode 8a (8b) is composed of the TaN layer 9a (9b) and the polysilicon layer 10a (10b) formed on the TaN layer 9a (9b), and the TaN layer 9a (9b) is made of polysilicon. By forming the TaN layer 9a (9b) by etching (RIE) by forming it so as to have an average film thickness of less than about 2.5 nm, which is smaller than the thickness of the layer 10a (10b), Even when the gate electrode 8a (8b) including the TaN layer 9a (9b) is used, the gate electrode 8a (8b) can be easily patterned. Further, since the thickness of the TaN layer 9a (9b) is small, the stress caused by the difference in thermal expansion coefficient between the TaN layer 9a (9b), the gate insulating film 7a (7b) and the single crystal silicon layer 3 is reduced. be able to. Thereby, it is possible to reduce deterioration of electron mobility caused by stress acting between the TaN layer 9a (9b), the gate insulating film 7a (7b) and the single crystal silicon layer 3.

  In the present embodiment, the TaN layer 9a (9b) is formed in a dot shape so as to partially cover the gate insulating film 7a (7b), and the polysilicon layer 10a (10b) is formed as the gate insulating film 7a (7b). ), The contact area between the TaN layer 9a (9b) and the gate insulating film 7a (7b) can be reduced. Accordingly, the Fermi level pinning of the TaN layer 9a (9b) due to the interface reaction between the TaN layer 9a (9b) and the gate insulating film 7a (7b) is less likely to occur. As a result, it can be suppressed that it is difficult to adjust the work functions of gate electrodes 8a and 8b to values suitable for n channel MOS transistor 50a and p channel MOS transistor 50b due to pinning.

  Next, an experiment conducted for confirming the effect of forming the gate electrode by the TaN layer and the polysilicon layer formed on the TaN layer as described above will be described. In this experiment, using an n-channel MOS transistor having a gate electrode having the structure of the above-described embodiment, a change in flat band voltage, a change in effective oxide equivalent film thickness of the gate insulating film, a capacitance − The gate voltage characteristics and electron mobility were examined. Further, using a p-channel MOS transistor in which the gate electrode having the structure of the above-described embodiment was formed, the change in flat band voltage and the change in the equivalent oxide film thickness of the gate insulating film were examined. Details will be described below.

First, an experiment conducted for examining changes in the flat band voltage of the n-channel MOS transistor and changes in the equivalent oxide thickness of the gate insulating film will be described. First, a plurality of n-channel MOS transistors were manufactured by changing the thickness of the TaN layer of the gate electrode from 0.0 nm to 10.0 nm. At this time, the gate insulating film was formed of a SiO ₂ film having a thickness of 4 nm. Except for this, an n-channel MOS transistor was fabricated in the same manner as in the above embodiment. And about the produced n channel MOS transistor, the flat band voltage _Vfb and the effective oxide film equivalent film thickness of a gate insulating film were measured. Here, the flat band voltage V _fb is a gate voltage necessary for flattening the energy band structure at the interface between the gate insulating film and the silicon layer constituting the channel region. _{When fb} changes, the threshold voltage of the n-channel MOS transistor also changes. The effective oxide film equivalent film thickness of the gate insulating film is an oxide film equivalent film thickness of a region functioning as a gate insulating film, which is measured electrically. The result of the above measurement is shown in FIG. The flat band voltage V _fb shown in FIG. 9 is a control sample (n-channel MOS) in which a gate electrode is formed only by a polysilicon layer having a thickness of 150 nm from the flat band voltage of each measurement sample (n-channel MOS transistor). The value obtained by subtracting the flat band voltage of the transistor) is shown. That is, the flat band voltage V _fb shown in FIG. 9 is calculated from the flat band voltage of each measurement sample (n channel MOS transistor), and the flatness of the n channel MOS transistor when the thickness of the TaN layer in FIG. The value obtained by subtracting the band voltage is shown.

Referring to FIG. 9, it can be seen that the flat band voltage V _fb gradually increases from 0.0 V to about 0.6 V as the thickness of the TaN layer gradually increases from 0.0 nm to 10 nm. Thus, it was found that the threshold voltage of the n-channel MOS transistor can be controlled by controlling the thickness of the TaN layer in the gate electrode. Further, from FIG. 9, by forming the TaN layer to a thickness of about 0.5 nm to about 2.5 nm, the flat band voltage V _fb is about 0.2 V to about 0.3 V compared to the case where the TaN layer is 0 nm. It can be seen that it can only be increased. That is, the work function of the gate electrode can be brought close to the silicon midgap by about 0.2 V to about 0.3 V, so that the threshold voltage of the n-channel MOS transistor is increased by about 0.2 V to about 0. It can be seen that it can be increased by 3V. From this result, with the miniaturization of the n-channel MOS transistor, the off-leakage current becomes too large because the threshold voltage, which has been a problem in a fully depleted SOIFET (Silicon on Insulator Field Effect Transistor), etc., is too low. Even when inconvenience occurs, if the gate electrode structure according to the present embodiment is used and the TaN layer is formed to a thickness of about 0.5 nm to about 2.5 nm, the threshold voltage is about 0.2 V to about 0. It has been found that by increasing the voltage by .3 V, the inconvenience that the off-leakage current becomes too large can be suppressed.

  Next, the results of measuring the capacitance-gate voltage characteristics of the n-channel MOS transistor will be described. First, n-channel MOS transistors according to Example 1 and Comparative Example 1 below were manufactured. Thereafter, the capacitance was measured using the manufactured n-channel MOS transistor while changing the applied gate voltage.

Example 1
In Example 1, the gate electrode was formed by a TaN layer having a thickness of 1 nm and a polysilicon layer having a thickness of 150 nm formed on the TaN layer. Further, the gate insulating film was formed of a SiO ₂ film having a thickness of 4 nm. In Example 1, an n-channel MOS transistor having a size of 100 μm × 100 μm was fabricated. Except for this, an n-channel MOS transistor according to Example 1 was fabricated in the same manner as the n-channel MOS transistor according to the above embodiment.

(Comparative Example 1)
In Comparative Example 1, the gate electrode was formed only by a polysilicon layer having a thickness of 150 nm. Except for this, an n-channel MOS transistor according to Comparative Example 1 was fabricated in the same manner as in Example 1 above.

10 and 11 show the results of measuring the capacitance-gate voltage (CV) characteristics using the n-channel MOS transistors (100 μm × 100 μm) according to Example 1 and Comparative Example 1, respectively. Yes. As can be seen from FIGS. 10 and 11, Comparative Example 1 (see FIG. 11) is performed in a positive range (> 0 V) where the n-channel MOS transistor can be operated by forming an inversion layer in the channel region. ), The capacitance is about 7.0 × 10 ⁻¹¹ F or less when the gate voltage is in the range of about 1 V or more, whereas in Example 1 (see FIG. 10), the gate voltage is in the range of about 1 V or more. The capacity is about 7.0 × 10 ⁻¹¹ F or more. Thus, it can be seen that when a gate voltage of about 1 V or more is applied, the n-channel MOS transistor according to the first embodiment has a larger capacity than the n-channel MOS transistor according to the first comparative example. Since the capacitance of the n-channel MOS transistor becomes larger as the thickness of the depletion layer of the gate electrode becomes smaller, the thickness of the depletion layer of the gate electrode of the n-channel MOS transistor according to Example 1 is larger than that of the n-channel MOS transistor according to Comparative Example 1. This is considered to be smaller than the thickness of the depletion layer. From the above results, it is possible to suppress the depletion of the gate electrode by providing a TaN layer having a thickness of 1 nm at the time of film formation at a portion in contact with the gate insulating film as in Example 1. found.

  Next, an experiment conducted for examining the electron mobility of the n-channel MOS transistor will be described. First, n-channel MOS transistors according to the following Example 2-1, Example 2-2, and Comparative Example 2-1 were fabricated. And the electron mobility was measured using the produced n channel MOS transistor while changing the applied electric field strength.

(Example 2-1)
In Example 2-1, a gate electrode is formed by a TaN layer having a thickness of 1 nm (during film formation) formed on the gate insulating film and a polysilicon layer having a thickness of 150 nm formed on the TaN layer. did. Further, the gate insulating film was formed of a SiO ₂ film having a thickness of 4 nm. In Example 2-1, an n-channel MOS transistor having a size of 100 μm × 100 μm was fabricated. Except for this, an n-channel MOS transistor according to Example 2-1 was fabricated in the same manner as the n-channel MOS transistor according to the above embodiment.

(Example 2-2)
In Example 2-2, a gate electrode is formed by a TaN layer having a thickness of 2.5 nm (during film formation) formed on the gate insulating film and a polysilicon layer having a thickness of 150 nm formed on the TaN layer. Formed. Other than this, an n-channel MOS transistor according to Example 2-2 was fabricated in the same manner as in Example 2-1.

(Comparative Example 2-1)
In Comparative Example 2-1, the gate electrode was formed only by the polysilicon layer having a thickness of 150 nm formed on the gate insulating film. In other words, an n-channel MOS transistor having a gate electrode TaN layer with a thickness of 0 nm was fabricated. Except for this, an n-channel MOS transistor according to Comparative Example 2-1 was fabricated in the same manner as in Example 2-1.

FIGS. 12 to 14 show the relationship between the effective vertical electric field strength and the electron mobility measured using the n-channel MOS transistors according to Examples 2-1 and 2-2 and Comparative Example 2-1, respectively. ing. Referring to FIGS. 12 to 14, in the range of the effective vertical electric field strength of about 0.1 MV / cm to about 1 MV / cm, the n-channel MOS transistor according to Example 2-1 (see FIG. 12), about 240 cm ² / shows an electron mobility of Vs～ about 480 cm ² / Vs, n-channel MOS transistor according to example 2-2 (see FIG. 13) shows the electron mobility of about 180cm ² / Vs~ about 240 cm ² / Vs, n-channel MOS transistor according to the comparative example 2-1 (see FIG. 14) it is seen to exhibit electron mobility of about 220cm ² / Vs~ about 400 cm ² / Vs. From this result, the n-channel MOS transistor according to Example 2-1 in which the TaN layer of the gate electrode is formed with a thickness of 1 nm has the same electron as the n-channel MOS transistor according to Comparative Example 2-1 in which the gate electrode does not include the TaN layer. It can be seen that it has mobility. On the other hand, in the n-channel MOS transistor according to Example 2-2 in which the TaN layer of the gate electrode is formed with a thickness of 2.5 nm, compared to the n-channel MOS transistor according to Comparative Example 2-1 in which the gate electrode does not include the TaN layer, It can be seen that the electron mobility is low. That is, when a gate electrode having a structure according to the present invention is used, it is preferable to form a TaN layer of the gate electrode so as to have a thickness of less than 2.5 nm (during film formation) in order to obtain high electron mobility. It has been found.

  The reason why the electron mobility is lower when the TaN layer is formed with a thickness of 2.5 nm than when the TaN layer of the gate electrode is formed with a thickness of 1 nm is considered to be as follows. That is, when the thickness of the TaN layer is 1 nm, the thermal expansion coefficient of the TaN layer, the gate insulating film, and the single crystal silicon layer is smaller than the thickness of the TaN layer is 2.5 nm. It is considered that the stress due to the difference can be reduced. As a result, when the thickness of the TaN layer is 1 nm, it is caused by the difference in stress acting between the TaN layer, the gate insulating film, and the single crystal silicon layer, compared with the case where the thickness of the TaN layer is 2.5 nm. It is considered that the deterioration of the electron mobility is suppressed. For this reason, when the TaN layer is formed with a thickness of 2.5 nm, the electron mobility is considered to be lower than when the TaN layer is formed with a thickness of 1 nm.

  Next, regarding a p-channel MOS transistor using a gate electrode composed of a TaN layer and a polysilicon layer similar to the above-described embodiment, the change in flat band voltage performed in the n-channel MOS transistor and the effective gate insulating film An experiment similar to the experiment for examining the change in the equivalent oxide thickness was performed. The result is shown in FIG.

Referring to FIG. 15, it can be seen that the flat band voltage V _fb gradually decreases from 0.0 V to about −0.6 V as the thickness of the TaN layer gradually increases from 0.0 nm to 10 nm. . Thus, it has been found that the threshold voltage of the p-channel MOS transistor can be controlled by controlling the thickness of the TaN layer in the gate electrode. In addition, it can be seen from FIG. 15 that by forming the TaN layer to a thickness of about 0.5 nm, the flat band voltage V _fb can be reduced by about 0.3 V compared to the case where the TaN layer is 0 nm. In other words, in this case, the work function of the gate electrode can be brought close to the silicon midgap by about 0.3 V, so that the threshold voltage of the p-channel MOS transistor is increased by about 0.3 V accordingly. I can see that From this result, when the p-channel MOS transistor is miniaturized, the gate electrode structure according to the present embodiment is used even when there is a disadvantage that the off-leakage current becomes too large due to the threshold voltage being lowered too much. It has been found that if the TaN layer is formed to a thickness of about 0.5 nm, it is possible to suppress the disadvantage that the off-leakage current becomes too large by increasing the threshold voltage by about 0.3V.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and further includes all modifications within the meaning and scope equivalent to the scope of claims for patent.

For example, in the above embodiment, the CMOS as an example of the semiconductor device according to the present invention has been described as an example. However, the present invention is not limited to this, and the present invention can be applied to semiconductor devices other than the CMOS.
In the above embodiment, an example in which the polysilicon layer of the gate electrode of the n-channel MOS transistor constituting the CMOS is n-type and the polysilicon layer of the gate electrode of the p-channel MOS transistor is p-type has been described. The present invention is not limited to this, and the polysilicon layers of the gate electrodes of the n-channel MOS transistor and the p-channel MOS transistor constituting the CMOS may be of the same conductivity type.

Moreover, in the said embodiment, although the metal layer of the gate electrode was formed in dot shape, this invention is not limited to this, You may form the metal layer of a gate electrode in shapes other than a dot shape. Further, the metal layer of the gate electrode may be formed by a continuous film formed on the entire surface of the gate insulating film.
Moreover, in the said embodiment, after forming a metal layer on a gate insulating film using CVD method, the metal layer was formed in the shape of a dot by aggregating a metal layer by heat processing, but this invention does this. However, the metal layer may be formed in a dot shape using various methods other than those described above. For example, by controlling the formation conditions by the CVD method so that the metal layer is already formed in a dot shape in the state where the metal layer is formed on the gate insulating film by the CVD method, the metal layer can be doted without performing heat treatment. You may form in a shape.
In the above embodiment, after forming the metal layer of the gate electrode by the CVD method, the step of depositing the amorphous silicon layer by the CVD method, or for activating impurities introduced into the source / drain regions and the amorphous silicon layer The heat treatment step and heat applied in other steps were used to agglomerate the metal layer in the form of dots, but the present invention is not limited to this, after forming the metal layer on the gate insulating film by the CVD method, By subsequently performing a heat treatment, the metal layer may be aggregated into dots.

  In the above embodiment, the metal layer of the gate electrode is formed of TaN. However, the present invention is not limited to this, and the metal layer of the gate electrode may be formed of a material other than TaN. For example, metal silicides such as TiSi, TaSi, and PtSi, metal nitrides, and simple metals can be used as the material for the metal layer of the gate electrode.

In the above embodiment, the HfO ₂ film is used as the high dielectric constant insulating film having a relative dielectric constant larger than 3.9 for forming the gate insulating film. However, the present invention is not limited to this, and the gate insulating film is not limited thereto. An insulating film made of a material other than the HfO ₂ film may be used as the high dielectric constant insulating film for forming the film. For example, a ZrO ₂ film, HfAlO film, SiN film, SiON film, HfSiO film, HfNO film, or the like may be used as the high dielectric constant insulating film for forming the gate insulating film.

  Moreover, in the said embodiment, although CMOS was formed using the SOI substrate, this invention is not limited to this, You may form CMOS using semiconductor substrates other than an SOI substrate. For example, a CMOS may be formed using a single crystal silicon substrate or the like. In this case, as shown in FIG. 16, p-type impurity is introduced into a predetermined region of single crystal silicon substrate 31 to form p well region 32 a, and n type is applied to the predetermined region of single crystal silicon substrate 31. The n well region 32b is formed by introducing the impurity. The p well region 32a and the n well region 32b of the single crystal silicon substrate 31 are examples of the “semiconductor region” in the present invention. Then, n-channel MOS transistor 50a is formed in p-well region 32a of single crystal silicon substrate 31, and p-channel MOS transistor 50b is formed in n-well region 32b.

  In the above embodiment, the gate electrode 8a of the n-channel MOS transistor 50a and the gate electrode 8b of the p-channel MOS transistor 50b are connected via the plugs 13a and 13b and the wirings 17a and 17b. However, the present invention is not limited to this, and the gate electrode 8a of the n-channel MOS transistor 50a and the gate electrode 8b of the p-channel MOS transistor 50b may be connected by various configurations other than those described above. For example, by using salicide technology, a single layer made of Ti, Co, or the like that connects the polysilicon layer 10a of the gate electrode 8a of the n-channel MOS transistor 50a and the polysilicon layer 10b of the gate electrode 8b of the p-channel MOS transistor 50b. A silicide layer is formed on polysilicon layers 10a and 10b by forming a metal layer and heat-treating, and gate electrode 8a of n-channel MOS transistor 50a and p-channel MOS transistor 50b are formed through the silicide layer. You may make it connect with the gate electrode 8b.

1 is a cross-sectional view illustrating a structure of a CMOS according to an embodiment of the present invention. FIG. 2 is an enlarged cross-sectional view showing the structure of an n-channel MOS transistor portion of the CMOS according to the embodiment shown in FIG. 1. It is sectional drawing for demonstrating the manufacturing process of CMOS by one Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of CMOS by one Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of CMOS by one Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of CMOS by one Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of CMOS by one Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of CMOS by one Embodiment of this invention. FIG. 6 is a correlation diagram showing the relationship between the thickness of the TaN layer of the gate electrode, the flat band voltage, and the effective equivalent oxide thickness of the gate insulating film in the n-channel MOS transistor of the present invention. It is the figure which showed the capacitance-gate voltage characteristic of the n channel MOS transistor by Example 1 of this invention. It is the figure which showed the capacity-gate voltage characteristic of the n channel MOS transistor by the comparative example 1 of this invention. It is the correlation figure which showed the relationship between the electron mobility and electric field strength of the n channel MOS transistor by Example 2-1 of this invention. It is the correlation figure which showed the relationship between the electron mobility of n channel MOS transistor by Example 2-2 of this invention, and electric field strength. It is the correlation figure which showed the relationship between the electron mobility and electric field strength of an n channel MOS transistor by the comparative example 2-1 of this invention. FIG. 6 is a correlation diagram showing the relationship between the thickness of the TaN layer of the gate electrode, the flat band voltage, and the effective equivalent oxide thickness of the gate insulating film in the p-channel MOS transistor of the present invention. It is sectional drawing which showed the structure of CMOS by the modification of one Embodiment of this invention.

Explanation of symbols

3 Single crystal silicon layer (semiconductor region)
5a channel region (first channel region)
5b channel region (second channel region)
6a Source / drain region (first source / drain region)
6b Source / drain region (second source / drain region)
7a Gate insulating film (first gate insulating layer)
7b Gate insulating film (second gate insulating layer)
8a Gate electrode (first gate electrode)
8b Gate electrode (second gate electrode)
9a TaN layer (first metal layer)
9b TaN layer (second metal layer)
10a Polysilicon layer (first semiconductor layer)
10b Polysilicon layer (second semiconductor layer)
32a p-well region (semiconductor region)
32b n-well region (semiconductor region)

Claims (7)

A pair of first source / drain regions of the first conductivity type formed at a predetermined interval so as to sandwich the first channel region on the main surface of the semiconductor region;
A first gate electrode formed on the first channel region via a first gate insulating layer;
A pair of second source / drain regions of the second conductivity type formed at a predetermined interval so as to sandwich the second channel region on the main surface of the semiconductor region;
A second gate electrode formed on the second channel region via a second gate insulating layer;
The first gate electrode includes a first metal layer formed on the first gate insulating layer, and a first semiconductor layer formed on the first metal layer,
The second gate electrode includes a second metal layer formed on the second gate insulating layer, and a second semiconductor layer formed on the second metal layer,
The semiconductor device, wherein the first metal layer and the second metal layer are made of the same layer.   The semiconductor device, wherein the first metal layer and the second metal layer have an average film thickness smaller than a film thickness of the first semiconductor layer and the second semiconductor layer.   The semiconductor device according to claim 2, wherein the first metal layer and the second metal layer have an average film thickness of less than 2.5 nm. The first metal layer and the second metal layer are formed so as to partially cover the first gate insulating layer and the second gate insulating layer, respectively.
The first semiconductor layer and the second semiconductor layer are respectively covered with a portion of the first gate insulating layer that is not covered with the first metal layer and with the second metal layer of the second gate insulating layer. The semiconductor device according to claim 1, wherein the semiconductor device is formed so as to be in contact with a portion that is not present.   The semiconductor device according to claim 4, wherein the first metal layer and the second metal layer are formed in a dot shape.   6. The semiconductor device according to claim 4, wherein the first gate insulating layer and the second gate insulating layer are made of a high dielectric constant insulating film having a relative dielectric constant greater than 3.9. The first semiconductor layer includes a silicon layer containing an impurity of a first conductivity type,
The semiconductor device according to claim 1, wherein the second semiconductor layer includes a silicon layer containing an impurity of a second conductivity type.

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