JP3966102B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a gate insulating film made of a high dielectric material.
[0002]
[Prior art]
In recent years, high speed operation and low power consumption have been demanded for semiconductor devices. Here, in order to achieve high speed, for example, it is necessary to increase the gate current of the MOSFET to increase the drive current. Therefore, in a structure using a silicon oxide film or a silicon oxynitride film as a gate oxide film of the MOSFET, the gate oxide film has a thin film thickness in order to increase the gate capacitance. However, if the film thickness is reduced to 1.5 nm or less, the leakage current flowing through the capacitor increases, so it is difficult to reduce power consumption even if high-speed operation can be realized, and the original operation of the capacitor to accumulate charge is also possible. There was a problem of difficulty.
[0003]
Therefore, as a gate insulating film material of the MOSFET, a metal oxide film having a higher dielectric constant than a silicon oxide film (relative dielectric constant: K = 3.9), for example, an aluminum oxide film (K = 9), a zirconium oxide film ( Attempts have been made to apply K = 20), hafnium oxide films (K = 20), tantalum oxide films (K = 25), titanium oxide films (K = 40), and the like. Since the relative dielectric constant of these metal oxide films is larger than that of silicon oxide films, the amount of charge accumulation increases, and even if the capacitance value is the same, the actual physical film thickness can be set thick. The increase can be suppressed (for example, Journal of Applied Physics vol. 89 5243 (2001)).
[0004]
Japanese Patent Laid-Open No. 10-189966 has proposed a method of manufacturing a semiconductor device using such a high dielectric film. In this manufacturing method, after forming a dummy gate pattern on a silicon substrate, an impurity diffusion layer is formed on the silicon substrate.
[0005]
Next, after forming an interlayer insulating film on the silicon substrate, the interlayer insulating film formed on the silicon substrate is planarized by a method such as CMP (Chemical Mechanical Polishing) to expose the surface of the dummy gate pattern. . Thereafter, after selectively removing the dummy gate pattern, a gate insulating film and a gate electrode are formed.
[0006]
[Problems to be solved by the invention]
However, when the interlayer insulating film is formed in the above conventional example, in order to improve the embedding characteristic in the vicinity of the dummy gate pattern, a high concentration that can be easily flattened by processing such as a BPSG (Born Phosphorous doped Silicate Glass) film. A silicon oxide film doped with impurities (hereinafter referred to as a doped oxide film) is used as an interlayer insulating film. In general, a doped oxide film has a higher etching rate than a silicon oxide film (hereinafter referred to as a non-doped oxide film) to which impurities are not substantially added during etching. For this reason, when the dummy gate pattern is removed, the interlayer insulating film is also etched to reduce the film thickness.
[0007]
Furthermore, it is conceivable to remove the dummy gate pattern by protecting the region other than the dummy gate pattern with a resist film, but the mask alignment process becomes very difficult when the gate pattern is miniaturized. Therefore, when removing the dummy gate pattern, it is desirable to protect the region other than the dummy gate pattern in a self-aligning manner.
[0008]
An object of the present invention is to solve such a problem, and an object of the present invention is to prevent a reduction in the thickness of an interlayer insulating film and to remove a dummy gate pattern so that a region other than the dummy gate pattern is protected in a self-aligning manner. To do.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a dummy gate pattern in a gate formation region on a semiconductor substrate, a method of manufacturing a semiconductor device having a gate insulating film, Forming a first film on the semiconductor substrate excluding the gate pattern, forming a second film on the first film, selectively removing the dummy gate pattern, and a dummy gate pattern A step of forming a gate insulating film on the inner wall of the recess from which the gate is removed, and a step of forming a gate electrode in the recess from which the gate insulating film is formed. The second film includes a dummy gate pattern and a first film. The material is characterized by using a material that can take an etching rate selection ratio.
[0010]
With this configuration, when the dummy gate pattern is removed, it is possible to prevent the interlayer insulating film from being significantly reduced and to protect regions other than the dummy gate pattern in a self-aligning manner.
[0011]
In the above manufacturing method, the step of forming the gate insulating film is characterized in that the gate insulating film is formed only on the bottom surface of the recess.
[0012]
According to this configuration, the dimensions of the gate electrode can be formed with good controllability regardless of the thickness of the gate insulating film, so that variation in transistor characteristics can be reduced.
[0013]
In the above manufacturing method, a step of forming a low-concentration impurity diffusion layer on the semiconductor substrate using the dummy gate pattern as a mask, a step of forming a sidewall on the sidewall of the dummy gate pattern, and using the sidewall and the dummy gate pattern as a mask And a step of forming a high concentration impurity diffusion layer on the semiconductor substrate.
[0014]
In the above manufacturing method, the step of forming the first film includes the step of depositing the first film on the semiconductor substrate including the dummy gate pattern with a thickness greater than the height of the dummy gate pattern, and the dummy gate pattern. It is preferable to further include a step of planarizing the first film so as not to be exposed and a step of removing the first film until the dummy gate pattern is exposed.
[0015]
In the above manufacturing method, the step of forming the second film includes the step of depositing the second film on the semiconductor substrate including the dummy gate pattern with a film thickness equal to or greater than the height of the dummy gate pattern, and the dummy gate pattern. It is preferable to further include a step of planarizing the second film until it is exposed.
[0016]
In the above manufacturing method, the dummy gate pattern is formed of a polysilicon film, the first film is a silicon oxide film doped with impurities at a high concentration, and the second film is substantially doped with impurities. It is preferable that the silicon oxide film is not formed.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
A method for manufacturing a semiconductor device having a gate insulating film according to the first embodiment of the present invention will be described below with reference to FIGS.
[0018]
First, as illustrated in FIG. 1A, an element isolation layer 1002 is formed on a semiconductor substrate 1001. Here, a silicon oxide film 1002 is formed on a (100) -plane silicon substrate 1001 by STI (Shallow Trench Isolation).
[0019]
Note that other semiconductor substrates such as a SiGe or GaAs substrate can be used instead of the silicon substrate. In addition, other element isolation methods such as the LOCOS method can be applied instead of the STI method.
[0020]
Next, as shown in FIG. 1B, the natural oxide film 1016 is removed. Here, the natural oxide film 1016 is formed of DHF (for example, HF: H ₂ The surface of the silicon substrate 1001 in the active region is exposed by etching using O = 1: 200).
[0021]
Next, a dummy gate pattern 1100 is formed in the gate electrode formation region on the silicon substrate 1001. Here, a silicon oxide film 1101 having a thickness of about 5 nm is formed on the silicon substrate 1001 as a base film, and a polysilicon film 1102 having a thickness of about 200 nm is formed thereon. Thereafter, the polysilicon film 1102 and the silicon oxide film 1101 are sequentially processed by lithography and RIE to form a dummy gate pattern 1100.
[0022]
Note that other deposited films such as a silicon nitride film can be used instead of the polysilicon film. That is, the material used for the dummy gate pattern 1100 may be any film type that can be selectively removed with respect to the silicon oxide film 1002 of the element isolation layer in a later process. In particular, in the case of a polysilicon film, the etching selectivity with respect to the silicon oxide film 1101 can be easily obtained when the polysilicon film is etched by RIE. Therefore, etching damage due to RIE on the silicon substrate 1001 can be suppressed.
[0023]
The cross-sectional shape of the dummy gate pattern 1100 is similar to that of a gate electrode formed in a later process. For example, the shape may be substantially the same as the gate electrode.
[0024]
Next, as shown in FIG. 1C, low-concentration impurity diffusion layers 1006 and 1007 are formed. Here, using dummy gate pattern 1100 as a mask, for example, phosphorus (P) is 50 keV, 1 × 10 6. ¹⁴ cm ^-2 Ion implantation at a degree. Thereafter, heat treatment is performed in a non-oxidizing atmosphere to activate the impurities. As a result, the low-concentration impurity diffusion layers 1006 and 1007 are n. ^- A mold diffusion layer was formed.
[0025]
Here, the impurity diffusion layers 1006 and 1007 are formed in the silicon substrate 1001 so as to be adjacent to the dummy gate pattern 1100. In other words, the impurity diffusion layers 1006 and 1007 are formed in the silicon substrate 1001 on the side (near) the gate electrode pattern 1003 formed in a later step.
[0026]
Next, as shown in FIG. 2A, a silicon oxide film 1104 as a sidewall is formed on the sidewall of the dummy gate pattern 1100. Here, after forming a silicon oxide film 1104 with a thickness of about 20 nm on the silicon substrate 1001, RIE is performed on the entire surface of the silicon oxide film 1104. As a result, a silicon oxide film 1104 which is a sidewall having a thickness of about 20 nm is formed on the sidewall of the dummy gate pattern 1100.
[0027]
Next, as shown in FIG. 2B, high-concentration impurity diffusion layers 1010 and 1011 are formed. Here, for example, arsenic (As) is 40 keV, 1 × 10 6 using the dummy gate pattern 1100 and the silicon oxide film 1104 as a mask. ¹⁵ ~ 5x10 ¹⁵ cm ^-2 Ion implantation at a degree. Thereafter, heat treatment is performed in a non-oxidizing atmosphere to activate the impurities. As a result, the high-concentration impurity diffusion layers 1010 and 1011 are n ⁺ A mold diffusion layer was formed.
[0028]
Here, the impurity diffusion layers 1010 and 1011 are formed in the silicon substrate 1001 so as to be adjacent to the silicon oxide film 1104 which is a sidewall. In other words, the impurity diffusion layers 1010 and 1011 are formed in the silicon substrate 1001 on the side (near the side) of the silicon oxide film 1104 which is a sidewall.
[0029]
Further, a single drain structure in which only the impurity diffusion layers 1006 and 1007 or only the impurity diffusion layers 1010 and 1011 may be formed without using the LDD structure. In particular, when only the impurity diffusion layers 1006 and 1007 are formed, the step of forming the silicon oxide film 1104 which is a sidewall and the step of forming the impurity diffusion layers 1010 and 1011 shown in FIGS. Can be omitted. On the other hand, in the case where only the impurity diffusion layers 1010 and 1011 are provided, the step of forming the impurity diffusion layers 1006 and 1007 and the silicon oxide film 1104 which is a sidewall shown in FIGS. The step of forming may be omitted.
[0030]
Next, as shown in FIG. 2C, a BPSG film 1105 as a first film is formed on the entire surface of the silicon substrate 1001. Here, for example, the BPSG film 1105 is formed with a film thickness of about 800 nm at about 400 to 500 ° C. by the AP-CVD method.
[0031]
Note that the BPSG film 1105 may be formed at about 800 ° C. by another LP-CVD method instead of the AP-CVD method. In this case, heat treatment in the non-oxidizing atmosphere of the impurity diffusion layers 1006 and 1007 or the impurity diffusion layers 1010 and 1011 described above can be performed and the impurity diffusion layer can be activated by heating in the CVD process.
[0032]
Further, when suppressing the diffusion depth of the impurity diffusion layers 1006 and 1007 or the impurity diffusion layers 1010 and 1011, the temperature of the heat treatment described above is lowered to about 750 ° C., and RTA (Rapid Thermal Anneal) is performed at 950 ° C. for about 10 seconds. The ion implantation layer may be activated by using a process together.
[0033]
Next, as shown in FIG. 3A, the BPSG film 1105 as the first film is planarized. Here, the BPSG film 1105 is planarized over the entire surface from above the silicon substrate 1001 by CMP. At this time, it is not necessary to expose the surface of the polysilicon film which is the dummy gate pattern 1100. Preferably, the BPSG film 1105 is planarized so as not to expose the surface of the polysilicon film.
[0034]
Next, as shown in FIG. 3B, the BPSG film 1105 as the first film is removed until the dummy gate pattern 1100 is exposed. Here, DHF (for example, HF: H ₂ O = 1: 100), and the BPSG film 1105 is removed until about half of the dummy gate pattern 1100 is exposed.
[0035]
Next, as shown in FIG. 3C, an NSG (Non doped Silicate Glass) film 1106 as a second film is formed. Here, an HDP-NSG (High Density Plasma-Non doped Silicate Glass) film 1106 is formed to be equal to or higher than the height of the dummy gate pattern 1100 by plasma CVD.
[0036]
Next, as shown in FIG. 4A, the surface of the polysilicon film 1102 which is the dummy gate pattern 1100 is exposed. Here, the NSG film 1106 is planarized over the entire surface from above the silicon substrate 1001 by CMP. As a result, the surface of the polysilicon film 1102 that becomes the dummy gate pattern 1100 is exposed.
[0037]
Next, as shown in FIG. 4B, the dummy gate pattern 1100 is selectively removed. Here, the dummy gate pattern 1100 exposed using potassium hydroxide (KOH) is selectively removed by wet etching. As a result, the surface of the silicon oxide film 1101 or the element isolation layer 1002 is exposed on the bottom surface of the recess from which the dummy gate pattern 1100 is removed. Thereafter, the exposed silicon oxide film 1101 is removed by wet etching using DHF or the like.
[0038]
It should be noted that chlorine gas (Cl ₂ May be used for dry etching. Carbon tetrafluoride (CF _Four ) CDE (Chemical Dry etching) using gas may be performed. Further, wet etching using DHF may be performed.
[0039]
Thereafter, as shown in FIG. 4C, a channel region 1107 is formed on the surface of the silicon substrate 1001 exposed at the bottom surface of the recess. Here, ion implantation is performed only in a desired channel region using the NSG film 1106, the silicon oxide film 1104 as a sidewall, and a resist film (not shown) as a mask. For example, when a threshold value (Vth) of about 0.7 V is set for an n-channel transistor, for example, boron (B) is set to 10 keV, 5 × 10 5 ¹² cm ^-2 Ion implantation at a degree. As a result, the p-type channel impurity layer 1107 is selectively formed only in the channel region.
[0040]
Next, as shown in FIG. 5A, a gate insulating film 1004 and a gate electrode 1005 are formed so as to be embedded in the recess. Here, a high dielectric film is formed as the gate insulating film 1004 and a tungsten film is formed as the gate electrode 1005.
[0041]
First, a hafnium oxide film which is a high dielectric film functioning as a gate insulating film 1004 is formed on the inner wall of the recess on the silicon substrate 1001. Here, a metal hafnium target, argon (Ar) gas and oxygen (O ₂ ) Sputter deposition is performed with a power of 200 W using a gas mixture. As a result, a hafnium oxide film 1004 which is a metal oxide film is formed with a thickness of about 3 nm.
[0042]
Note that sputter deposition may be performed using a hafnium oxide itself as a target as a metal oxide. Alternatively, the hafnium oxide film 1004 may be formed using a CVD method instead of the sputter deposition. For example, as conditions for depositing hafnium oxide, a deposition temperature of 400 ° C., a pressure of 30 Pa, tetradiethylaminohafnium as a source gas, and oxygen as an oxidizing gas can be used. Here, the tetradiethylaminohafnium flow rate was 0.1 ml / min, the carrier nitrogen flow rate was 500 ml / min, and the oxygen flow rate was 500 ml / min.
[0043]
Next, a tungsten film is formed as a gate electrode 1005 in the recess. Here, a tungsten film with a thickness of about 100 nm is formed over the hafnium oxide film 1004. The tungsten film 1005 was formed by sputter deposition at a power of 300 W using argon gas with metallic tungsten as a target.
[0044]
Note that other conductive films such as a tantalum nitride (TaN) film and a polysilicon film can be applied instead of the tungsten film which is a metal film. Here, since tungsten and tantalum nitride are mid-gap metals, they can be used for both n-channel transistors and p-type n-channel transistors. That is, by using tungsten or tantalum nitride, the difference in threshold voltage between the n-channel transistor and the p-type n-channel transistor is small. Therefore, it is particularly advantageous for a CMOS type semiconductor device having both transistors.
[0045]
When a tantalum nitride film is used, the heat resistance of the hafnium oxide film and the zirconium oxide film is improved by using the tantalum nitride film as an electrode for the hafnium and zirconium oxide films. Therefore, it is desirable to use a tantalum nitride film from the viewpoint of heat resistance.
[0046]
Next, the gate electrode 1005 and the gate insulating film 1004 are sequentially planarized over the entire surface from above the silicon substrate 1001 by CMP. Thereby, the gate electrode 1105 and the gate insulating film 1004 are formed so as to be embedded in the recess.
[0047]
Next, as shown in FIG. 5B, contact holes 1017 are formed in the interlayer insulating film 1012 by using a well-known technique, and thereafter, lead wires 1013, 1014, and 1015 are sequentially formed.
[0048]
First, an interlayer insulating film 1012 is formed on the silicon substrate 1001. Thereafter, contact holes 1017 reaching the source diffusion layer, the drain diffusion layer, and the gate electrode are formed in the first film 1105, the second film 1106, and the interlayer insulating film 1012.
[0049]
Next, a titanium nitride film that is a barrier film and a tungsten film that is a conductor film are sequentially formed over the interlayer insulating film 1012 in which the contact holes 1017 are formed. Thereafter, the tungsten film and the titanium nitride film are sequentially processed to form lead wirings 1013, 1014, and 1015 connected to the source diffusion layer, the drain diffusion layer, and the gate electrode, thereby completing the semiconductor device of the first embodiment. .
[0050]
In this embodiment, a BPSG film is used as the doped oxide film for the first film 1105, an NSG film is used as the non-doped oxide film for the second film 1106, and the dummy gate pattern 1100 is formed of a polysilicon film. Therefore, when the polysilicon film that is the dummy gate pattern 1100 is removed, the second film 1106 is a material that can have an etching selectivity with respect to the dummy gate pattern 1100. Therefore, the second film 1106 is hardly etched, and the film loss can be prevented.
[0051]
In other words, the material for forming the second film 1106 and the dummy gate pattern 1100 may be selected so that the etching rate of the second film 1106 is lower than the etching rate of the material for forming the dummy gate pattern 1100. .
[0052]
In order to improve the embedding characteristics in the vicinity of the dummy gate pattern 1100, the first film 1105 is a doped oxide film that is excellent in processing and easily flattened like a high-concentration BPSG film. In general, the etching rate of the doped oxide film is high, but by forming the second film 1106, the first film 1105 is protected from the etching of the polysilicon film.
[0053]
In other words, the first film 1105 can be used even when the etching rate is high, and the embedding characteristics of the first film 1105 can be improved in the vicinity of the dummy gate pattern 1100. Therefore, the second film 1106 is also formed flat, and the second film 1106 can protect regions other than the dummy gate pattern 1100 in a self-aligning manner.
[0054]
As described above, according to the present embodiment, when the dummy gate pattern is removed, it is possible to prevent the interlayer insulating film from being significantly reduced, and to protect regions other than the dummy gate pattern in a self-aligning manner.
[0055]
In addition, high temperature processing such as heat treatment process for activating the source and drain and reflow process of the interlayer insulating film can be performed before the formation of the high dielectric film as the gate insulating film. Therefore, deterioration of the gate insulating film such as an increase in leakage current can be suppressed.
[0056]
Further, the thickness of the gate insulating film can be made smaller than a dimension in which the channel length of the transistor is determined by the limit of lithography, and the performance of the transistor can be improved by shortening the channel.
[0057]
(Second Embodiment)
A method for manufacturing a semiconductor device having a gate insulating film according to the second embodiment of the present invention will be described below with reference to FIGS. The second embodiment is a modification of the first embodiment, and the steps shown in FIGS.
[0058]
As shown in FIG. 6A, after forming the gate insulating film 1004 only on the bottom surface of the recess, the gate electrode 1005 is formed so as to be embedded in the recess. Here, as in the first embodiment, a high dielectric film is formed on the gate insulating film 1004 and a tungsten film is formed on the gate electrode.
[0059]
First, a hafnium oxide film which is a high dielectric film functioning as the gate insulating film 1004 is selectively formed on the silicon substrate 1001 only on the bottom surface of the recess. Here, long throw sputter deposition with high directivity is performed using the hafnium oxide itself as a target. As a result, the hafnium oxide film 1004 is formed with a film thickness of about 3 nm only on the bottom surface of the recess. Here, long throw sputter deposition is used for hafnium oxide film deposition, but other highly directional deposition techniques such as collimation sputter deposition may be used.
[0060]
Next, as in the first embodiment, a tungsten film is formed as a gate electrode 1005 in the recess. Here, a tungsten film was formed to a thickness of about 100 nm over the second film 1106. Thereafter, the gate electrode 1005 is planarized over the entire surface from above the silicon substrate 1001 by CMP. Thereby, the gate electrode 1005 is formed so as to be embedded in the recess.
[0061]
Next, as shown in FIG. 6B, in the same manner as in the first embodiment, an interlayer insulating film 1012, a contact hole 1017, and lead wirings 1013, 1014, and 1015 are sequentially formed to form the second embodiment. This completes the semiconductor device.
[0062]
As described above, according to the present embodiment, in addition to the same effects as those of the first embodiment, the gate insulating film 1004 is formed only on the bottom surface of the gate electrode 1005. ) Can be formed with good controllability regardless of the thickness of the gate insulating film, and therefore, variations in transistor characteristics can be reduced. In addition, it is preferable that the dielectric constant be increased only on the bottom surface of the recess, and the other portions should have a lower dielectric constant in consideration of the capacitance delay effect. If a hafnium oxide film is deposited only on the bottom surface of the recess, the characteristics of the transistor can be improved.
[0063]
(Other embodiments)
In this embodiment, a high dielectric film is used as the gate insulating film, but other insulating films such as a silicon oxide film or a silicon nitride oxide film can also be applied.
[0064]
When a high dielectric film such as a hafnium oxide film is used as the gate insulating film, a silicon nitride film may be formed between the semiconductor substrate and the gate insulating film.
[0065]
The high dielectric film used in the present embodiment is a film having a relative dielectric constant larger than that of silicon oxide. For example, aluminum (Al), zirconium (Zr), hafnium (Hf), tantalum (Ta), An oxide film selected from one or more of titanium (Ti), lanthanum (La) and the like is desirable. In particular, it is desirable to select an oxide of zirconium, hafnium, tantalum or the like from the advantage of relative permittivity. In the present embodiment, hafnium and zirconium can use zirconium oxide instead of hafnium oxide from the viewpoint of chemical similarity. Instead of these, a hafnium-zirconium mixed oxide can be used. Further, the hafnium oxide or zirconium oxide may be a pure oxide, and hafnium oxynitride, zirconium oxynitride or hafnium oxynitride silicon, and zirconium oxynitride silicon also have a high relative dielectric constant and are good. Therefore, it can be used in place of the hafnium oxide of this embodiment.
[0066]
【The invention's effect】
As described above, the method of manufacturing a semiconductor device according to the present invention can prevent a significant decrease in the interlayer insulating film when removing the dummy gate pattern, and can self-align regions other than the dummy gate pattern. Can be protected.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a manufacturing process of a semiconductor device according to a first embodiment of the invention.
FIG. 2 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the first embodiment of the invention.
FIG. 3 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the first embodiment of the invention.
FIG. 4 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the first embodiment of the invention.
FIG. 5 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the first embodiment of the invention.
FIG. 6 is a cross-sectional view showing a manufacturing process of a semiconductor device according to a second embodiment of the present invention.
[Explanation of symbols]
1001 Semiconductor substrate
1002 Element isolation layer
1003 Gate electrode pattern
1004 Hafnium oxide film (gate insulating film)
1005 Tungsten film (gate electrode)
1006, 1007 Low-concentration impurity diffusion layer
1010,1011 High concentration impurity diffusion layer
1012 Interlayer insulating film
1013, 1014, 1015 Lead wiring
1100 Dummy gate pattern
1101 Silicon oxide film (underlying film)
1102 Polysilicon film
1104 Silicon oxide film (side wall)
1105 BPSG film (first film)
1106 NSG film (second film)
1107 channel region

Claims (2)

Forming a silicon oxide film on the semiconductor substrate (a);
A step (b) of forming a polysilicon film on the silicon oxide film;
Etching the silicon oxide film and the polysilicon film to form a dummy gate pattern;
Forming a sidewall made of a silicon oxide film on the sidewall of the dummy gate pattern (d);
A step (e) of forming a first film made of a BPSG film on the semiconductor substrate, the sidewall and the dummy gate pattern;
The first film, the step (f) to remove before Symbol dummy gate pattern is exposed about half,
Forming a second film made of a non-doped silicon oxide film on the first film, the sidewall and the dummy gate pattern (g);
Flattening the second film until at least the dummy gate pattern is exposed; and
(I) removing the silicon oxide film of the dummy gate pattern after selectively removing the polysilicon film of the dummy gate pattern with respect to the second film;
Forming a gate insulating film on the inner wall of the recess from which the dummy gate pattern has been removed;
And a step (k) of forming a gate electrode in the recess in which the gate insulating film is formed. The step (j)
The method for manufacturing a semiconductor device according to claim 1, wherein the gate insulating film is formed only on a bottom surface of the recess.

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