JP2010272598A - Semiconductor device, and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent reduction in a resistance value of a silicon resistive element in a semiconductor device including a resistive element on a substrate. <P>SOLUTION: A semiconductor device 1 includes a MOS transistor having a MIPS structure and a silicon resistive element on a substrate 10. The resistive element includes: a metallic film 28 formed on the substrate 10; an insulating film 30 formed on the metallic film 28; and a silicon layer 37 formed on the insulating film 30. The insulating film 30 includes at least one selected from among a silicon oxide film, a silicon nitride film, HfSiON, HfO<SB>2</SB>, ZrO<SB>2</SB>, HfAlO and Al<SB>2</SB>O<SB>3</SB>. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device including a resistance element and a manufacturing method thereof.

  A structure using a polysilicon resistor is known as a resistance element in a semiconductor device. A predetermined resistance value can be obtained by doping polysilicon with impurities. For example, Patent Document 1 discloses a technique in which a polysilicon resistance element in a semiconductor device is formed on a field insulating film in the same manufacturing process as a gate electrode made of polysilicon of a MOSFET (Metal-Oxide Field Effect Transistor). Has been.

  On the other hand, with the progress of miniaturization of LSIs, there is a problem of deterioration of drive current due to depletion of polysilicon gate electrodes constituting each MOSFET. Therefore, a technique for avoiding depletion of the electrode by using a metal gate electrode has been studied. For example, Patent Document 2 discloses a MIPS (Metal Inserted Poly-Silicon Stacks) structure in which a metal gate electrode is inserted between a high-k film and a polysilicon gate electrode as one of the structures using a metal gate electrode. Has been.

JP 2004-179490 A JP 2007-19400 A

  In the technique of Patent Document 1, the polysilicon resistance element is formed in the same manufacturing process as the MOSFET. For this reason, when the MIPS structure of Patent Document 2 is simply applied to the technique of Patent Document 1, there arises a problem that the resistance value of the polysilicon resistance element is lowered. This is due to the following reason.

  FIG. 16A is a cross-sectional view showing a configuration of a polysilicon resistance element having a configuration similar to that of Patent Document 1. FIG. FIG. 16B is a cross-sectional view showing a configuration of a polysilicon resistance element when it is assumed that the MIPS structure of Patent Document 2 is simply applied to the technique of Patent Document 1.

  In the case of forming a polysilicon resistance element, a polysilicon 106 is formed on the element isolation region 104. In this case, a current flows through the polysilicon 106 as shown in FIG. However, in the polysilicon resistance element of FIG. 16B, since the metal electrode 114 exists under the polysilicon 106, most of the current flows through the metal electrode 114 having a lower resistance than the polysilicon 106. Therefore, the resistance is lowered.

  According to the present invention, there is provided a semiconductor device including a resistive element on a substrate, wherein the resistive element is provided on a metal film, an insulating film provided on the metal film, and the insulating film. There is provided a semiconductor device comprising a silicon resistance layer.

  In addition, according to the present invention, there is provided a method for manufacturing a semiconductor device including a resistance element on a substrate, the step of forming a metal film on the substrate, and the step of forming an insulating film on the metal film. And a step of forming a silicon layer on the insulating film, wherein the resistance element includes the metal film, the insulating film, and the silicon layer.

  According to the above configuration, since the insulating film is interposed between the silicon resistance layer and the metal film constituting the resistance element, it is possible to prevent a decrease in the resistance value by preventing a current from flowing through the metal film. it can.

  ADVANTAGE OF THE INVENTION According to this invention, the fall of the resistance value of a silicon resistance element can be prevented in the semiconductor device provided with a resistance element on a board | substrate. Moreover, the temperature change of the resistance value of the resistance element can be reduced.

It is sectional drawing which shows the semiconductor device of 1st Embodiment by this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device of 1st Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device of 1st Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device of 1st Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device of 1st Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device of 1st Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device of 1st Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device of 1st Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device of 1st Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device of 1st Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device of 1st Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device of 1st Embodiment. It is sectional drawing which shows the semiconductor device of 2nd Embodiment by this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device of 2nd Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device of 2nd Embodiment. (A) is sectional drawing which shows the conventional resistive element. (B) is sectional drawing explaining the subject of this application.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same components are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

(First embodiment)
FIG. 1 is a cross-sectional view showing a semiconductor device 1 according to the first embodiment. The semiconductor device 1 includes an N ⁺ resistance element 100 and a P ⁺ resistance element 102 on a substrate 10. In the present embodiment, the substrate 10 is a semiconductor substrate.

The N ⁺ resistance element 100 includes a gate insulating film 65 provided on the substrate 10, a metal film 28 provided on the gate insulating film 65, an insulating film 30 provided on the metal film 28, And an N ⁺ silicon layer (silicon resistance layer) 35 provided on the insulating film 30. In the present embodiment, the N ⁺ resistance element 100 has a gate insulating film 65 located under the metal film 28. The gate insulating film 65 is formed on the element isolation insulating film 14.

The N ⁺ resistance element 100 has a contact plug 80 (first contact plug) and a contact plug 82 (second contact plug) that are spaced apart from each other on the silicon layer. A silicide layer 72 is interposed between the contact plug 80 and the silicon layer and between the contact plug 82 and the silicon layer (silicon resistance layer) 35. However, the silicide layer 72 is not formed in a region located between the contact plugs 80 and 82 in the silicon layer 35 in plan view.

The P ⁺ resistance element 102 includes a gate insulating film 65 provided on the substrate 10, a metal film 28 provided on the gate insulating film 65, an insulating film 30 provided on the metal film 28, And a P ⁺ silicon layer (silicon resistance layer) 37 provided on the insulating film 30.

The P ⁺ resistance element 102 has a contact plug 80 (first contact plug) and a contact plug 82 (second contact plug) arranged on the silicon layer 37 at a distance from each other. A silicide layer 73 is interposed between the contact plug 80 and the silicon layer 37 and between the contact plug 82 and the silicon layer. However, the silicide layer 73 is not formed in a region of the silicon layer 37 located between the contact plugs 80 and 82 in plan view.

The substrate 10 of the semiconductor device 1 has an element isolation region where the element isolation insulating films 12 and 14 are formed and an element formation region where an active element such as a transistor is formed. At least one of the N ⁺ resistance element 100 and the P ⁺ resistance element 102 is formed in at least a part of the element isolation region. In the example shown in the figure, both the N ⁺ resistance element 100 and the P ⁺ resistance element 102 are formed. An N channel MOSFET and a P channel MOSFET are formed in the element formation region. The N channel MOSFET and the P channel MOSFET have a metal film 28 that is a metal gate electrode.

  The N-channel MOSFET includes a P-type well 16, a gate insulating film 64 provided in the element formation region, a metal film 28 provided on the gate insulating film 64, and a silicon electrode 35 provided on the metal film 28. And an extension area 48 and a deep SD area 58. That is, the N channel MOSFET has a MIPS structure. A silicide layer 72 is formed on the silicon electrode 35 and the Deep SD region 58. The gate electrode 66 of the N-channel MOSFET has a metal film 28 that is a metal gate electrode, a silicon electrode 35, and a silicide layer 72.

  The P-channel MOSFET includes an N-type well 18, a gate insulating film 65 provided in the element formation region, a metal film 28 provided on the gate insulating film 65, and a silicon layer 37 provided on the metal film 28. And an extension area 52 and a deep SD area 62. The P channel MOSFET also has a MIPS structure like the N channel MOSFET. A silicide layer 73 is formed on the silicon layer 37 and the Deep SD region 62. The gate electrode 67 of the P-channel MOSFET has a metal film 28 that is a metal gate electrode, a silicon layer 37, and a silicide layer 73.

  The P-channel MOSFET and the N-channel MOSFET are connected to contact plugs 78 embedded in the interlayer insulating film 76, respectively.

  Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the cross-sectional views of FIGS.

  First, as shown in FIG. 2A, element isolation insulating films 12 and 14 are formed on a substrate 10. As the substrate 10, for example, a silicon substrate can be used. The formation method of the element isolation insulating films 12 and 14 is STI (Shallow Trench Isolation). Next, the P-type well 16 is formed in the region where the N-channel MOSFET is formed, and the N-type well 18 is formed in the region where the P-channel MOSFET is formed.

  Next, as shown in FIG. 2B, a 1.0 nm oxynitride film is formed as the interface insulating film 20. The interfacial insulating film 20 is formed by performing plasma nitridation after forming a silicon oxide film by, for example, sulfuric acid / hydrogen peroxide mixture, ozone water, hydrochloric acid / ozone water, and after thermal oxidation.

  Thereafter, as shown in FIG. 2C, a La film 22 is formed on the entire surface of the substrate 10 by sputtering. The film thickness of the La film 22 is in the range of 0.1 nm to 2.0 nm. La is a metal for controlling the threshold voltage of the N-channel MOSFET. In addition to La, Dy can also be used.

  Then, as shown in FIG. 3A, a resist mask 24 is formed. Thereafter, the La film on the N-type well 18 and the element isolation insulating film 14 is removed by wet processing. Diluted hydrochloric acid is used for the wet treatment. Then, as shown in FIG. 3B, after removing the La film, the resist mask 24 is removed by an ashing process.

Next, a high dielectric constant gate insulating film 26 is formed as shown in FIG. The high dielectric constant gate insulating film 26 is an insulating film selected from, for example, HfO ₂ , ZrO ₂ , HfSiON, La ₂ O ₃ , and HfAlO. The film thickness is 1.0 nm or more and 5.0 nm or less. The high dielectric constant gate insulating film 26 can be formed using any one of a CVD method, an AL (Atomic Layer) CVD method, and a sputtering method. Subsequently, a metal film 28 that is a metal gate electrode is formed on the high dielectric constant gate insulating film 26. The metal film 28 is at least one metal selected from, for example, TiN, W, TaN, TaSiN, Ru, TiAl, and Al. The film thickness of the metal film 28 is 1.0 nm or more and 20.0 nm or less.

Next, as shown in FIG. 4A, an insulating film 30 is formed on the metal film 28. As a material of the insulating film 30, a silicon oxide film, a silicon nitride film, HfSiON, HfO ₂ , ZrO ₂ , HfAlO, Al ₂ O ₃ or the like can be used. The thickness of the insulating film 30 is 1 to 20 nm. As a method for forming the insulating film 30, a CVD method, a sputtering method, or the like can be used.

  Subsequently, a resist mask 32 is formed as shown in FIG. 4B, and openings located on the N-type well 18 region and the P-type well 16 region are formed in the resist mask 32. Next, as shown in FIG. 4C, the insulating film 30 in the N-type well 18 region and the P-type well 16 region is removed by etching using the resist mask 32 as a mask. In this state, the metal film 28 in the N-type well 18 region and the P-type well 16 region is not covered with the insulating film 30. Thereafter, the resist mask 32 is removed.

  Then, as shown in FIG. 5A, a silicon layer 34 is formed on the entire surface including the metal film 28 as the metal gate electrode and the insulating film 30 in the N-type well 18 region and the P-type well 16 region. The silicon electrode in this embodiment is amorphous silicon. The film thickness of amorphous silicon is 10 nm or more and 100 nm or less. Polysilicon may be used as the material of the silicon layer 34.

Next, as shown in FIG. 5B, a resist mask 36 is formed. The resist mask 36 has openings in each of the N-type well 18 region and the region where the P ⁺ resistance element is formed. Next, boron (B), which is a P-type impurity, is implanted into the silicon layer 34 using the resist mask 36 as a mask. The injection condition is, for example, B 2 keV 5E15 atoms / cm ² . The resistance value of the P ⁺ resistance element 102 can be adjusted by the injection amount at this time.

Thereafter, after removing the resist mask 36, a resist mask 38 is formed as shown in FIG. The resist mask 38 has openings in the P-type well 16 region and the region where the N ⁺ resistance element is formed. Next, phosphorus (P) which is an N-type impurity is implanted into the silicon layer 34 using the resist mask 38 as a mask. The implantation conditions are, for example, P 4 keV 5E15 atoms / cm ² . The resistance value of the N ⁺ resistance element 100 can be adjusted by the injection amount at this time.

  Subsequently, as shown in FIG. 6A, a hard mask 40 is formed on the silicon layer 34, and a resist mask 42 is further formed on the hard mask 40. The hard mask 40 is a film selected from a silicon oxide film and a silicon nitride film.

Next, by dry etching and wet processing, gate electrodes 66 and 67 of the N-channel MOSFET and P-channel MOSFET, the N ⁺ resistance element 100, and the P ⁺ resistance element 102 are formed as shown in FIG. 6B.

Then, a silicon nitride film is formed by ALCVD, and an offset spacer 44 is formed on the gate electrodes 66 and 67, the N ⁺ resistance element 100, and the P ⁺ resistance element 102 as shown in FIG. The offset spacer 44 may be a silicon oxide film or a stacked structure of silicon nitride film / silicon oxide film.

Thereafter, as shown in FIG. 7B, after covering the N-type well 18, the N ⁺ resistance element 100, and the P ⁺ resistance element 102 with a resist mask 46, an extension is formed in the N-channel MOSFET formation region of the P-type well 16. Region 48 is formed by ion implantation. The implantation conditions are, for example, BF ₂ 50 keV 3E13 atoms / cm ² 30 degrees and As 2 keV 8E14 atoms / cm ² 0 degrees.

Subsequently, as shown in FIG. 8A, similarly, after covering the P-type well 16, the N ⁺ resistance element 100, and the P ⁺ resistance element 102 with the resist mask 50, an extension region 52 is formed in the N-type well 18. It is formed by ion implantation. The implantation conditions are, for example, As 50 keV 3E13 atoms / cm ² 30 degrees and BF ₂ 3 keV 8E14 atoms / cm ² 0 degrees.

  Next, a silicon nitride film or a silicon oxide film is formed, and sidewall spacers 54 are formed by dry etching as shown in FIG.

Thereafter, as shown in FIG. 9A, the N-type well 18, the N ⁺ resistance element 100, and the P ⁺ resistance element 102 are covered with a resist mask 56, and then a deep SD region 58 is ion-implanted into the P-type well 16. To form. The implantation conditions are, for example, Ge 30 keV 5E14 atoms / cm ² 0 degrees, As 15 keV 3E15 atoms / cm ² 0 degrees, and P 20 keV 5E13 atoms / cm ² 0 degrees.

Subsequently, as shown in FIG. 9B, similarly, after covering the P-type well 16, the N ⁺ resistance element 100, and the P ⁺ resistance element 102 with the resist mask 60, the Deep SD region 62 is formed in the N-type well 18. It is formed by ion implantation. The implantation conditions are, for example, Ge 30 keV 5E14 atoms / cm ² 0 degrees, B 7 keV 5.0E13 atoms / cm ² 0 degrees, and BF ₂ 9 keV 2E15 atoms / cm ² 0 degrees.

  Then, after removing the resist mask 60, heat treatment is performed to activate the extension and deep SD regions. The heat treatment conditions are, for example, 1050 ° C. and approximately 0 seconds. At this time, La in the N channel MOSFET formation region diffuses into the high dielectric constant gate insulating film 26. Thereby, the La-containing high dielectric constant insulating film 27 is formed in the N-channel MOSFET.

  Next, as shown in FIG. 10A, a silicide block layer 68 is formed. The silicide block layer 68 is an insulating film selected from a silicon oxide film, a silicon nitride film, and a silicon oxide film / silicon nitride film laminated film.

  Thereafter, as shown in FIG. 10B, a region where no silicide is formed is masked with a resist mask 70. The region where silicide is not formed is, for example, a region on the upper surface of each resistance element and a contact described later is not formed on each resistance element.

  Then, as shown in FIG. 11A, the silicide block layer 68 is selectively removed by performing dry etching using the resist mask 70 as a mask. Thereafter, the resist mask 70 is removed.

  Next, as shown in FIG. 11B, silicide layers 72 and 73 are formed. The silicide layers 72 and 73 use NiSi. The formation method of the silicide layers 72 and 73 is as follows. First, a NiPt film is formed on the entire surface by sputtering, a primary silicide layer is formed by heat treatment, and then the excess NiPt film is removed with aqua regia. Further, by performing heat treatment, silicide layers 72 and 73 that are NiPtSi films that are secondary silicide films are obtained. As the silicide layers 72 and 73, NiSi, PtSi, or the like can be used in addition to NiPtSi.

  Subsequently, as shown in FIG. 12A, a contact etching stopper film 74 is formed. The contact etching stopper film 74 is, for example, a silicon nitride film, and the film thickness is 10 nm or more and 100 nm or less. Then, as shown in FIG. 12B, an interlayer insulating film 76 made of a silicon oxide film is formed. Further, by forming the contact plugs 78, 80, 82, the semiconductor device 1 of FIG. 1 is obtained.

Next, the effect of this embodiment is demonstrated. In the N ⁺ resistance element 100 in the present embodiment, an insulating film 30 is interposed between the silicon layer and the metal film 28. Therefore, when a current flows from the first contact plug 80 to the second contact plug 82, the current does not flow through the metal film 28 but flows through the silicon layer 35. Therefore, the N ⁺ resistance element 100 can be sufficiently used as a resistance element without lowering the resistance value. The P ⁺ resistance element 102 of the present embodiment has exactly the same effect.

  In addition, the current flowing only through the silicon layer 35 without flowing through the metal film 28 also has an excellent effect that the temperature coefficient of the resistance value can be extremely reduced. This is because, in the case of metal, the temperature coefficient of resistivity is larger than that of silicon. Therefore, in the configuration in which the insulating film 30 is not provided between the silicon layer 35 and the metal film 28, most of the current flows in the metal film 28. This is because the temperature coefficient of the resistance value increases by flowing.

  The resistance element of the present embodiment has the same configuration as the N-channel MOSFET and P-channel MOSFET except that the insulating film 30 is interposed between the silicon layer and the metal film 28. Therefore, it can be manufactured simultaneously with the N-channel MOSFET and the P-channel MOSFET in the element formation region without complicating the manufacturing process. Therefore, the manufacturing cost can be reduced.

  In FIG. 16B, when the MIPS structure of Patent Document 2 is simply applied to the technique of Patent Document 1, it may be considered that the polysilicon resistance element is not provided with the metal electrode 114. However, in such a configuration, the height of the polysilicon resistance element becomes lower than that of a transistor (not shown) provided in the element formation portion. Such a difference in height causes a step in the subsequent interlayer insulating film forming process, which has an adverse effect. Furthermore, there is a problem that the manufacturing process becomes complicated.

  On the other hand, the resistance element of this embodiment has the same configuration as the N-channel MOSFET and P-channel MOSFET except that the insulating film 30 is interposed between the silicon layer and the metal film 28. The heights of the MOSFETs are substantially the same, and there is no influence on subsequent processes.

(Second Embodiment)
FIG. 13 is a cross-sectional view showing the semiconductor device 2 of the second embodiment. The semiconductor device 2 is different from the semiconductor device 1 according to the first embodiment in that a fuse element 104 is further provided on the element isolation insulating film 14.

The fuse element 104 in the semiconductor device 2 of the present embodiment includes a metal film 28, an insulating film 30 provided on the metal film 28, a silicon layer 34 provided on the insulating film 30, and a silicon layer 34. A silicide layer 75 covering at least a part of the upper surface. In the present embodiment, the silicon layer 34 is non-doped silicon. In the present embodiment, the fuse element 104 has a gate insulating film 65 located under the metal film 28. The gate insulating film 65 is formed on the element isolation insulating film 14.

  The fuse element 104 has contact plugs 80 (first contact plugs) and contact plugs 82 (second contact plugs) arranged on the silicide layer 75 so as to be spaced apart from each other. The contact plug 80 and the contact plug 82 are electrically connected by a silicide layer 75.

The fuse element 104 in the semiconductor device 2 of the present embodiment has the N ⁺ resistance element 100 in that the silicon layer 34 is non-doped and the contact plug 80 and the contact plug 82 are electrically connected by the silicide layer 75. And P ⁺ resistance element 102. Other than that, the configuration is the same as that of the N ⁺ resistance element 100 and the P ⁺ resistance element 102.

  In such a fuse element 104, when an overcurrent is passed between the contact plug 80 and the contact plug 82, the silicide layer is disilicided by the generated heat to increase the resistance, and the fuse is cut.

  Even in such a fuse element, the insulating film 30 is interposed between the silicon layer 34 and the metal film 28, whereby current can be prevented from flowing into the metal film 28. When the insulating film 30 is not provided, an overcurrent hardly flows through the silicide layer 75, so that the fuse is not easily cut. Further, even after the fuse is cut, a current flows between the contact plugs through the metal film 28. According to the configuration of the present embodiment, such a problem can be solved.

Next, a method for manufacturing the semiconductor device 2 will be described.
The semiconductor device 2 is manufactured by substantially the same process as the semiconductor device 1 of the first embodiment. The steps from FIG. 2A to FIG. 5A shown in the first embodiment are the same as those in the first embodiment. However, in the step of implanting P-type impurities into the silicon layer 34 (corresponding to FIG. 5B in the first embodiment), the fuse element formation region is covered with a resist mask 36 as shown in FIG. P-type impurities are not implanted. Similarly, in the step of implanting an N-type impurity into the silicon layer 34 (corresponding to FIG. 5C in the first embodiment), as shown in FIG. Cover and do not implant N-type impurities.

  Subsequently, the processes from FIG. 6A to FIG. 10A are also performed by the same processes as in the first embodiment. In the step of forming the silicide block layer 68, in this embodiment, the silicide block layer is not formed on the silicon layer 34 of the fuse element (FIG. 15A), and the silicide layer 75 is formed on the fuse element. It is formed on the entire surface of the silicon layer 34 (FIG. 15B). The subsequent steps are the same as those in the first embodiment.

  In the present embodiment, the silicide layer 75 is formed on the entire surface of the silicon layer 34 of the fuse element. However, the silicon layer 34 may be used as long as the contact plug 80 and the contact plug 82 are electrically connected. Needless to say, it is not necessary to form it on the entire surface.

1, 2 Semiconductor device 10 Semiconductor substrate 12 Element isolation insulating film (STI)
14 Device isolation insulating film (STI)
16 P-type well 18 N-type well 20 Interfacial insulating film 22 La film 24, 32, 36, 38, 42, 46, 50, 56, 60, 70 Resist mask 26 High dielectric constant gate insulating film 27 La-containing high dielectric constant gate Insulating film 28 Metal film 30 Insulating films 34, 35, 37 Silicon layer 40 Hard mask 44 Offset spacer 48 Extension region 52 Extension region 54 Side wall spacer 58 Deep SD region 62 Deep SD region 64 Gate insulating film 65 Gate insulating film 66 Gate electrode 67 Gate electrode 68 Silicide block layers 72, 73, 75 Silicide layer 74 Contact etching stopper film 76 Interlayer insulating film 78 Contact plug 80 Contact plug 82 Contact plug 100 N ⁺ resistance element 102 P ⁺ resistance element 10 4 Fuse element

Claims (10)

A semiconductor device comprising a resistive element on a substrate,
The resistance element is
A metal film,
An insulating film provided on the metal film;
A silicon resistance layer provided on the insulating film;
A semiconductor device comprising: The semiconductor device according to claim 1,
The semiconductor device has at least one selected from a silicon oxide film, a silicon nitride film, HfSiON, HfO ₂ , ZrO ₂ , HfAlO, and Al ₂ O _{3 as the} insulating film. The semiconductor device according to claim 1 or 2,
The semiconductor device according to claim 1, wherein the resistance element further includes a gate insulating film located between the substrate and the metal film. The semiconductor device according to claim 1,
The substrate is partitioned into an element isolation region and an element formation region,
The resistance element is provided in at least a part of the element isolation region,
The device forming region further includes a MOS transistor having a metal gate electrode. The semiconductor device according to claim 4,
The MOS transistor is
A gate insulating film provided in the element formation region of the substrate;
The metal gate electrode provided on the gate insulating film;
A silicon electrode provided on the metal gate electrode;
A semiconductor device comprising: The semiconductor device according to claim 1,
The resistance element includes a first contact plug and a second contact plug that are spaced apart from each other on the silicon resistance layer, and each of the first and second contact plugs and the silicon resistance layer. A semiconductor device having a silicide layer interposed therebetween. A method of manufacturing a semiconductor device comprising a resistive element on a substrate,
Forming a metal film on the substrate;
Forming an insulating film on the metal film;
Forming a silicon layer on the insulating film;
The resistance element includes the metal film, the insulating film, and the silicon layer. In the manufacturing method of the semiconductor device according to claim 7,
The substrate is partitioned into an element isolation region in which the resistance element is formed at least in part and an element formation region in which a MOS transistor is formed,
Forming the metal film on the substrate includes forming a metal film of the resistance element in the element isolation region and simultaneously forming a metal gate electrode of the MOS transistor in the element formation region;
In the step of forming the insulating film on the metal film, the insulating film is formed on the metal film of the resistance element in the element isolation region, and the insulating film is formed on the metal gate electrode Without
The step of forming the silicon layer on the insulating film includes forming a silicon resistance layer on the insulating film of the resistive element in the element isolation region and simultaneously forming the metal gate of the MOS transistor in the element forming region. Forming a silicon electrode on the electrode. In the manufacturing method of the semiconductor device according to claim 7 or 8,
A method of manufacturing a semiconductor device, further comprising a step of forming a gate insulating film on the substrate before the step of forming the metal film on the substrate. In the manufacturing method of the semiconductor device according to claim 9,
The step of forming the gate insulating film on the substrate forms a gate insulating film located under the metal film in the element isolation region and simultaneously forms a gate insulating film of the MOS transistor in the element forming region. A method for manufacturing a semiconductor device, comprising the step of:

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