JP2010056239A - Semiconductor device, and method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide technique for adjusting a threshold voltage of each of transistors differing in threshold voltages. <P>SOLUTION: A semiconductor device includes a semiconductor substrate, a gate insulating film provided on the semiconductor substrate, a gate electrode provided on the gate insulating film, and a plurality of kinds of field-effect transistor differing in threshold voltages, at least one kind of field-effect transistors having at least one kind of metal present in its gate insulating film. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a field effect transistor semiconductor device.

  One of the elements used in a semiconductor integrated circuit device is a MOS field effect transistor (MOSFET). In order to increase the speed and integration of semiconductor integrated circuit devices, MOSFETs are miniaturized according to scaling rules. By simultaneously reducing the height and lateral dimensions of the MOSFET, it is possible to improve the performance while keeping the device characteristics normal.

  In the next-generation MOSFET, use of a high dielectric constant (High-k) dielectric for the gate insulating film is being studied in order to reduce gate leakage current. A MOSFET using a high dielectric constant dielectric as the gate insulating film can increase the thickness of the gate insulating film while suppressing the gate leakage current while ensuring the same transistor performance.

For example, when an Hf-based material is used as the high dielectric constant gate insulating film, the concentration of Hf is increased to increase the dielectric constant. However, when the concentration of Hf is high, it is difficult to fabricate a device that is fixed with a high threshold voltage and has a low threshold voltage. Therefore, the threshold voltage is adjusted by reducing the channel impurity concentration of the transistor. There is also a technique related to adjustment of the threshold voltage.
JP 2006-093670 A

  In the conventional technique of adjusting the threshold voltage by lowering the channel impurity concentration of the transistor, problems such as punch-through occur. Punch-through is a phenomenon in which a depletion layer extending from a source and a depletion layer extending from a drain are connected. In the case where transistors with different threshold voltages are formed on the same substrate, adjusting the threshold voltage by adjusting the channel impurity concentration of each transistor causes an increase in the number of manufacturing steps. Therefore, there is a desire to adjust the threshold voltage by a method other than changing the channel impurity concentration of the transistor. The present disclosure has been made in view of the above problems, and an object thereof is to provide a technique for adjusting a threshold voltage for each transistor having a different threshold voltage.

  A semiconductor device according to an aspect of the present invention includes a semiconductor substrate, a gate insulating film provided on the semiconductor substrate, and a plurality of types of field effect types having different threshold voltages including a gate electrode provided on the gate insulating film. At least one type of field effect transistor including a transistor has at least one type of metal in the gate insulating film.

  The disclosed apparatus has an effect that the threshold voltage can be adjusted for each transistor having a different threshold voltage.

  Hereinafter, a semiconductor device and a manufacturing method thereof according to the best mode (hereinafter referred to as an embodiment) for carrying out the present invention will be described with reference to the drawings. The configuration of the following embodiment is an exemplification, and the disclosed semiconductor device and the manufacturing method thereof are not limited to the configuration of the embodiment.

<First Embodiment>
A semiconductor device and a manufacturing method thereof according to the first embodiment will be described with reference to FIGS. In the method for manufacturing a semiconductor device according to the first embodiment, first, an element isolation region 3 is formed on a semiconductor substrate 2 as shown in FIG. The semiconductor substrate 2 is, for example, a silicon substrate. In the present embodiment, a silicon substrate is used as the semiconductor substrate 2, but germanium (Ge) may be used. The element isolation region 3 can be formed on the semiconductor substrate 2 by using a method such as shallow trench isolation (STI) or LOCOS method.

  By forming a plurality of element isolation regions 3 on the semiconductor substrate 2, a region where a high speed MOSFET is formed on the semiconductor substrate 2, a region where a standard MOSFET is formed, and a region where a low leak MOSFET is formed Are defined respectively. In this embodiment, a MOSFET that requires high-speed operation is referred to as a High Speed MOSFET, a MOSFET that prioritizes low leakage current is referred to as a Low Leak MOSFET, and an intermediate MOSFET between a High Speed MOSFET and a Low Leak MOSFET is used. Called the standard MOSFET.

  The threshold voltages of High Speed MOSFET, Standard MOSFET and Low Leak MOSFET are different. The power supply voltage of the high speed MOSFET, the standard MOSFET, and the low leak MOSFET may be the same. The region where the High Speed MOSFET is formed is called the High Speed region, the region where the Standard MOSFET is formed is called the Standard region, and the region where the Low Leak MOSFET is formed is called the Low Leak region.

  Next, as shown in FIG. 1, impurities are ion-implanted into the semiconductor substrate 2 to form wells 4, 5 and 6 in the semiconductor substrate 2. When the wells 4, 5 and 6 are formed as n wells, n-type impurities are ion-implanted into the semiconductor substrate 2. The n-type impurity is, for example, phosphorus (P) or arsenic (As). When the wells 4, 5, and 6 are formed as p-wells, p-type impurities are ion-implanted into the semiconductor substrate 2. The p-type impurity is, for example, boron (B).

  Then, impurities for controlling the threshold voltage are ion-implanted into the wells 4, 5 and 6. When the wells 4, 5 and 6 are formed as n wells, n-type impurities are ion-implanted into the wells 4, 5 and 6. When the wells 4, 5 and 6 are formed as p-wells, p-type impurities are ion-implanted into the wells 4, 5 and 6.

The well 4 is ion-implanted with an impurity with a dose of 1 × 10 ¹² / cm ² to 1 × 10 ¹³ / cm ² at 10 to 40 keV. That is, impurities are ion-implanted so that the concentration of the channel impurity in the well 4 is 1 × 10 ¹² / cm ³ to 1 × 10 ¹³ / cm ³ .

The well 5 is ion-implanted with an impurity having a dose of 5 × 10 ¹² / cm ^{2 to} 5 × 10 ¹³ / cm ² at 10 to 40 keV. That is, impurities are ion-implanted so that the concentration of the channel impurity in the well 5 is 5 × 10 ¹² / cm ^{3 to} 5 × 10 ¹³ / cm ³ .

The well 6 is ion-implanted with an impurity having a dose of 1 × 10 ¹³ / cm ² to 1 × 10 ¹⁴ / cm ² at 10 to 40 keV. That is, impurities are ion-implanted so that the concentration of the channel impurity in the well 6 is 1 × 10 ¹³ / cm ³ to 1 × 10 ¹⁴ / cm ³ .

  The dose amount of the impurity implanted into the wells 4, 5 and 6 described above is an example, and the impurity may be implanted into the wells 4, 5 and 6 with other dose amounts.

Further, the dose amount of the impurity implanted into the wells 4, 5 and 6 may be the same. For example, ions of a dose of 1 × 10 ¹³ / cm ² may be implanted into the wells 4, 5 and 6. By making the dose amount of the impurity ion-implanted into the wells 4, 5 and 6 the same,
It is possible to perform ion implantation of the wells 4, 5 and 6 in one step.

  Next, as shown in FIG. 1, a gate insulating film 7 is formed on the semiconductor substrate 2. The gate insulating film 7 is a metal oxide, metal oxynitride, or metal nitride containing at least one of Hf, Si, Zr, La, Y, and Ta. That is, the gate insulating film 7 is a high dielectric constant insulating film containing a High-K material. The gate insulating film 7 may be in an amorphous state that is not crystallized.

The gate insulating film 7 is formed by using, for example, a chemical vapor deposition (CVD) method, an atomic layer deposition (ALD) method, or a physical vapor deposition (PVD) method. .

  The thickness of the gate insulating film 7 is 1.5 nm to 4 nm. However, this value is merely an example, and the film thickness of the gate insulating film 7 may be another value. By reducing the thickness of the gate insulating film 7, the electrical thickness can be reduced. By increasing the thickness of the gate insulating film 7, the dielectric constant of the gate insulating film 7 can be increased. For example, when hafnium silicate (HfSiO) is used as the material of the gate insulating film 7, the thickness of the gate insulating film 7 is preferably 2 nm to 3 nm.

  As shown in FIG. 2, a resist is applied on the gate insulating film 7 and mask exposure is performed to form a resist pattern 10. In this case, the resist pattern 10 is formed so as to cover a region other than the High Speed region. That is, the resist pattern 10 is formed so as to cover the standard area and the low leak area.

Next, as shown in FIG. 3, metal is deposited at 5 × 10 ¹³ atoms / cm ² to 1 × 10 ¹⁵ atoms / cm ² on the gate insulating film 7 in the High Speed region using the resist pattern 10 as a mask. . That is, the surface density of the metal deposited on the gate insulating film 7 in the High Speed region is set in the range of 5 × 10 ¹³ atoms / cm ² to 1 × 10 ¹⁵ atoms / cm ² . For example, metal is deposited on the gate insulating film 7 in the High Speed region by sputtering. The value of the surface density of the metal attached on the gate insulating film 7 in the High Speed region is an example, and the value of the surface density of the metal attached on the gate insulating film 7 in the High Speed region is another value. Good.

  Metals deposited on the gate insulating film 7 in the High Speed region are Hf, Zr, Al, La, Y, Ti, Ta, W, Ir, and Pt. Further, the type of metal deposited on the gate insulating film 7 may be one type or two or more types.

  Here, the dose amount of the impurity ion-implanted into the well 4 in the adjustment of the threshold voltage of the high speed MOSFET and the kind and surface density of the metal deposited on the gate insulating film 7 in the high speed region will be described. Here, a method of adjusting the threshold voltage of the high speed MOSFET to the predetermined voltage V1 will be described.

  The dose amount of the impurity ion-implanted into the well 4 and the kind and surface density of the metal deposited on the gate insulating film 7 in the High Speed region are determined according to the predetermined voltage V1. That is, the dose amount of the impurity ion-implanted into the well 4 for adjusting the threshold voltage of the high speed MOSFET to the predetermined voltage V1, the type and surface density of the metal deposited on the gate insulating film 7 in the high speed region are determined. To do.

  In the step described with reference to FIG. 1, impurities are ion-implanted into the well 4 with the dose determined above. In the process described with reference to FIG. 3, metal is deposited on the gate insulating film 7 in the High Speed region with the metal type and surface density determined above.

  It should be noted that the impurity dose for adjusting the threshold voltage of the high speed MOSFET to the predetermined voltage V1, the kind of metal deposited on the gate insulating film 7 in the high speed region, and the surface density are obtained in advance by experiments. Just keep it. In addition, values obtained by experiments may be mapped or databased.

For example, when the predetermined voltage V1 is 0.1 V, the impurity dose is set to 1 × 10 ¹² / cm ² −1.
It determines from the range of * 10 < ¹³ > / cm < ² >. Then, the type and surface density of the metal are determined based on the determined impurity dose. The metal type is determined from at least one of Hf, Zr, Al, La, Y, Ti, Ta, W, Ir, and Pt. The surface density of the metal is determined from the range of 5 × 10 ¹³ atoms / cm ² to 1 × 10 ¹⁵ atoms / cm ² .

By implanting ions into the High Speed region with the determined dose amount, and depositing metal on the gate insulating film 7 in the High Speed region with the determined metal type and surface density, the High Speed region
The threshold voltage of the speed MOSFET can be adjusted to the desired voltage.

Then, as shown in FIG. 4, the resist pattern 10 is peeled off. The resist pattern 10 can be stripped by ashing using O ₂ plasma, a method using a resist stripping solution, or the like.

  Next, heat treatment is performed on the semiconductor substrate 2 and the gate insulating film 7. The heat treatment conditions for the semiconductor substrate 2 and the gate insulating film 7 are a heat treatment temperature of 650 ° C. to 1050 ° C. and a treatment time of less than 10 seconds. Further, the heat treatment on the semiconductor substrate 2 and the gate insulating film 7 may be performed before the resist pattern 10 is peeled off.

  Here, heat treatment for the semiconductor substrate 2 and the gate insulating film 7 will be described. The region where the metal deposited on the gate insulating film 7 in the High Speed region changes depending on the heat treatment conditions for the semiconductor substrate 2 and the gate insulating film 7. Depending on the heat treatment conditions for the semiconductor substrate 2 and the gate insulating film 7, the metal diffuses inside the gate insulating film 7 in the High Speed region, and the metal exists inside the gate insulating film 7 in the High Speed region. Depending on the heat treatment conditions for the semiconductor substrate 2 and the gate insulating film 7, the metal does not diffuse inside the gate insulating film 7 in the High Speed region, and the metal exists on the upper surface of the gate insulating film 7 in the High Speed region.

  Of the heat treatment conditions described above, by setting the heat treatment temperature low and shortening the treatment time, it becomes possible to make the metal exist on the upper surface of the gate insulating film 7 in the High Speed region or in the vicinity thereof.

In addition, among the heat treatment conditions described above, by setting the heat treatment temperature high and lengthening the treatment time, it becomes possible to make the metal exist below the gate insulating film 7 in the High Speed region. As described above, by controlling the heat treatment conditions for the semiconductor substrate 2 and the gate insulating film 7, it is possible to change the metal existence region in the gate insulating film 7 in the High Speed region. When the metal is present inside the gate insulating film 7 in the High Speed region, the volume density of the metal present in the gate insulating film 7 in the High Speed region is 5 × 10 ¹³ atoms / cm ³ to The range is 1 × 10 ¹⁵ atoms / cm ³ .

  Depending on the type of metal deposited on the gate insulating film 7 in the High Speed region, the threshold voltage of the High Speed MOSFET can be easily adjusted by making the metal exist on the upper surface of the gate insulating film 7 in the High Speed region. There is a case. Also, depending on the type of metal deposited on the high speed gate insulating film 7, the presence of metal inside the high speed gate insulating film 7 may facilitate the adjustment of the threshold voltage of the high speed MOSFET. is there.

  Therefore, the heat treatment conditions for the semiconductor substrate 2 and the gate insulating film 7 may be determined according to the type of metal deposited on the high speed gate insulating film 7. Further, the heat treatment may not be performed on the semiconductor substrate 2 and the gate insulating film 7 depending on the type of metal deposited on the high speed gate insulating film 7.

  Next, as shown in FIG. 5, polysilicon 11 is formed on the gate insulating film 7. The polysilicon 11 can be formed on the gate insulating film 7 by thermally decomposing silane gas in nitrogen gas by the CVD method. 5 to 15 show examples in which metal is present inside the gate insulating film 7.

  Then, as shown in FIG. 6, patterning is performed on the polysilicon 11 by photolithography and dry etching to form gate electrodes 12, 13, and 14 on the gate insulating film 7. More specifically, the gate electrode 12 is formed in the High Speed region, the gate electrode 13 is formed in the Standard region, and the gate electrode 14 is formed in the Low Leak region.

  As described above, when metal is present on the upper surface of the gate insulating film 7 by controlling the heat treatment conditions for the semiconductor substrate 2 and the gate insulating film 7, the metal is present at the interface between the gate electrode 12 and the gate insulating film 7. Will exist.

Next, as shown in FIG. 7, a lightly doped drain (LDD) region 15 and a sidewall insulating film 16 are formed. Specifically, LDD regions 15 are formed in the High Speed region, Standard region, and Low Leak region by injecting impurities into the wells 4, 5 and 6 using the gate electrodes 12, 13 and 14 as masks. Here, for example, impurities are ion-implanted under the conditions of a dose of 1 × 10 ¹³ / cm ² and an acceleration energy of 10 keV to form the LDD region 15. When the wells 4, 5 and 6 are formed as n-wells, p-type impurities are ion-implanted into the wells 4, 5 and 6. When the wells 4, 5 and 6 are formed as p-wells, n-type impurities are ion-implanted into the wells 4, 5 and 6.

  Then, a silicon oxide film is deposited on the semiconductor substrate 2 including the High Speed region, the Standard region, and the Low Leak region so as to cover the gate electrodes 12, 13, and 14. A silicon oxide film can be deposited on the semiconductor substrate 2 by using the CVD method. Next, anisotropic dry etching (etchback) is performed using the gate electrodes 12, 13 and 14 as a mask. By performing etch back, sidewall insulating films 16 are formed on the respective side surfaces of the gate electrodes 12, 13 and 14.

Then, as shown in FIG. 8, source / drain regions 17 and silicide 18 are formed. Specifically, by implanting impurities into the wells 4, 5 and 6 using the gate electrodes 12, 13 and 14 and the sidewall insulating film 17 as a mask, source / drains are formed in the High Speed region, Standard region and Low Leak region. Region 17 is formed. Here, for example, impurities are ion-implanted under the conditions of a dose amount of 5 × 10 ¹³ / cm ² and an acceleration energy of 15 keV so that the impurity concentration is higher than that of the LDD region, and the source / A drain region 17 is formed. When the wells 4, 5 and 6 are formed as n-wells, p-type impurities are ion-implanted into the wells 4, 5 and 6. When the wells 4, 5 and 6 are formed as p-wells, n-type impurities are ion-implanted into the wells 4, 5 and 6.

Next, heat treatment is performed after depositing a metal capable of forming the silicide 18 on the semiconductor substrate 2 including the High Speed region, the Standard region, and the Low Leak region. The metal capable of forming the silicide 18 is, for example, cobalt or nickel. By using the sputtering method, a metal capable of forming the silicide 18 can be deposited on the semiconductor substrate 2. By performing the heat treatment, the metal capable of forming the silicide 18 reacts with silicon, and the silicide 18 is formed on the gate electrodes 12, 13 and 14 and on the source / drain regions 17. By forming the silicide 18, the resistance of the gate electrodes 12, 13 and 14 and the source / drain region 17 can be reduced.

Then, as shown in FIG. 9, an interlayer insulating film 19 is formed on the semiconductor substrate 2 including the High Speed region, the Standard region, and the Low Leak region, and the interlayer insulating film 19 is formed by a chemical mechanical polishing (CMP) method. To flatten. The interlayer insulating film 19 is, for example, a silicon oxide film (SiO ₂ ). The interlayer insulating film 19 can be formed on the semiconductor substrate 2 by a CVD method using silane gas and oxygen gas.

  Next, as shown in FIG. 10, contact plugs 20 and wirings 21 are formed. Specifically, a contact hole is formed in the interlayer insulating film 19 by photolithography and etching. Then, after depositing, for example, tungsten (W) on the interlayer insulating film 19, the contact plug 20 is formed in the interlayer insulating film 19 by polishing tungsten by CMP. Next, a metal such as aluminum (Al) or copper (Cu) is deposited on the interlayer insulating film 19, and wirings 21 are formed on the interlayer insulating film 19 by photolithography and etching.

Then, as shown in FIG. 11, an interlayer insulating film 22, a contact plug 23, and a wiring 24 are formed. Specifically, an interlayer insulating film 22 is formed on the wiring 21, and the interlayer insulating film 22 is planarized by a CMP method. The interlayer insulating film 22 is, for example, a silicon oxide film (SiO ₂ ). The interlayer insulating film 22 can be formed on the wiring 21 by a CVD method using silane gas and oxygen gas. The contact plug 23 and the wiring 24 are formed in the same manner as the contact plug 20 and the wiring 21.

  In this manner, by forming the interlayer insulating film 22, the contact plug 23, and the wiring 24, it is possible to form a multilayer wiring. Further, if necessary, the process of forming the interlayer insulating layer and the wiring layer may be repeated.

  In this embodiment, an example is shown in which the threshold voltage of the high speed MOSFET is adjusted to a desired voltage. However, the present invention is not limited to this, and the threshold voltage of the standard MOSFET or the threshold voltage of the low leak MOSFET is adjusted to the desired voltage. It is also possible to do. An example of adjusting the threshold voltage of the standard MOSFET or the threshold voltage of the low leak MOSFET to a desired voltage is shown below.

<Adjustment of threshold voltage of standard MOSFET>
When adjusting the threshold voltage of the standard MOSFET to a desired voltage, after performing the process described in FIG. 1, a resist is applied on the gate insulating film 7 and mask exposure is performed as shown in FIG. Then, a resist pattern 30 is formed. In this case, the resist pattern 30 is formed so as to cover areas other than the Standard area. That is, the resist pattern 30 is formed so as to cover the high speed region and the low leak region.

Next, as shown in FIG. 13, metal is deposited at 5 × 10 ¹³ atoms / cm ² to 1 × 10 ¹⁵ atoms / cm ² on the gate insulating film 7 in the Standard region using the resist pattern 30 as a mask. That is, the surface density of the metal deposited on the gate insulating film 7 in the Standard region is set in the range of 5 × 10 ¹³ atoms / cm ² to 1 × 10 ¹⁵ atoms / cm ² . For example, metal is deposited on the gate insulating film 7 in the Standard region by sputtering. The value of the surface density of the metal deposited on the gate insulating film 7 in the standard region is an example, and the value of the surface density of the metal deposited on the gate insulating film 7 in the standard region may be another value.

Metals deposited on the gate insulating film 7 in the standard region are Hf, Zr, Al, La, Y,
Ti, Ta, W, Ir and platinum. Further, the type of metal deposited on the gate insulating film 7 in the Standard region may be one type or two or more types.

  A description will be given of the dose amount of impurities ion-implanted into the well 5 and the kind and surface density of the metal deposited on the gate insulating film 7 in the Standard region in adjusting the threshold voltage of the standard MOSFET. Here, a method of adjusting the threshold voltage of the standard MOSFET to the predetermined voltage V2 will be described.

  The dose amount of the impurity ion-implanted into the well 5 in accordance with the predetermined voltage V2, the type of metal deposited on the gate insulating film 7 in the Standard region, and the surface density are determined. That is, the dose amount of impurities for adjusting the threshold voltage of the standard MOSFET to the predetermined voltage V2, the type of metal deposited on the gate insulating film 7 in the standard region, and the surface density are determined.

  In the process described with reference to FIG. 1, impurities are ion-implanted into the well 5 with the dose determined above. In the step described with reference to FIG. 13, metal is deposited on the gate insulating film 7 in the Standard region with the metal type and surface density determined above.

  Note that the dose amount of impurities for adjusting the threshold voltage of the standard MOSFET to the predetermined voltage V2, the type of metal deposited on the gate insulating film 7 in the standard region, and the surface density should be obtained in advance by experiments. Good. In addition, values obtained by experiments may be mapped or databased.

For example, when the predetermined voltage V2 is 0.2V, the impurity dose is set to 5 × 10 ¹² / cm ² to 5 × 5.
It determines from the range of * 10 < ¹³ > / cm < ² >. Then, based on the determined impurity dose, the type and surface density of the metal deposited on the gate insulating film 7 in the Standard region are determined. Standard
The type of metal deposited on the gate insulating film 7 in the region is determined from at least one of Hf, Zr, Al, La, Y, Ti, Ta, W, Ir, and Pt. The surface density of the metal deposited on the gate insulating film 7 in the Standard region is determined from the range of 5 × 10 ¹³ atoms / cm ² to 1 × 10 ¹⁵ atoms / cm ² .

  Ions are implanted into the Standard region with the determined dose amount, and a metal is deposited on the gate insulating film 7 in the Standard region with the determined metal type and surface density, so that the threshold voltage of the Standard MOSFET is set to a desired value. Can be adjusted to voltage.

Then, the resist pattern 30 shown in FIG. 13 is peeled off. The resist pattern 30 can be peeled by ashing using O ₂ plasma, a method using a resist stripping solution, or the like.

  Next, heat treatment is performed on the semiconductor substrate 2 and the gate insulating film 7. The heat treatment conditions for the semiconductor substrate 2 and the gate insulating film 7 are a heat treatment temperature of 650 ° C. to 1050 ° C. and a treatment time of less than 10 seconds. The heat treatment on the semiconductor substrate 2 and the gate insulating film 7 may be performed before the resist pattern 30 is peeled off.

  Note that the heat treatment conditions for the semiconductor substrate 2 and the gate insulating film 7 may be determined in accordance with the type of metal deposited on the gate insulating film 7 in the Standard region. Further, the heat treatment may not be performed on the semiconductor substrate 2 and the gate insulating film 7 according to the type of metal deposited on the gate insulating film 7 in the Standard region.

  The process after the resist pattern 30 shown in FIG. 13 is peeled and the semiconductor substrate 2 and the gate insulating film 7 are heat-treated is the same as the process described with reference to FIGS.

<Adjustment of threshold voltage of Low Leak MOSFET>
When adjusting the threshold voltage of the low leak MOSFET to a desired voltage, after performing the process described in FIG. 1, a resist is applied on the gate insulating film 7 as shown in FIG. Then, a resist pattern 40 is formed. In this case, the resist pattern 40 is formed so as to cover areas other than the low leak region. That is, the resist pattern 40 is formed so as to cover the high speed region and the standard region.

Next, as shown in FIG. 15, metal is deposited at 5 × 10 ¹³ atoms / cm ² to 1 × 10 ¹⁵ atoms / cm ² on the gate insulating film 7 in the low leak region using the resist pattern 40 as a mask. . That is, the surface density of the metal deposited on the gate insulating film 7 in the low leak region is set to be in the range of 5 × 10 ¹³ atoms / cm ² to 1 × 10 ¹⁵ atoms / cm ² . For example, metal is deposited on the gate insulating film 7 in the low leak region by sputtering. The value of the surface density of the metal deposited on the gate insulating film 7 in the Low Leak region is an example, and the value of the surface density of the metal deposited on the gate insulating film 7 in the Low Leak region is another value. Good.

  Metals deposited on the gate insulating film 7 in the low leak region are Hf, Zr, Al, La, Y, Ti, Ta, W, Ir, and platinum. Further, the type of metal deposited on the gate insulating film 7 in the low leak region may be one type or two or more types.

  The amount of impurities ion-implanted into the well 6 in adjusting the threshold voltage of the low leak MOSFET, the kind of metal deposited on the gate insulating film 7 in the low leak region, and the surface density will be described. Here, a method of adjusting the threshold voltage of the low leak MOSFET to the predetermined voltage V3 will be described.

  The dose amount of the impurity ion-implanted into the well 6, the kind of metal deposited on the gate insulating film 7 in the low leak region, and the surface density are determined according to the predetermined voltage V3. That is, the dose amount of impurities for adjusting the threshold voltage of the low leak MOSFET to the predetermined voltage V3, the kind of metal deposited on the gate insulating film 7 in the low leak region, and the surface density are determined.

  In the process described with reference to FIG. 1, impurities are ion-implanted into the well 6 with the dose determined above. In the process described with reference to FIG. 15, metal is deposited on the gate insulating film 7 in the low leak region with the metal type and surface density determined above.

  The dose amount of impurities for adjusting the threshold voltage of the low leak MOSFET to the predetermined voltage V3, the type of metal deposited on the gate insulating film 7 in the low leak region, and the surface density are obtained in advance by experiments. Just keep it. In addition, values obtained by experiments may be mapped or databased.

For example, when the predetermined voltage V3 is 0.3 V, the impurity dose is set to 1 × 10 ¹³ / cm ² to 1
It determines from the range of * 10 < ¹⁴ > / cm < ² >. And based on the determined impurity dose, Low
The kind and surface density of the metal deposited on the gate insulating film 7 in the leak region are determined. Low leak
The type of metal deposited on the gate insulating film 7 in the region is determined from at least one of Hf, Zr, Al, La, Y, Ti, Ta, W, Ir, and Pt. The surface density of the metal deposited on the gate insulating film 7 in the low leak region is determined from the range of 5 × 10 ¹³ atoms / cm ² to 1 × 10 ¹⁵ atoms / cm ² .

  By implanting ions into the low leak region with the determined dose, and depositing metal on the gate insulating film 7 in the low leak region with the determined metal type and surface density, the threshold voltage of the low leak MOSFET is obtained. Can be adjusted to a desired voltage.

Then, the resist pattern 40 shown in FIG. 15 is peeled off. The resist pattern 40 can be stripped by ashing using O ₂ plasma, a method using a resist stripping solution, or the like.

  Next, heat treatment is performed on the semiconductor substrate 2 and the gate insulating film 7. The heat treatment conditions are a heat treatment temperature of 650 ° C. to 1050 ° C. and a treatment time of less than 10 seconds. The heat treatment for the semiconductor substrate 2 and the gate insulating film 7 may be performed before the resist pattern 40 is removed.

  Note that the heat treatment conditions for the semiconductor substrate 2 and the gate insulating film 7 may be determined in accordance with the type of metal deposited on the gate insulating film 7 in the low leak region. Further, depending on the type of metal deposited on the gate insulating film 7 in the low leak region, the semiconductor substrate 2 and the gate insulating film 7 may not be subjected to heat treatment.

  The process after the resist pattern 40 shown in FIG. 15 is peeled and the semiconductor substrate 2 and the gate insulating film 7 are heat-treated is the same as the process described with reference to FIGS. Further, when the semiconductor substrate 2 and the gate insulating film 7 are not heat-treated, the steps after the resist pattern 40 is peeled off are the same as the steps described with reference to FIGS. 5 to 11 of the first embodiment.

In the present embodiment, an example in which a p-type (p-channel) MOSFET or an n-type (n-channel) MOSFET is manufactured has been described. However, the present invention is not limited to this, and the semiconductor device according to the present embodiment and its It is possible to apply a manufacturing method.

  In this embodiment, an example of manufacturing three types of MOSFETs, a high speed MOSFET, a standard MOSFET, and a low leak MOSFET has been shown. However, the present invention is not limited to this, and when four or more MOSFETs having different threshold voltages are manufactured. It is also possible to apply the semiconductor device and the manufacturing method thereof according to this embodiment.

  According to the semiconductor device and the manufacturing method thereof according to the present embodiment, the threshold voltage of the MOSFET can be adjusted to a desired voltage. That is, the dose amount of the impurity ion-implanted into the region where the MOSFET of the semiconductor substrate 2 is formed, the kind of metal deposited on the gate insulating film 7 and the surface density are determined. Ions are implanted into the region of the semiconductor substrate 2 where the MOSFET is to be formed with the determined dose, and the threshold voltage of the MOSFET is reduced by depositing metal on the gate insulating film 7 with the determined type and surface density of the metal. It can be adjusted to a desired voltage.

Second Embodiment
A semiconductor device and a manufacturing method thereof according to the second embodiment will be described with reference to FIGS. In the first embodiment, the semiconductor device and the manufacturing method thereof in the case where the threshold voltage of one kind of MOSFET is adjusted to a desired voltage have been described. In the second embodiment, a semiconductor device and a method for manufacturing the semiconductor device when adjusting threshold voltages of a plurality of types of MOSFETs to a desired voltage will be described. In addition, about the same component, the code | symbol same as 1st Embodiment is attached | subjected and the description is abbreviate | omitted. Further, the drawings in FIGS. 1 to 15 are referred to as necessary.

  In the semiconductor device and the manufacturing method thereof according to the second embodiment, the same processes as those in FIGS. 1 to 4 described in the first embodiment are performed. Therefore, the description of the steps of FIGS. 1 to 4 is omitted here, and the steps after FIG. 4 will be described below.

  As shown in FIG. 16, a resist is applied on the gate insulating film 7 and mask exposure is performed to form a resist pattern 50. In this case, the resist pattern 50 is formed so as to cover areas other than the Standard area. That is, the resist pattern 50 is formed so as to cover the high speed region and the low leak region.

Next, as shown in FIG. 17, metal is deposited at 5 × 10 ¹³ atoms / cm ² to 1 × 10 ¹⁵ atoms / cm ² on the gate insulating film 7 in the Standard region using the resist pattern 50 as a mask. That is, the surface density of the metal deposited on the gate insulating film 7 in the Standard region is set in the range of 5 × 10 ¹³ atoms / cm ² to 1 × 10 ¹⁵ atoms / cm ² . For example, metal is deposited on the gate insulating film 7 in the Standard region by sputtering. The value of the surface density of the metal deposited on the gate insulating film 7 in the standard region is an example, and the value of the surface density of the metal deposited on the gate insulating film 7 in the standard region may be another value.

  Metals deposited on the gate insulating film 7 in the Standard region are Hf, Zr, Al, La, Y, Ti, Ta, W, Ir, and Pt. Further, the type of metal deposited on the gate insulating film 7 in the Standard region may be one type or two or more types.

  The metal deposited on the gate insulating film 7 in the Standard region may be the same type of metal as the metal deposited on the gate insulating film 7 in the High Speed region, or may be a different type of metal. . In addition, the type of metal deposited on the gate insulating film 7 in the Standard region may partially overlap with the type of metal deposited on the gate insulating film 7 in the High Speed region.

  The determination of the dose amount of impurities ion-implanted into the well 5 in the adjustment of the threshold voltage of the standard MOSFET, the type of metal deposited on the gate insulating film 7 in the standard region, and the surface density are the same as in the first embodiment. The same method is used.

Then, as shown in FIG. 18, the resist pattern 50 is peeled off. The resist pattern 50 can be stripped by ashing using O ₂ plasma, a method using a resist stripping solution, or the like.

  Next, heat treatment is performed on the semiconductor substrate 2 and the gate insulating film 7. The heat treatment conditions are a heat treatment temperature of 650 ° C. to 1050 ° C. and a treatment time of less than 10 seconds. Further, the heat treatment for the semiconductor substrate 2 and the gate insulating film 7 may be performed before the resist pattern 50 is removed.

  Note that the heat treatment conditions for the semiconductor substrate 2 and the gate insulating film 7 may be determined in accordance with the type of metal deposited on the gate insulating film 7 in the Standard region. In addition, the heat treatment conditions for the semiconductor substrate 2 and the gate insulating film 7 may be determined in accordance with the types of metals deposited on the gate insulating film 7 in the High Speed region and the gate insulating film 7 in the Standard region. .

  Furthermore, the heat treatment may not be performed on the semiconductor substrate 2 and the gate insulating film 7 according to the type of metal deposited on the gate insulating film 7 in the Standard region. Further, the heat treatment may not be performed on the semiconductor substrate 2 and the gate insulating film 7 according to the type of each metal deposited on the gate insulating film 7 in the High Speed region and the gate insulating film 7 in the Standard region. .

  Then, as shown in FIG. 19, a resist is applied on the gate insulating film 7, mask exposure is performed, and a resist pattern 60 is formed. In this case, the resist pattern 60 is formed so as to cover areas other than the low leak region. That is, the resist pattern 60 is formed so as to cover the high speed region and the standard region.

Next, as shown in FIG. 20, metal is deposited at 5 × 10 ¹³ atoms / cm ² to 1 × 10 ¹⁵ atoms / cm ² on the gate insulating film 7 in the low leak region using the resist pattern 60 as a mask. . That is, the surface density of the metal deposited on the gate insulating film 7 in the low leak region is set to be in the range of 5 × 10 ¹³ atoms / cm ² to 1 × 10 ¹⁵ atoms / cm ² . For example, metal is deposited on the gate insulating film 7 in the low leak region by sputtering. The value of the surface density of the metal deposited on the gate insulating film 7 in the Low Leak region is an example, and the value of the surface density of the metal deposited on the gate insulating film 7 in the Low Leak region is another value. Good.

  Metals deposited on the gate insulating film 7 in the low leak region are Hf, Zr, Al, La, Y, Ti, Ta, W, Ir, and Pt. Further, the type of metal deposited on the gate insulating film 7 in the low leak region may be one type or two or more types.

  The metal deposited on the gate insulating film 7 in the Low Leak region may be the same type of metal as the metal deposited on the gate insulating film 7 in the High Speed region, or may be a different type of metal. Good. Further, the type of metal deposited on the gate insulating film 7 in the Low Leak region may partially overlap with the type of metal deposited on the gate insulating film 7 in the High Speed region.

  The metal deposited on the gate insulating film 7 in the Low Leak region may be the same type of metal as the metal deposited on the gate insulating film 7 in the Standard region, or may be a different type of metal. . In addition, the type of metal deposited on the gate insulating film 7 in the Low Leak region may partially overlap with the type of metal deposited on the gate insulating film 7 in the Standard region.

  For example, as shown in FIG. 21, the type of metal deposited on the gate insulating film 7 in the High Speed region, on the gate insulating film 7 in the Standard region, and on the gate insulating film 7 in the Low Leak region is determined. Also good.

  The column of “High Speed” in FIG. 21 indicates the type of metal deposited on the gate insulating film 7 in the High Speed region. The column “Standard” in FIG. 21 indicates the type of metal deposited on the gate insulating film 7 in the Standard region. The column “Low Leak” in FIG. 21 indicates the type of metal deposited on the gate insulating film 7 of Low Leak. In FIG. 21, metal A, metal B, and metal C are any of Hf, Zr, Al, La, Y, Ti, Ta, W, Ir, and Pt, and metal A, metal B, and metal C are different from each other. It shall be a kind of metal.

  Regarding the determination of the dose amount of the impurities ion-implanted into the well 6 in the adjustment of the threshold voltage of the low leak MOSFET, the determination of the kind and surface density of the metal deposited on the gate insulating film 7 in the low leak region is the first implementation. The method is the same as that of the form.

Then, as shown in FIG. 22, the resist pattern 60 is peeled off. The resist pattern 60 can be stripped by ashing using O ₂ plasma, a method using a resist stripping solution, or the like.

  Next, heat treatment is performed on the semiconductor substrate 2 and the gate insulating film 7. The heat treatment conditions for the semiconductor substrate 2 and the gate insulating film 7 are a heat treatment temperature of 650 ° C. to 1050 ° C. and a treatment time of less than 10 seconds. Further, the heat treatment for the semiconductor substrate 2 and the gate insulating film 7 may be performed before the resist pattern 60 is removed.

  The heat treatment conditions for the semiconductor substrate 2 and the gate insulating film 7 may be determined according to the type of metal deposited on the gate insulating film 7 in the low leak region. In addition, the heat treatment conditions for the semiconductor substrate 2 and the gate insulating film 7 are determined in accordance with the type of each metal deposited on the gate insulating film 7 in the High Speed region and on the gate insulating film 7 in the Low Leak region. Also good.

The heat treatment conditions for the semiconductor substrate 2 and the gate insulating film 7 may be determined according to the type of each metal deposited on the gate insulating film 7 in the Standard region and on the gate insulating film 7 in the Low Leak region. Further, the semiconductor substrate 2 and the gate insulation are selected according to the type of each metal deposited on the gate insulating film 7 in the high speed region, on the gate insulating film 7 in the standard region, and on the gate insulating film 7 in the low leak region. Conditions for heat treatment on the film 7 may be determined.

  Depending on the type of metal deposited on the gate insulating film 7 in the low leak region, the semiconductor substrate 2 and the gate insulating film 7 may not be subjected to heat treatment. In addition, the semiconductor substrate 2 and the gate insulating film 7 are not subjected to heat treatment according to the type of each metal deposited on the gate insulating film 7 in the High Speed region and on the gate insulating film 7 in the Low Leak region. Also good.

  Depending on the type of each metal deposited on the gate insulating film 7 in the Standard region and on the gate insulating film 7 in the Low Leak region, the semiconductor substrate 2 and the gate insulating film 7 may not be subjected to heat treatment. Further, the semiconductor substrate 2 and the gate insulation are selected according to the type of each metal deposited on the gate insulating film 7 in the high speed region, on the gate insulating film 7 in the standard region, and on the gate insulating film 7 in the low leak region. The heat treatment on the film 7 may not be performed.

  The process after the heat treatment of the semiconductor substrate 2 and the gate insulating film 7 is the same as the process described with reference to FIGS. 5 to 11 of the first embodiment. Further, when the semiconductor substrate 2 and the gate insulating film 7 are not heat-treated, the steps after the resist pattern 60 is peeled off are the same as the steps described with reference to FIGS. 5 to 11 of the first embodiment.

  In this embodiment, after depositing a metal on the gate insulating film 7 in the High Speed region, the metal is deposited on the gate insulating film 7 in the Standard region. Thereafter, a metal was deposited on the gate insulating film 7 in the low leak region. However, the order of depositing the metal on the gate insulating film 7 in the High Speed region, the gate insulating film 7 in the Standard region, and the gate insulating film 7 in the Low Leak region can be changed as appropriate. For example, after depositing a metal on the gate insulating film 7 in the Standard region, the metal may be deposited on the gate insulating film 7 in the High Speed region. Thereafter, a metal may be deposited on the gate insulating film 7 in the low leak region.

In this embodiment, metal is deposited on the gate insulating film 7 in the High Speed region, on the gate insulating film 7 in the Standard region, and on the gate insulating film 7 in the Low Leak region. Not limited to this, High
Although metal is deposited on the gate insulating film 7 in the Speed region and on the gate insulating film 7 in the Standard region, the metal may not be deposited on the gate insulating film 7 in the Low Leak region. In this case, it is possible to prevent the metal from adhering to the gate insulating film 7 in the low leak region by omitting the steps described with reference to FIGS.

  Further, metal is deposited on the gate insulating film 7 in the High Speed region and on the gate insulating film 7 in the Low Leak region, but metal may not be deposited on the gate insulating film 7 in the Standard region. Good. In this case, it is possible to prevent metal from adhering to the gate insulating film 7 in the Standard region by omitting the steps described with reference to FIGS.

  Further, metal is deposited on the gate insulating film 7 in the Standard region and on the gate insulating film 7 in the Low Leak region, but metal may not be deposited on the gate insulating film 7 in the High Speed region. Good. In this case, it is possible to prevent metal from adhering to the gate insulating film 7 in the Standard region by omitting the steps described in FIGS. 2 to 4 of the first embodiment.

In the present embodiment, an example in which a p-type (p-channel) MOSFET or an n-type (n-channel) MOSFET is manufactured has been described. However, the present invention is not limited to this, and the semiconductor device according to the present embodiment and its It is possible to apply a manufacturing method.

In this embodiment, an example of manufacturing three types of MOSFETs, a high speed MOSFET, a standard MOSFET, and a low leak MOSFET has been shown. However, the present invention is not limited to this, and when four or more MOSFETs having different threshold voltages are manufactured. It is also possible to apply the semiconductor device and the manufacturing method thereof according to this embodiment.

  According to the semiconductor device and the manufacturing method thereof according to the present embodiment, the threshold voltage of the MOSFET can be adjusted to a desired voltage. That is, the dose amount of the impurity ion-implanted into the region where the MOSFET of the semiconductor substrate 2 is formed, the kind of metal deposited on the gate insulating film 7 and the surface density are determined. Ions are implanted into the region of the semiconductor substrate 2 where the MOSFET is to be formed with the determined dose, and the threshold voltage of the MOSFET is reduced by depositing metal on the gate insulating film 7 with the determined type and surface density of the metal. It can be adjusted to a desired voltage.

  Further, according to the semiconductor device and the manufacturing method thereof according to the present embodiment, the threshold voltage can be adjusted to a desired voltage for each MOSFET having a different threshold voltage. That is, the dose amount of the impurity ion-implanted into the region where the MOSFET of the semiconductor substrate 2 is formed, the kind of metal deposited on the gate insulating film 7 and the surface density are determined for each MOSFET having different threshold voltages. With the determined dose amount, ion implantation is performed for each region where MOSFETs having different threshold voltages of the semiconductor substrate 2 are formed. A metal is deposited on the gate insulating film 7 in each region where MOSFETs having different threshold voltages of the semiconductor substrate 2 are formed with the determined metal type and surface density. Thereby, the threshold voltage can be adjusted to a desired voltage for each MOSFET having a different threshold voltage.

<Modification>
With reference to FIGS. 23 to 25, a semiconductor device and a manufacturing method thereof according to this modification will be described. In the second embodiment, an example is shown in which the metal is deposited on the gate insulating film 7 in the Standard region and on the gate insulating film 7 in the Low Leak region in separate steps. Not limited to this, the metal may be deposited on the gate insulating film 7 in the Standard region and on the gate insulating film 7 in the Low Leak region in the same process. In this modification, an example will be described in which metal is deposited on the gate insulating film 7 in the Standard region and on the gate insulating film 7 in the Low Leak region in the same process.

  In the semiconductor device and the manufacturing method thereof according to this modification, the same processes as those in FIGS. 1 to 4 described in the first embodiment are performed. Therefore, the description of the steps of FIGS. 1 to 4 is omitted here, and the steps after FIG. 4 will be described below.

  As shown in FIG. 23, a resist is applied on the gate insulating film 7 and mask exposure is performed to form a resist pattern 70. In this case, the resist pattern 70 is formed so as to cover areas other than the Standard area and the Low Leak area. That is, the resist pattern 70 is formed so as to cover the high speed region.

Next, as shown in FIG. 24, 5 × 10 ¹³ atoms / cm ² to 1 × 10 6 on the gate insulating film 7 in the Standard region and on the gate insulating film 7 in the Low Leak region using the resist pattern 70 as a mask. Metal is deposited at ¹⁵ atoms / cm ² . That is, the surface density of the metal deposited on the gate insulating film 7 in the Standard region and on the gate insulating film 7 in the Low Leak region is 5 × 10 ¹³ atoms / c.
The range is from m ² to 1 × 10 ¹⁵ atoms / cm ² .

  For example, a metal is deposited on the gate insulating film 7 in the Standard region and the gate insulating film 7 in the Low Leak region by sputtering. The value of the surface density of the metal deposited on the gate insulating film 7 in the standard region is an example, and the value of the surface density of the metal deposited on the gate insulating film 7 in the standard region may be another value. Further, the value of the surface density of the metal deposited on the gate insulating film 7 in the low leak region is an example, and the value of the surface density of the metal deposited on the gate insulating film 7 in the low leak region is another value. It is good.

  Metals deposited on the gate insulating film 7 in the Standard region and on the gate insulating film 7 in the Low Leak region are Hf, Zr, Al, La, Y, Ti, Ta, W, Ir, and Pt. Further, the type of metal deposited on the gate insulating film 7 in the Standard region and on the gate insulating film 7 in the Low Leak region may be one type or two or more types.

  In this modification, the metal adhering on the gate insulating film 7 in the Standard region and on the gate insulating film 7 in the Low Leak region is the same type of metal, and on the gate insulating film 7 in the Standard region and in the Low Leak region. The surface density of the metal deposited on the gate insulating film 7 is the same. By performing metal deposition on the gate insulating film 7 in the Standard region and on the gate insulating film 7 in the Low Leak region in the same process, the number of processing steps can be reduced.

  The metal deposited on the gate insulating film 7 in the Standard region and the gate insulating film 7 in the Low Leak region may be the same type of metal as the metal deposited on the gate insulating film 7 in the High Speed region. However, different types of metals may be used. In addition, there are some types of metal adhering on the gate insulating film 7 in the Standard region and on the gate insulating film 7 in the Low Leak region, and some types of metal adhering on the gate insulating film 7 in the High Speed region. It may overlap.

  In adjusting the threshold voltage of the standard MOSFET, the dose of the impurity ion-implanted into the well 5, the type of metal deposited on the gate insulating film 7 in the standard region, and the surface density are the same as in the first embodiment. By the way. Further, in the adjustment of the threshold voltage of the low leak MOSFET, the determination of the dose amount of the impurity ion-implanted into the well 6, the kind of metal deposited on the gate insulating film 7 in the low leak region, and the surface density are described in the first embodiment. The method is the same as that of the form.

Then, as shown in FIG. 25, the resist pattern 70 is peeled off. The resist pattern 70 can be peeled by ashing using O ₂ plasma or a resist stripping method.

  Next, heat treatment is performed on the semiconductor substrate 2 and the gate insulating film 7. The heat treatment conditions are a heat treatment temperature of 650 ° C. to 1050 ° C. and a treatment time of less than 10 seconds. Further, the heat treatment for the semiconductor substrate 2 and the gate insulating film 7 may be performed before the resist pattern 70 is removed. The determination of the heat treatment conditions for the semiconductor substrate 2 and the gate insulating film 7 and the determination of whether or not to perform the heat treatment for the semiconductor substrate 2 and the gate insulating film 7 are the same as in the second embodiment.

  The process after the heat treatment of the semiconductor substrate 2 and the gate insulating film 7 is the same as the process described with reference to FIGS. 5 to 11 of the first embodiment. Further, when the semiconductor substrate 2 and the gate insulating film 7 are not heat-treated, the steps after the resist pattern 70 is peeled off are the same as the steps described in FIGS. 5 to 11 of the first embodiment.

Regarding the above first embodiment and second embodiment, the following additional notes are disclosed.
(Appendix 1)
A semiconductor substrate;
A gate insulating film provided on the semiconductor substrate;
A gate electrode provided on the gate insulating film;
Including a plurality of types of field effect transistors having different threshold voltages including:
At least one of the field effect transistors is a semiconductor device in which at least one metal is present in the gate insulating film.

(Appendix 2)
2. The semiconductor device according to claim 1, wherein when a metal is present in the gate insulating film of the plurality of types of field effect transistors, the density of the metal in the gate insulating film is different for each type of the field effect transistor.

(Appendix 3)
3. The semiconductor device according to appendix 1 or 2, wherein the concentration of the channel impurity of the field effect transistor differs depending on the type of the field effect transistor.

(Appendix 4)
The semiconductor device according to any one of appendices 1 to 3, wherein the metal is selected from the group consisting of Hf, Zr, Al, La, Y, Ti, Ta, W, Ir, and Pt.

(Appendix 5)
Forming a gate insulating film on the semiconductor substrate;
Forming a resist pattern on the gate insulating film in a region for forming a first field effect transistor;
Depositing at least one metal on the gate insulating film in a region where a second field effect transistor having a threshold voltage different from that of the first field effect transistor is formed using the resist pattern as a mask; ,
Removing the resist pattern;
Performing a heat treatment on the semiconductor substrate and the gate insulating film;
Forming a gate electrode on the gate insulating film.

(Appendix 6)
The semiconductor device manufacturing method according to appendix 5, wherein the metal is selected from the group consisting of Hf, Zr, Al, La, Y, Ti, Ta, W, Ir, and Pt.

(Appendix 7)
Forming a gate insulating film on the semiconductor substrate;
Forming a first resist pattern on the gate insulating film in a region for forming a first field effect transistor;
Using the first resist pattern as a mask, at least one first type of first insulating film is formed on the gate insulating film in a region where a second field effect transistor having a threshold voltage different from that of the first field effect transistor is formed. Attaching metal,
Peeling the first resist pattern;
Forming a second resist pattern on the gate insulating film in a region for forming the second field effect transistor;
Depositing at least one second metal on the gate insulating film in the region where the first field effect transistor is to be formed using the second resist pattern as a mask;
Peeling the second resist pattern;
Performing a heat treatment on the semiconductor substrate and the gate insulating film;
Forming a gate electrode on the gate insulating film.

(Appendix 8)
The manufacturing method of a semiconductor device according to appendix 7, wherein the first metal and the second metal are deposited on the gate insulating film with different areal densities.

(Appendix 9)
The semiconductor device manufacturing method according to appendix 7 or 8, wherein a channel impurity concentration of the first field effect transistor is different from a channel impurity concentration of the second field effect transistor.

(Appendix 10)
10. The method of manufacturing a semiconductor device according to any one of appendices 7 to 9, wherein the metal is selected from the group consisting of Hf, Zr, Al, La, Y, Ti, Ta, W, Ir, and Pt.

It is process drawing of the manufacturing method of the semiconductor device which concerns on 1st Embodiment which showed to the process of forming a gate insulating film. It is process drawing of the manufacturing method of the semiconductor device which concerns on 1st Embodiment which showed to the process of forming a resist pattern. FIG. 6 is a process diagram of the method for manufacturing a semiconductor device according to the first embodiment, showing up to a process of depositing metal on a gate insulating film in a high speed region. It is process drawing of the manufacturing method of the semiconductor device which concerns on 1st Embodiment which showed even the process of peeling of a resist pattern. It is process drawing of the manufacturing method of the semiconductor device which concerns on 1st Embodiment which showed to the process of forming a polysilicon. It is process drawing of the manufacturing method of the semiconductor device which concerns on 1st Embodiment which showed to the process of forming a gate electrode. It is a flowchart of the manufacturing method of the semiconductor device concerning a 1st embodiment showing up to the process of forming a sidewall insulating film. It is process drawing of the manufacturing method of the semiconductor device which concerns on 1st Embodiment which showed the process to form silicide. It is process drawing of the manufacturing method of the semiconductor device which concerns on 1st Embodiment which showed to the process of forming an interlayer insulation film. It is process drawing of the manufacturing method of the semiconductor device which concerns on 1st Embodiment which showed to the process of forming wiring. It is sectional drawing of a semiconductor device provided with MOSFET. It is process drawing of the manufacturing method of the semiconductor device which concerns on 1st Embodiment which showed to the process of forming a resist pattern. FIG. 6 is a process diagram of the method for manufacturing a semiconductor device according to the first embodiment, showing up to a process of depositing metal on a gate insulating film in a standard region. It is process drawing of the manufacturing method of the semiconductor device which concerns on 1st Embodiment which showed to the process of forming a resist pattern. FIG. 5 is a process diagram of the method for manufacturing a semiconductor device according to the first embodiment, showing up to a process of depositing metal on a gate insulating film in a low leak region. It is process drawing of the manufacturing method of the semiconductor device which concerns on 2nd Embodiment which showed to the process of forming a resist pattern. It is process drawing of the manufacturing method of the semiconductor device which concerns on 2nd Embodiment which showed to the process which adheres a metal to the gate insulating film in a Standard area | region. It is process drawing of the manufacturing method of the semiconductor device which concerns on 2nd Embodiment which showed even the process of peeling of a resist pattern. It is process drawing of the manufacturing method of the semiconductor device which concerns on 2nd Embodiment which showed the process until it forms a resist pattern. It is process drawing of the manufacturing method of the semiconductor device which concerns on 2nd Embodiment which showed to the process of adhering a metal to the gate insulating film in a Low Leak area | region. It is the figure which showed the example of the kind of metal adhering on the gate insulating film in a High Speed area | region, the gate insulating film in a Standard area | region, and the gate insulating film in a Low Leak area | region. It is process drawing of the manufacturing method of the semiconductor device which concerns on 2nd Embodiment which showed even the process of peeling of a resist pattern. It is process drawing of the manufacturing method of the semiconductor device which concerns on the modification which showed the process until it forms a resist pattern. FIG. 11 is a process diagram of a method for manufacturing a semiconductor device according to a modified example, showing up to a step of attaching metal to the gate insulating film in the Standard region and the gate insulating film in the Low Leak region. It is process drawing of the manufacturing method of the semiconductor device which concerns on the modification which showed the process until peeling of a resist pattern.

Explanation of symbols

2 Silicon substrate 3 Element isolation region 4, 5, 6 Well 7 Gate insulating film 10, 30, 40, 50, 60, 70 Resist pattern 11 Polysilicon 12, 13, 14 Gate electrode 15 LDD region 16 Side wall insulating film 17 Source / Drain region 18 Silicide 19, 22 Interlayer insulating film 20, 23 Contact plug 21, 24 Wiring

Claims (7)

A semiconductor substrate;
A gate insulating film provided on the semiconductor substrate;
A gate electrode provided on the gate insulating film;
Including a plurality of types of field effect transistors having different threshold voltages including:
At least one of the field effect transistors is a semiconductor device in which at least one metal is present in the gate insulating film.   2. The semiconductor device according to claim 1, wherein when a metal is present in the gate insulating film of the plurality of types of field effect transistors, the density of the metal in the gate insulating film is different for each type of the field effect transistor.   3. The semiconductor device according to claim 1, wherein the concentration of the channel impurity of the field effect transistor is different for each type of the field effect transistor. Forming a gate insulating film on the semiconductor substrate;
Forming a resist pattern on the gate insulating film in a region for forming a first field effect transistor;
Depositing at least one metal on the gate insulating film in a region where a second field effect transistor having a threshold voltage different from that of the first field effect transistor is formed using the resist pattern as a mask; ,
Removing the resist pattern;
Performing a heat treatment on the semiconductor substrate and the gate insulating film;
Forming a gate electrode on the gate insulating film. Forming a gate insulating film on the semiconductor substrate;
Forming a first resist pattern on the gate insulating film in a region for forming a first field effect transistor;
Using the first resist pattern as a mask, at least one first type of first insulating film is formed on the gate insulating film in a region where a second field effect transistor having a threshold voltage different from that of the first field effect transistor is formed. Attaching metal,
Peeling the first resist pattern;
Forming a second resist pattern on the gate insulating film in a region for forming the second field effect transistor;
Depositing at least one second metal on the gate insulating film in the region where the first field effect transistor is to be formed using the second resist pattern as a mask;
Peeling the second resist pattern;
Performing a heat treatment on the semiconductor substrate and the gate insulating film;
Forming a gate electrode on the gate insulating film.   The method for manufacturing a semiconductor device according to claim 5, wherein the first metal and the second metal are deposited on the gate insulating film with different surface densities.   7. The method of manufacturing a semiconductor device according to claim 5, wherein a channel impurity concentration of the first field effect transistor is different from a channel impurity concentration of the second field effect transistor.

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