JP2001326351A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of realizing a phenomenon of a channel resistance without deteriorating characteristics of transistors even from 0.1 μm generation, and to provide its manufacturing method. SOLUTION: After a gate electrode is formed, a semiconductor film has once selectively been formed in a source region and a drain region. An angle θmade between a side face 120 opposite to a gate electrode 103 of these source semiconductor layer and drain semiconductor layer 105, and a face 121 coming into contact with a semiconductor substrate 101 of the source semiconductor layer and drain semiconductor layer 105 is an acute angle. A recess part is formed on an upper face of the source semiconductor layer and drain semiconductor layer 105, and a source electrode and drain electrode 108 are embedded in this recess part, respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly to a structure of a MIS transistor and a method of manufacturing the same.

[0002]

2. Description of the Related Art The miniaturization of a field effect transistor is not known to end, and a gate length of 0.1 .mu.m has already been approached. This is because the miniaturization achieves a high-speed operation of the element, and the reduction rule of further reducing the power consumption is established. Further, miniaturization itself reduces the area occupied by elements, and more elements can be mounted on the same chip area, so that the LSI itself is highly integrated and multifunctional.

However, the above-mentioned reduction rule is expected to hit a large wall at a boundary of 0.1 μm. The wall is a problem that even if the element is miniaturized, the parasitic resistance of the element increases, so that the driving force of the element does not increase and the speed cannot be increased.

Conventionally, in order to solve this problem, self-aligned silicide (SALICIDE) has been proposed.
In addition, a structure in which a metal is selectively deposited on a source, a drain, and a gate has been used.

FIG. 26 is a cross-sectional view of a MISFET using SALICIDE. This MISFET has a gate insulating film 110 formed on a silicon substrate 1101.
2, a gate electrode 1103 formed on the gate insulating film 1102, a gate insulating side wall 1104 formed on the side wall of the gate electrode 1103, and a silicon substrate 110
1 and a silicide 1106 which is a material having a resistivity as low as metal formed on the drain region 1105 in a self-aligned manner. Here, the drain region 1105 is formed by diffusing impurities into the silicon substrate 1101.
For example, when the silicon substrate 1101 is p-type, the drain region 1105 is n-type. A pn junction is formed at an interface 1200 between the drain region 1105 and the silicon substrate 1101 with a depletion layer interposed therebetween. Here, the drain region has been described, but the same applies to the source region.

[0006] With this configuration, the resistance of the source electrode and the drain electrode can be reduced. However, p
It has been pointed out that when the distance between the n-junction 1200 and the silicide 1106 is reduced (about 100 nm or less), the rectification of the pn-junction deteriorates and a leak current starts to flow. When this problem occurs, the memory retention characteristics of the DRAM deteriorate, and the power consumption of the LOGIC increases. When it gets worse, the transistor does not work.

If the pn junction is deepened to solve this problem, a short channel effect will occur this time, causing a problem that the threshold value varies and decreases. That is, it is necessary to reduce the resistance of the source region and the drain region while keeping the pn junction shallow.

In order to lower the resistance of the source and drain regions while keeping the pn junction shallow as described above, the source and drain regions are grown thickly by a method such as SEG (Selective Epitaxial Growth).
A measure has been taken to form a silicide thereon to substantially increase the distance between the silicide and the pn junction.

FIG. 27 is a cross-sectional view of the field effect transistor formed as described above.

This field-effect transistor includes a gate electrode 1203 formed on a silicon substrate 1201 via a gate insulating film 1202, a gate insulating side wall 1204 formed on the side wall of the gate electrode 1203, and a gate electrode 1203 formed on the silicon substrate 1201. Drain region 1205 formed by growth
And a silicide 1206 formed on the drain region 1205. Here, the drain region 12
05 is formed by growing a film on a silicon substrate 1201. For example, when the silicon substrate 1201 is p-type, the drain region 1205 is n-type. And the drain region 12
A pn junction is formed at an interface 1200 between the substrate 05 and the silicon substrate 1201 with a depletion layer interposed therebetween. Here, the drain region has been described, but the same applies to the source region.

In such a field-effect transistor, when a transistor having a gate length of 0.1 μm or less is considered in the future, as shown in FIG.
It can be formed as an extraordinarily thick 1 μm. Therefore, as described above, the distance between the pn junction 1200 and the silicide 1206 can be increased, but the drain region 1205 and the gate electrode 1203 can be combined with the thinning of the gate insulating side wall 1204.
It can be easily predicted that the problem that the parasitic capacitance between them becomes large and the high speed as the LSI speed cannot be obtained eventually occurs.

As described above, lowering the resistance of the source and drain regions or the gate deteriorates other transistor characteristics (short channel effect, increase in parasitic capacitance, leak characteristics of pn junction) after the 0.1 μm generation. It is becoming more difficult to do without them. Also, the reduction in channel resistance due to transistor scaling allows for lower parasitic resistance.

Further, the conventional salicide process has been performed using selective growth of metal. However, in the selective growth of a metal, conditions for enhancing the selectivity are severe, and a metal may be partially formed on an insulating film which is not allowed to grow. In such a case, a short circuit occurs between the source electrode and the drain electrode, which causes a reduction in the yield of the device. Such a problem becomes more remarkable as the element is miniaturized. In addition, the metal selective growth method has a problem that a metal that can be used to enhance selectivity with silicon is limited.

[0014]

SUMMARY OF THE INVENTION The present invention has been made to solve this problem, and has been made in view of the above circumstances. A semiconductor device capable of realizing a channel resistance phenomenon without deteriorating transistor characteristics even in the 0.1 μm generation or later. It is an object of the present invention to provide a method of manufacturing a semiconductor device in which the source, drain, and gate have sufficiently low contact resistance.

Another object of the present invention is to provide a method of manufacturing a semiconductor device in which any metal can be used for a source electrode, a drain electrode, and a gate electrode without using a metal selective growth method.

[0016]

In order to achieve the above object, a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, A channel region formed under the film, a source region and a drain region formed apart from each other in the semiconductor, and provided such that the channel region is located therebetween, and a channel region formed on the source region. A source semiconductor layer, a drain semiconductor layer formed on the drain region, a source electrode formed on the source semiconductor layer, and a drain electrode formed on the drain semiconductor layer. A side surface of the semiconductor layer and the drain semiconductor layer facing the gate electrode, and a contact between the source semiconductor layer and the drain semiconductor layer and the semiconductor substrate. The source electrode and the drain electrode are formed in concave portions formed above the source semiconductor layer and the drain semiconductor layer. .

At this time, the semiconductor device is an n-channel M
The source electrode and the drain electrode of the n-channel MIS field-effect transistor are different from the source electrode and the drain electrode of the p-channel MIS field-effect transistor. Is preferred. Thus, by selecting a material having a low Schottky barrier for each electrode of the n-channel MIS field-effect transistor and the p-channel MIS field-effect transistor, the characteristics of the transistor can be improved.

The semiconductor device is an n-channel MIS.
A field-effect transistor and a p-channel MIS field-effect transistor, wherein the gate electrode of the n-channel MIS field-effect transistor is
Preferably, it is different from the gate electrode of the S field effect transistor. an n-channel MIS field-effect transistor,
By selecting a material having a low Schottky barrier for each of the gate electrodes of the p-channel MIS field-effect transistor, the characteristics of the transistor can be improved.

It is preferable that the angle is 10 ° or more and 80 ° or less. More preferably, the angle is not less than 20 ° and not more than 70 °.

It is preferable that the gate insulating film is made of a metal oxide.

It is preferable that a side face of the source semiconductor layer and the drain semiconductor layer facing the gate electrode forms a facet.

It is preferable that a surface where the source semiconductor layer and the drain semiconductor layer are in contact with the source electrode and the drain electrode region, respectively, is formed by anisotropic etching.

Further, it is preferable that a surface where the source semiconductor layer and the drain semiconductor layer are in contact with the source electrode and the drain electrode region, respectively, is formed by isotropic etching.

The present invention also provides a step of forming a first insulating film on a semiconductor substrate, a step of depositing a first semiconductor layer on the first insulating film, and the steps of: First
Patterning a semiconductor layer, forming a second semiconductor layer of first and second conductivity types on a main surface of the semiconductor substrate, and forming the first insulating film, the first semiconductor layer, Depositing a second insulating film on a second semiconductor layer; and providing the second insulating film with the first semiconductor layer and the second semiconductor layer.
Removing the first semiconductor layer and the second semiconductor layer so that at least a part of the second semiconductor layer remains; and removing the second semiconductor layer until the upper surface of the second semiconductor layer appears. Depositing a metal or a silicide on a semiconductor layer.

At this time, when depositing the second semiconductor layers of the first and second conductivity types, one of the n-type field effect transistor and the p-type field effect transistor is formed with carbon. Is preferably covered with a film containing

In depositing the second semiconductor layers of the first and second conductivity types, one of the n-type field effect transistor and the p-type field effect transistor is formed by: It is preferable to cover with a film containing nitrogen.

Further, the present invention provides a step of forming a first insulating film on a semiconductor substrate, a step of depositing a first semiconductor layer on the first insulating film, Patterning the first semiconductor layer, forming first and second conductivity-type second semiconductor layers on a main surface of the semiconductor substrate, and forming the second semiconductor layer on the second semiconductor layer. Forming a third semiconductor layer of first and second conductivity types having a composition different from that of the first insulating film;
The first semiconductor layer, the second semiconductor layer, and the third
Depositing a second insulating film on the first semiconductor layer, removing the second insulating film until the upper surfaces of the first semiconductor layer and the third semiconductor layer appear, Removing the semiconductor layer and the third semiconductor layer until the upper surface of the second semiconductor layer appears, and depositing a metal or silicide on the upper surface of the second semiconductor layer. To provide a method of manufacturing a semiconductor device.

At this time, when depositing the first and second conductive type second semiconductor layers, one of the n-type field effect transistor and the p-type field effect transistor is formed in the field effect transistor forming region. It is preferable to cover with a film containing carbon.

When depositing the first and second conductive type second semiconductor layers, one of the n-type field effect transistor and the p-type field effect transistor is formed in a field-effect transistor forming region. It is preferable to cover with a film containing nitrogen.

Further, the present invention provides a step of forming a first insulating film on a semiconductor substrate, a step of depositing a first semiconductor layer on the first insulating film, Patterning the first semiconductor layer, forming first and second conductivity-type second semiconductor layers on a main surface of the semiconductor substrate; and forming the first insulating film and the first insulating film on the main surface. Depositing a second insulating film on the semiconductor layer and the second semiconductor layer, and removing the second insulating film until upper surfaces of the first semiconductor layer and the second semiconductor layer are exposed; When,
Oxidizing the first semiconductor layer and the second semiconductor layer so that at least a part of the second semiconductor layer remains;
Manufacturing a semiconductor device, comprising: removing an oxidized portion of the first semiconductor layer and the second semiconductor layer; and depositing a metal or a silicide on the second semiconductor layer. Provide a way.

At this time, when depositing the second semiconductor layers of the first and second conductivity types, one of the n-type field effect transistor and the p-type field effect transistor is formed in the field effect transistor formation region. It is preferable to cover with a film containing carbon.

In depositing the second semiconductor layers of the first and second conductivity types, one of the n-type field effect transistor and the p-type field effect transistor is formed by It is preferable to cover with a film containing nitrogen.

Also, the present invention provides a step of forming a first insulating film on a semiconductor substrate, a step of depositing a first semiconductor layer on the first insulating film, Patterning the first semiconductor layer, forming first and second conductivity-type second semiconductor layers on a main surface of the semiconductor substrate, and forming the second semiconductor layer on the second semiconductor layer. Forming a third semiconductor layer of first and second conductivity types having a composition different from that of the first insulating film;
The first semiconductor layer, the second semiconductor layer, and the third
Depositing a second insulating film on the first semiconductor layer, removing the second insulating film until the upper surfaces of the first semiconductor layer and the third semiconductor layer appear, Oxidizing the semiconductor layer and the third semiconductor layer; removing the oxide films of the first semiconductor layer and the third semiconductor layer until the upper surface of the second semiconductor layer appears; And a step of depositing a metal or a silicide on the second semiconductor layer.

At this time, when depositing the second semiconductor layers of the first and second conductivity types, one of the n-type field effect transistor and the p-type field effect transistor is formed in the field effect transistor forming region. It is preferable to cover with a film containing carbon.

In depositing the second semiconductor layers of the first and second conductivity types, one of the n-type field-effect transistor and the p-type field-effect transistor is formed by: It is preferable to cover with a film containing nitrogen.

In the present invention, a facet can be formed on the side surface facing the gate electrode by growing the second semiconductor layer by vapor phase growth. At this time, the inclination of the facet can be adjusted by selecting the plane orientation of the growth surface of the semiconductor substrate.

In the present invention, other transistor characteristics (short channel effect, increase in parasitic capacitance, pn junction leak characteristics)
Parasitic resistance can be reduced without adversely affecting the resistance.

In the present invention, the source electrode, the drain electrode, and the gate electrode are formed by forming a recess, forming a metal on the entire surface, and etching back the metal. Therefore, since the conventional selective growth method of metal is not used,
There is no problem of being restricted by the selective growth of the metal, and there is no problem such as a short circuit between the source electrode and the drain electrode. Therefore, the yield can be improved.

[0039]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a MISFE formed according to the present invention.
FIG. 3 shows a cross-sectional view of T.

As shown in FIG. 1, this MISFET
A semiconductor substrate 101 made of silicon or the like; a gate insulating film 102 made of silicon oxide or the like formed on the semiconductor substrate 101; a gate electrode 103 formed on the gate insulating film 102;
A source region 107A and a drain region 107B formed in the semiconductor substrate 101 at a position sandwiching the source region, a source semiconductor layer 105A and a drain semiconductor layer 105B formed on the source region 107A and the drain region 107B, respectively, The semiconductor device includes a source electrode 108A and a drain electrode 108B formed over the layer 105A and the drain semiconductor layer 105B, respectively.
In the following description, when A and B are omitted, independent portions are shown.

Source and drain semiconductor layers 10
5, a side surface 120 facing the gate electrode 103, and the semiconductor substrate 10 of the source semiconductor layer and the drain semiconductor layer 105.
1 forms an acute angle. A concave portion is formed on the upper surface of the source semiconductor layer and the drain semiconductor layer 105, and a source electrode and a drain electrode region 108 are respectively buried in the concave portion. Reference numeral 106 denotes an interlayer insulating film. Reference numeral 104 denotes a gate sidewall made of an insulator formed to insulate the gate sidewall. Source semiconductor layer and drain semiconductor layer 10
Reference numeral 5 is formed by the gate sidewall 104 so as to be slightly away from the gate insulating film 102 by the thickness a of the gate sidewall 104. Thus, leakage current between the source and drain semiconductor layers 105 and the gate electrode 103 can be prevented.

In this MISFET, since the side surface 120 of the source and drain semiconductor layers 105 facing the gate electrode 103 and the interface 121 with the semiconductor substrate 101 form an acute angle as shown in FIG. 103 between the semiconductor layer and the drain semiconductor layer 105 and the gate electrode,
The distance is large and the parasitic capacitance can be reduced.

The angle θ is preferably 10 ° or more in order to reduce the parasitic resistance. Further, the angle is preferably 20 ° or more. Is preferably 80 ° or less in order to reduce the parasitic capacitance. Further, the angle is preferably 70 ° or less.

A concave portion is formed on the upper surface of the source semiconductor layer and the drain semiconductor layer 105, and the concave portion is filled with the source electrode and the drain electrode. Therefore, the contact area between the source and drain electrodes 108 and the source and drain semiconductor layers 105 can be increased, so that the contact resistance can be reduced.

The source and drain regions 107
Is formed shallowly, and a source semiconductor and a drain electrode 105 are formed thereon. Therefore, the pn junction surface 13
The distance between 0 and the source and drain electrodes 108 is long.

Accordingly, the pn junction is a shallow pn junction where the short channel effect does not occur, and the leakage characteristics of the pn junction do not deteriorate due to metal deposition.

In the MISFET shown in FIG. 1, a part of the source and drain semiconductor layers 105 is removed by anisotropic etching such as RIE (reactive ion etching) to bury the source and drain electrodes 108. It was done. Therefore, the side surfaces where the source and drain semiconductor layers 105 and the source and drain electrodes 108 are in contact with each other are substantially vertically etched.

On the other hand, the MISFET shown in FIG. 2 is obtained by removing the source semiconductor layer and the drain semiconductor layer 105 from the MISFET shown in FIG. 1 by isotropic etching such as plasma etching. Therefore, the source semiconductor layer and the drain semiconductor layer 105 are isotropically etched, and the concave portions formed on the upper surfaces of the source semiconductor layer and the drain semiconductor layer 105 have a U-shaped structure. The angle θ between the side surface 120 of the source and drain semiconductor layers 105 facing the gate electrode 103 and the one main surface 121 of the semiconductor substrate 101 is an acute angle. At this time, the source electrode and the drain electrode 108 are buried in the concave portions of the source semiconductor layer and the drain semiconductor layer 105, and are formed thereover. Then, the side surface 123 of the source electrode and the drain electrode 108 facing the gate electrode 103 is formed by the source semiconductor layer and the drain semiconductor layer 1.
05, facing the gate electrode 103 at the same angle as the side surface 120. The side surfaces 120 and 123 form the same surface smoothly.

Source and drain semiconductor layers 10
5 facing the gate electrode 103 and the semiconductor substrate 1
01 is formed so as to form an acute angle θ with one main surface of the source semiconductor layer 105 and the drain semiconductor layer 105.
And the source and drain electrodes 108 and the gate electrode 10
3, and the parasitic capacitance can be reduced.

Here, in the MISFET shown in FIG.
The same parts as those of the MISFET shown in FIG.

Also in the case of the MISFET shown in FIG. 2, a concave portion is formed on the upper surface of the source semiconductor layer and the drain semiconductor layer 105, and the source electrode and the drain electrode 108 are buried. Therefore, the contact area between the source and drain electrodes 108 and the source and drain semiconductors 105 can be increased, and the contact resistance can be reduced.

Further, the source region and the drain region 107
Is formed shallowly, and a source semiconductor and a drain electrode 105 are formed thereon. Therefore, the pn junction surface 13
The distance between 0 and the source and drain electrodes 108 is long.

Therefore, the pn junction is a shallow pn junction where the short channel effect does not occur, and the leakage characteristics of the pn junction do not deteriorate due to metal deposition.

The following are (1) the field effect transistor of the present invention shown in FIGS. 1 and 2, (2) the field effect transistor formed by the salicide process shown in FIG. 26, and (3) the elevated shown in FIG. Device-induced parasitic capacitance of the field effect transistor formed by the source / drain structure and the salicide process
tance) Ctot, parasitic resistance Rsd, and gate delay time.

(1) Ctot [fF / μm] = 5.9 Rsd [ohm (S / D)] = 120 Tpd [ps] = 5.5 (2) Ctot [fF / μm] = 5.1 Rsd [ ohm (S / D)] = 440 Tpd [ps] = 7.3 (3) Ctot [fF / μm] = 11.1 Rsd [ohm (S / D)] = 200 Tpd [ps] = 11.5 or more As shown in (2), the transistor (2) has a small parasitic capacitance but a large parasitic resistance. Also (3)
On the other hand, the transistor has a small parasitic resistance but a large parasitic capacitance. On the other hand, in the transistor (1) of the present invention, the parasitic capacitance and the parasitic resistance are both low, and the gate delay time is faster than the transistors (2) and (3).

In the present invention, a transistor using a metal oxide film such as TiO ₂ having a high dielectric constant as a gate insulating film is more effective. Because the metal oxide film has a high dielectric constant, the gate film thickness is generally large. Therefore, the area where the side surfaces of the source semiconductor and the drain semiconductor are in contact with the gate film is increased, so that the parasitic capacitance is likely to be increased. However, in the present invention, since the side surfaces of the source semiconductor layer and the drain semiconductor layer are within the above-mentioned angle range, the contact with the gate insulating film is reduced and the parasitic capacitance can be reduced.

Next, a method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS.

First, as shown in FIG. 3, in order to form an element isolation region 201 on the main surface of a Si substrate (semiconductor substrate), a trench for STI (Shallow Trench Isolation) having a depth of about 0 is formed in the Si substrate. After digging 4 μm, SiO ₂ is entirely deposited by a CVD method, and the entire surface is flattened by CMP (chemical mechanical polishing). In FIG. 3, STI20
Parts deeper than 1 are omitted because they are not directly relevant to the description of the present invention. This is the same in and after this figure.

Next, after the p-channel transistor formation region and the n-channel transistor formation region are respectively masked by a photolithography process, ion implantation is performed to form an n-type well 203 and a p-type well 202, respectively.

Next, ions are implanted into each channel to adjust the threshold value of the transistor.

Next, a TiO ₂ film 204 serving as a gate insulating film (first insulating film) 204 is formed on a Si substrate (semiconductor substrate).
To TPT (tetra-iso-propyltitanate) (Ti (OC ₃
A mixed gas of H ₇ ) ₄ ) and oxygen is reacted at 380 ° C. to deposit 20 nm in thickness on the entire surface.

Next, polycrystalline Si is formed on the gate insulating film 204.
(First semiconductor layer) is deposited on the entire surface with a thickness of 50 nm. The deposition method is CVD (Chemical Vapor Deposition)
Any method such as sputtering or sputtering may be used.

Next, a p-type photolithography process is performed.
Mask channel formation region and n-channel formation region respectively
After that, ion implantation of P (phosphorus) and B (boron) is performed 1 ×.
10 ^Fifteencm^-2Do about.

Next, a SiO ₂ film 207 is deposited on the entire surface to a thickness of 20 nm. The deposition method may be any method such as CVD and sputtering.

Next, the impurities in the polycrystalline Si are activated by annealing (at 800 ° C. for 30 minutes in N ₂ ), and the n ⁺ -type Si gate electrode 2 is formed on the n-channel formation region.
05, p ⁺ type Si gate electrode 2 on p channel formation region
06 is formed.

Next, the gate insulating film (first insulating film) 204 and the polycrystalline Si film gate electrode 20 are formed using reactive ion etching (RIE).
5, 206 and the SiO ₂ film 207 are processed into a gate shape.

Next, after depositing a SiO ₂ film to a thickness of 10 nm on the entire surface by the CVD method, a gate sidewall 208 is formed on the side surfaces of the gate electrodes (first semiconductor layers) 205 and 206 by an RIE process. The thickness of the gate side wall 208 is about 10 nm from the side surfaces of the gate electrodes 205 and 206.

Next, as shown in FIG. 4, an SiN film is deposited over the entire surface to a thickness of 50 nm, and then the SiN film 2 is formed only on the p-channel transistor forming region by using a photolithography process.
Etching is performed so as to leave 09.

Next, phosphorus is grown at a temperature of 600 ° C. in a mixed gas of SiH ₄ , PH ₃ and HCl at 600 ° C.
The Si source semiconductor layer and the drain semiconductor layer (the second semiconductor layer of the first conductivity type) 210 containing 0 ²⁰ cm ⁻³ are selectively formed to a thickness of 70 nm only on the exposed portion (the n-channel transistor formation region) of the semiconductor substrate. accumulate. At this time, since the SiO ₂ film 207 exists on the gate electrode 205,
No polycrystalline Si gate electrode 2 without depositing Si layer
05 and Si source semiconductor layer and drain semiconductor layer 210
Have almost the same surface height.

The Si source semiconductor layer and the drain semiconductor layer 210 deposited by setting the deposition temperature to 600 ° C. or higher are single crystals. Therefore, the surfaces of the source semiconductor layer 210 and the drain semiconductor layer 210 facing the gate side wall 208 become {111} or {311} planes to form facets. Although the face orientation of the facet depends on the formation conditions, the facet is controlled so that the angle formed by the interface between the side surfaces of the source semiconductor layer and the drain semiconductor layer 210 and the semiconductor substrate is an acute angle. Then, the SiN film 209 on the p-channel transistor formation region is formed by hot phosphoric acid or dry etching.
Is removed.

Next, as shown in FIG.
After the entire surface is deposited to a thickness of 0 nm, the SiN film 21 is formed only on the n-channel transistor formation region by using a photolithography process.
Etching is performed so that 1 is left.

Next, a Si source semiconductor layer and a drain semiconductor layer containing 1 × 10 ²⁰ cm ^{−3 of} B (boron) are grown by vapor phase growth at 600 ° C. in a mixed gas of SiH ₄ , B ₂ H ₆ and HCl. The layer (second semiconductor layer of the second conductivity type) 212 is selectively formed only on the exposed portion (p-channel transistor formation region) of the semiconductor substrate to a thickness of 70 n.
m. At this time, the SiO ₂ film 2 is formed on the gate electrode 206.
07, the Si layer is not deposited, and the surface heights of the polycrystalline Si gate electrode 206 and the Si source semiconductor layer and the drain semiconductor layer 212 are almost the same.

The Si source semiconductor layer and the drain semiconductor layer 212 deposited by setting the deposition temperature to 600 ° C. or higher are single crystals. Therefore, the surfaces of the source semiconductor layer 212 and the drain semiconductor layer 212 facing the gate side wall 208 become {111} or {311} planes to form facets. The plane orientation of the facet depends on the formation conditions, but is controlled so that the angle formed by the interface between the side surface of the source semiconductor layer and the drain semiconductor layer 212 and the semiconductor substrate is an acute angle. Then, the SiN film 211 on the n-channel transistor formation region is formed by hot phosphoric acid or dry etching.
Is removed.

Next, as shown in FIG.
By performing heat treatment in an atmosphere for 60 minutes, phosphorus is diffused into the semiconductor substrate via the n-type Si source semiconductor and the drain semiconductor 210, and B (boron) is diffused through the p-type Si source semiconductor and the drain semiconductor 212, respectively. Thereby, an n-type source and drain region 213 and a p-type source and drain region 214 are formed, respectively. The source and drain regions 213 and 21
Since the depth of 4 is as shallow as about 10 nm to 20 nm in the semiconductor substrate, the short channel effect of the transistor can be sufficiently suppressed.

[0076] Next, as shown in FIG. 7, SiO ₂ on the entire surface
A film (second insulating film) 215 is deposited to a thickness of 100 nm.

Next, the gate electrodes (first semiconductor layers) 205 and 206, the source semiconductor layer and the drain semiconductor layer (first semiconductor layer) are formed in both the n-channel transistor formation region and the p-channel transistor formation region by using a CMP (chemical mechanical polishing) process. 2 semiconductor layers) 210, 212
The SiO ₂ film 215 is removed until the upper surface of the substrate appears.

Next, as shown in FIG. 8, after a resist (not shown) is left only on the n-channel transistor formation region by a photolithography process, a source semiconductor layer and a drain semiconductor layer (the second semiconductor layer) are formed by an RIE process. Part of the semiconductor layer 212 and the Si gate electrode (first semiconductor layer) 206 are cut away.

At this time, it should be noted that the polycrystalline S
While i206 is completely removed, single-crystal Si of the source semiconductor layer / drain semiconductor layer 212 is etched so that a part thereof remains on the bottom surface.

The end point of this etching is that a Ti (titanium) compound such as TiFx or Ti
Clx can be easily detected by being mixed. This Ti
The (titanium) compound is generated from the gate insulating film 204.
In this example, ideally, the etching is performed until the bottom surface comes to a position about 20 nm higher than the surface of the original source region and drain region 214. Then remove the resist,
Only the etched portion is left as a concave shape.

Next, as shown in FIG. 9, metal or silicide is used as a source electrode, a drain electrode, and a gate electrode.
In particular, for p-type Si, Schottky Barr
ierHeight: SBH), for example, Pt, PtSi, P
d is deposited on the entire surface. This deposition can be performed by any of CVD, sputtering and other general deposition methods.

Next, the entire surface is etched until the SiO ₂ film 215 is detected by CMP, so that the gate electrode 216 and the source and drain semiconductor layers (second semiconductor layers) 21
2, a source electrode and a drain electrode (metal or silicide) 216 are formed.

Next, as shown in FIG. 10, after a resist (not shown) is left only on the p-channel transistor by a photolithography process, a source semiconductor layer and a drain semiconductor layer (second semiconductor layer) are formed by an RIE process. ) 2
10 and Si gate electrode (first semiconductor layer) 20
Cut 5

At this time, it should be noted that the polycrystalline S
While i205 is entirely removed, the single-crystal Si of the source semiconductor layer and the drain semiconductor layer 210 is etched so that a part thereof remains on the bottom surface.

The end point of the etching can be easily detected by mixing a Ti compound such as TiFx or TiClx into the etching gas. In this example, ideally, the etching is performed until the bottom surface comes to a position higher than the surface of the original source region and drain region 213 by about 20 nm. Thereafter, the resist is removed so that only the etched portion remains as a concave shape.

Next, Schottky Barrier Height (SB) is used as a source electrode, a drain electrode, and a gate electrode against metal or silicide, particularly n-type Si.
A material having a low H), for example, ErSi ₂ is deposited on the entire surface. This deposition can be performed by any of CVD, sputtering and other general deposition methods.

Next, the entire surface is etched by CMP until the SiO ₂ film 215 is detected. Thus, the source electrode and the drain electrode (metal or silicide) 217 can be formed in the concave portion formed in the second semiconductor layer 210. At this time, the gate electrode 216 can be formed in the recess formed on the gate insulating film 204 at the same time.

Next, an LSI is formed by performing a usual process of depositing a SiO ₂ film (not shown) on the entire surface, making a contact hole (not shown), and providing a wiring (not shown).

In this embodiment, high dielectric TiO ₂ is used as an example of the gate insulating film 204. However, the present invention is not limited to this. Ta ₂ O ₅ , Al ₂ O ₃ , Y ₂ O ₃ , Zr
O ₂ , (Ba, Sr) TiO ₃ film or the like can be used.

Further, the TiO ₂ gate insulating film 204 is
Although formed by the CVD method, a sputtering method may be used.

When depositing a TiO ₂ gate insulating film, the entire surface of a wafer (semiconductor substrate) was irradiated with 200 W light through a window of a deposition apparatus so as to emit near-ultraviolet light having a wavelength of 300 nm.
A (watt) Xe (xenon) lamp may be operated. The lamp is operated before the deposition gas flows, and continues to irradiate until the deposition is completed. By doing so, the incorporation of C (carbon) and H (proton) from the organic source gas can be eliminated, and a film whose composition is completely TiO ₂ can be deposited.

The source gas for MOCVD deposition is not limited to the above combination, but may be TET (Ethyltitanat).
e) (Ti (OC ₂ H ₅ ) ₄ ) or TTIP (Titanium-tetrakis-isopr
A mixed gas of opoxide) and oxygen may be used. Also, T
In the case of TIP, TiO ₂ can be formed without mixing oxygen. Also, instead of organic source, Ti
An inorganic source may be deposited, such as Cl _4. However, in this case, it is desirable to set the reaction temperature slightly higher, for example, about 600 ° C.

The gate insulating film 204 does not necessarily need to be a high dielectric film as described above, but may be formed of SiO ₂ or Si.
N may be used.

The gate insulating film 204 does not have to use the insulating film deposited first. For example, in FIG. 8, after removing the polycrystalline Si 206 in the gate portion, the insulating film 204 is once removed, and another material (SiO ₂ , SiN, a high dielectric film, a ferroelectric film, or the like) is newly deposited to form a gate insulating film. You may use as.

At this time, of course, the gate insulating film 20
4 may be left partially. For example, in the process of FIG. 8, the source semiconductor layer and the drain semiconductor layer 212 are formed on the source region and the drain region 214 in a thickness of 40 nm instead of 20 nm.
If the TiO ₂ film is to be left with a thickness of 40 nm, the etching end point can be detected. However, a thickness of 40 nm may be too thick as a gate insulating film, but in that case, a process of reducing the thickness by 20 nm may be performed.

As a layer for preventing a reaction between the gate insulating film 204 and the gate electrode material, for example, a TiN layer may be provided on the TiO ₂ gate insulating film 204.

In the etching shown in FIG. 8, it is not always necessary to remove all the polycrystalline Si 206 in the gate portion. In this case, as shown in FIG.
1, 303 and polycrystalline Si 302, 304, and the gate electrode enjoys low resistance by metal.
Surface channelization of an n-channel transistor and a p-channel transistor using n-type Si and p-type Si can be performed. Of course, even in this case, the work functions of the metals provided for n and p can be set separately, so that the polycrystalline Si3
02, 304 and the metal 301, 303 can be minimized.

On the other hand, in the etching shown in FIG.
When all 6 are removed, the polycrystalline Si 205 and 206 containing different impurities may not include one kind of impurity (for example, phosphorus-diffused polycrystalline Si) or the impurity. However, in this case, it is difficult to control the same rate as the impurity-containing Si by the etching in FIG.

The single-crystal Si layers 210 and 2 deposited in the SEG (selective epitaxial growth) process
12 is not limited to being doped during CVD. For example, in the step of FIG. 4, single-crystal Si containing no impurity may be selectively deposited in advance on the exposed Si portions of the n-channel transistor formation region and the p-channel transistor formation region, and the impurities may be separately formed by ion implantation. This ion implantation may be performed immediately after the formation of the single crystal Si, or may be performed after the CMP of the insulating film 215 as shown in FIG. However, the pn junction cannot be precisely controlled to 10 nm to 20 nm in the substrate because the presence of point defects due to ion implantation makes it difficult to control impurity diffusion later. Therefore, the CVD simultaneous doping method is more preferable. Of course, CVD
In the doping method according to the above, the impurity amount may not be uniform in the thickness direction of Si. For example, a variation is conceivable in which the concentration is high near the Si substrate and low when far away.

Further, before depositing single-crystal Si, ions may be implanted to form pn junctions in the n-channel transistor formation region and the p-channel transistor formation region in advance.

In order to keep the selectivity high at the time of selective deposition of single-crystal Si, it is desirable to perform H ₂ annealing or vacuum annealing in a CVD apparatus at a temperature of about 800 ° C., for example. As a result, the exposure S
The natural oxide film on the surface of i can be removed, and Si with good crystallinity can be reliably formed on Si.

The crystallinity of the deposited single-crystal Si not only affects the reproducibility of the etching shown in FIG. 8, but also affects the characteristics of the device in the form of reproducibility of the contact resistance with the metal.

The insulating film 208 on the side surface of the gate formed before the source and drain semiconductor layers 210 and 212 are formed by selective CVD is formed by CVD and RIE, but the semiconductor layers 205 and 206 are oxidized or nitrided. It may be formed by performing the above.

Also, without forming the insulating film 208 on the side surface of the gate, the semiconductor layers 205 and 206 are formed by the gate insulating film 204.
And source and drain semiconductor layers 210 and 212
It is also possible to insulate it from. For example, the insulating layer 106
Can be insulated.

The materials 209 and 211 used as masks in the SEG process are not limited to SiN, and may be any material that can be easily removed selectively from a carbon film or SiO ₂ or Si. However, when a carbon film is used, an ashing technique cannot be used for removing the resist for processing the carbon film, and therefore, it is necessary to use a wet treatment (for example, a mixed solution of sulfuric acid and hydrogen peroxide solution). Needless to say, when the masks 209 and 211 are formed of a carbon film, they can be easily removed by ashing in removing them. Of course, the carbon film is represented here as a film that can be easily removed by ashing, and is a substance containing carbon. It is also possible to use another element such as Si or Ge as main component carbon.

In order to reduce the resistance of the source electrode and the drain electrode or the gate electrode, metal materials 216,
Although 17 uses an n-channel transistor and a p-channel transistor separately, the same transistor may be used. In this case, the recess for embedding the metal is n
Since it is not necessary to separately form a channel transistor and a p-channel transistor, the number of steps can be reduced. In this case, as the metal or the silicide, it is desirable to use the same SBH as the n-type Si and the p-type Si.

The metal layers 216 and 217 need not be a single layer. For example, n-type Si, p-type Si and S
After disposing a material having a low BH, a material having a low resistivity, for example, Al, W, or a noble metal is provided thereon, so that the resistance of the source electrode, the drain electrode, or the gate electrode can be reduced.

A salicide process may be used to form a metal silicide that is in direct contact with Si. However, when salicide is performed, a certain thickness of a Si layer is required before a pn junction thereunder. In order to reduce the thickness of the Si layer as much as possible by measures such as forming the silicide very thin, the rise of the parasitic capacitance between the gate electrode, the source electrode and the drain is suppressed, and the speeding up of the element is realized. It is valid.

The etching shown in FIG.
The method is not limited to anisotropic etching such as IE, but may be isotropic plasma etching containing, for example, CF ₄ , or may use a liquid such as hydrofluoric nitric acid.

When the anisotropic etching and the isotropic etching are used, the final shapes of the contact surfaces of the metal and the source electrode and the drain electrode are different as shown in FIGS.

Although the n-channel transistor and the p-channel transistor are formed by masking the respective regions in order to form them separately, it is not necessary to make these regions separately. , P-channel transistors.

The material having a lower SBH than the p-type Si is not limited to Pt (platinum) or Pd (palladium), but may be Ir (iridium), Ni (nickel), or a silicide thereof. It is.

The material having a lower SBH than n-type Si is not limited to ErSi ₂ , but Hf (hafnium), Ta (tantalum), Sc (scandium) or a silicide thereof can be used. .

In the field effect transistor shown in FIG. 10, focusing on the structures on the source region and the drain region 213 and 214, the source semiconductor layer and the drain semiconductor layer 2
The side surfaces of the reference numerals 10 and 212 are formed at an acute angle with respect to the surface of the semiconductor substrate. Therefore, the side surfaces of the source and drain semiconductor layers 210 and 212 and the side surfaces of the gate electrode face each other at an angle rather than in parallel, so that the parasitic capacitance can be minimized.

In addition, a concave portion is formed above the source semiconductor layer and the drain semiconductor layer, and the source electrode and the drain electrode are buried in the concave portion, so that the contact surface can be increased and the contact resistance can be reduced. I have. Of course, a shallow junction is formed so that the short channel effect does not occur, and the pn junction does not deteriorate in leak characteristics due to metal deposition.

Next, another method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS.

First, as shown in FIG. 12, a trench for STI (Shallow Trench Isolation) is dug in the Si substrate to a depth of about 0.4 μm in order to form an element isolation region 401 on the main surface of the semiconductor substrate. After that, SiO ₂ is deposited on the entire surface by the CVD method, and the CMP (Chemo-Mechanical)
(Polish) to flatten the entire surface.

Next, after the p-channel transistor formation region and the n-channel transistor formation region are respectively masked by a photolithography process, ion implantation is performed.
A mold well 403 and a p-type well 402 are formed.

Next, ions are implanted into each channel formation region for adjusting the threshold value of the transistor.

Next, the gate is placed on a Si substrate (semiconductor substrate).
TiO to become the gate insulating film (first insulating film) 404₂Membrane 40
4 to TPT (tetra-iso-propyltitanate) (Ti (OC
₃H ₇)₄) And oxygen at 380 ° C.
20 nm thick is deposited on the surface.

Next, polycrystalline Si is formed on the gate insulating film 404.
Ge (first semiconductor layer) is deposited on the entire surface with a thickness of 50 nm. The deposition method may be any method such as CVD or sputtering.

Next, a p-ch is formed by a photolithography process.
Mask channel formation region and n-channel formation region respectively
After that, ion implantation of P (phosphorus) and B (boron) is performed 1 ×.
10 ^Fifteencm^-2Do about.

Next, an SiO ₂ film 407 is deposited on the entire surface to a thickness of 20 nm. The deposition method may be any method such as CVD and sputtering. Next, impurities in the polycrystalline SiGe are activated by annealing (30 minutes in N ₂ at 800 ° C.), and the n-channel formation region is n ⁺ -type SiGe.
The gate electrode 405 and the p-channel formation region are p ⁺ -type SiG
It becomes the e-gate electrode 406.

Next, reactive ion etching (RIE)
Gate insulating layer (first insulating layer) 404, polycrystalline SiGe gate electrodes 405 and 406, and SiO ₂ film 4
07 is processed.

Next, after a SiO ₂ film is deposited to a thickness of 10 nm on the entire surface by the CVD method, a sidewall 408 having a thickness of about 10 nm is formed on the side surfaces of the gate electrodes (first semiconductor layers) 405 and 406 by the RIE process. To leave.

Next, as shown in FIG. 13, a 50 nm-thick SiN film is deposited over the entire surface, and then etched using a photolithography process so as to leave the SiN film 409 only on the p-channel transistor formation region.

Then, phosphorus is grown in a mixed gas of SiH ₄ , PH _3, and HCl at 600 ° C. in a vapor phase to make the phosphorus 1 × 1.
The thickness of the Si source semiconductor layer and the drain semiconductor layer (the second semiconductor layer of the first conductivity type) 410 containing 0 ²⁰ cm ⁻³ is selectively increased only in the exposed portion (the n-channel transistor formation region) of the semiconductor substrate. Deposit 20 nm.

Next, GeH ₄ , SiH ₄ ,
SiG containing 1 × 10 ²⁰ cm ^{−3 of} phosphorus is grown by vapor phase growth at 600 ° C. in a mixed gas of PH ₃ and HCl.
An e source semiconductor layer and a drain semiconductor layer (third semiconductor layer of a first conductivity type having a composition different from that of the second semiconductor layer) 411 are selectively deposited on the source semiconductor layer and the drain semiconductor layer 410 with a thickness of 50 nm. I do. At this time, since the SiO ₂ film 407 exists on the gate electrode 405, no Si layer or SiGe layer is deposited, and the surface heights of the polycrystalline SiGe gate electrode 405 and the Si source semiconductor layer and the drain semiconductor layer 410 are almost equal. Matches.

The Si or SiGe deposited at a deposition temperature of 600 ° C. or higher is a single crystal. Therefore, the surface of the source semiconductor layer 410 and the drain semiconductor layer 410 facing the gate sidewall 408 is {111} or {31}.
It becomes a 1｝ plane and forms a facet. Although the face orientation of the facet depends on the forming conditions, the facet is controlled so that the angle formed between the side surface of the source semiconductor layer and the drain semiconductor layer 410 and the interface between the semiconductor substrate and the semiconductor substrate becomes an acute angle. Thereafter, the SiN film 409 on the p-channel transistor formation region is removed by hot phosphoric acid or dry etching.

Next, as shown in FIG. 14, a 50 nm-thick SiN film is deposited over the entire surface and then etched using a photolithography process so that the SiN film 412 is left only on the n-channel transistor formation region.

Next, a Si source semiconductor layer and a drain semiconductor layer containing 1 × 10 ²⁰ cm ^{−3 of} B (boron) are grown by vapor phase growth at 600 ° C. in a mixed gas of SiH ₄ , B ₂ H ₆ and HCl. A layer (second semiconductor layer of the second conductivity type) 413 is selectively deposited to a thickness of 20 nm only on the exposed portion (p-channel transistor formation region) of the substrate.

Next, GeH ₄ , SiH ₄ ,
By performing vapor phase growth at 600 ° C. in a mixed gas of B ₂ H ₆ and HCl, an SiGe source semiconductor layer and a drain semiconductor layer containing B (boron) at 1 × 10 ²⁰ cm ⁻³ (the second semiconductor layer) Third of second conductivity type of different composition
Is deposited to a thickness of 50 nm. At this time, since the SiO ₂ film 407 exists on the gate electrode 406,
Polycrystalline SiG without depositing Si layer or SiGe layer
The surface heights of the e-gate electrode 406 and the Si source semiconductor layer and the drain semiconductor layer 413 are almost the same.

Further, Si or SiGe deposited at a deposition temperature of 600 ° C. or higher is a single crystal. Therefore, portions of the source semiconductor layer 413 and the drain semiconductor layer 413 which are in contact with the gate sidewall become {111} or {311} planes to form facets. The face orientation of the facet depends on the formation conditions, but is controlled so that the angle between the side surfaces of the source semiconductor layer and the drain semiconductor layer 413 and the interface with the semiconductor substrate is an acute angle. Thereafter, the SiN film 412 on the n-channel transistor formation region is removed by hot phosphoric acid or dry etching.

Next, as shown in FIG.
By performing a heat treatment in an r (argon) atmosphere for 60 minutes, the n-type Si source semiconductor layer and the drain semiconductor layer 410 are formed.
Is diffused into the semiconductor substrate through the p-type source semiconductor layer and the drain semiconductor layer 413, respectively, so that n-type source and drain regions 415, p-type source region and A drain region 416 is formed. The depth of the source and drain regions 415 and 416 is about 10 nm in the semiconductor substrate.
Since it is as shallow as 20 nm, the short channel effect of the transistor can be sufficiently suppressed.

Next, as shown in FIG.
_Two films (second insulating films) 417 are deposited to a thickness of 100 nm.

Next, the gate electrodes (first semiconductor layers) 405 and 406 are formed in both the n-channel transistor formation region and the p-channel transistor formation region by using a CMP process.
And the SiO ₂ film 41 until the upper surfaces of the source and drain semiconductor layers (third semiconductor layers) 411 and 414 appear.
7 is removed.

Next, as shown in FIG. 17, after a resist (not shown) is left only on the n-channel transistor formation region by a photolithography process, a source semiconductor layer and a drain semiconductor layer (third semiconductor layer) are formed by an RIE process. A part of the semiconductor layer 414 and the SiGe gate electrode (first semiconductor layer) 406 are cut off. In this case, by using a mixed gas of CF ₄ and Ar (argon) under appropriate conditions, S
Since iGe can be selectively removed with respect to Si, etching can be easily stopped at the interface between the source and drain semiconductor layers 411 and 410. Thereafter, the resist is removed so that only the etched portion remains as a concave shape.

Next, as shown in FIG.
Schottky barrier for metal or silicide, especially p-type Si as drain electrode and gate electrode
A material with a low Barrier Height (SBH), for example, Pt (platinum), PtSi, Pd (palladium) is deposited on the entire surface. This deposition can be performed by any of CVD, sputtering and other general deposition methods.

Next, the entire surface is etched by CMP until the SiO ₂ film 417 is detected. By doing so, the source and drain electrodes 418 can be formed in the concave portions formed over the source and drain semiconductor layers 413. At this time, the gate insulating film 4
The gate electrode 418 can be formed in the recess formed on the gate electrode 04.

As shown in FIG. 19, after leaving a resist (not shown) only on a p-channel transistor formation region by a photolithography process, a source semiconductor layer and a drain semiconductor layer (third semiconductor layer) by an RIE process
Part of 411 and gate electrode (first semiconductor layer) 407
Of SiGe. In this case, by using a mixed gas of CF ₄ and Ar (argon) under appropriate conditions, the SiG
e can be selectively removed with respect to Si,
Etching can be easily stopped at the interface between the source / drain semiconductor layer 411 and the source / drain semiconductor layer 410. Then remove the resist,
Only the etched portion is left as a concave shape. Thereafter, the resist is removed so that only the etched portion remains as a concave shape.

Next, a material having a low Schottky Barrier Height (SBH), for example, ErSi ₂ is deposited on the entire surface of the n-type Si. This deposition can be performed by any of CVD, sputtering and other general deposition methods. Further, a gate electrode 419, a source semiconductor layer, and a drain semiconductor layer (second semiconductor layer) are formed on a concave portion formed by etching the entire surface until the SiO ₂ film is detected by CMP, that is, on the gate insulating film 204.
A source electrode and a drain electrode (metal or silicide) 419 are formed on 410.

Next, an LSI is formed by performing a normal process of depositing a SiO ₂ film (not shown) over the entire surface, making a contact hole (not shown), and providing a wiring (not shown).

In this embodiment, high dielectric TiO ₂ is used as an example of the gate insulating film 410. However, the present invention is not limited to this. Ta ₂ O ₅ , Al ₂ O ₃ , Y ₂ O ₃ , ZrO _2
2 , a (Ba, Sr) TiO ₃ film or the like can be used.

Although TiO ₂ is formed by MOCVD, sputtering may be used.

When depositing the TiO ₂ gate insulating film 410, the wavelength 30 is applied to the entire surface of the wafer through the window of the deposition apparatus.
A 200 W (watt) Xe (xenon) lamp may be operated so that near-ultraviolet light of 0 nm is irradiated. The lamp is operated before the deposition gas flows, and continues to irradiate until the deposition is completed. By doing so, the incorporation of C (carbon) and H (proton) from the organic source gas can be eliminated, and a film whose composition is completely TiO ₂ can be deposited.

The source gas for MOCVD deposition is not limited to the above combination, but may be TET (Ethyltitan).
ate) (Ti (OC ₂ H ₅ ) ₄ ) or TTIP (Titanium-tetrakis-iso
A mixed gas of propoxide and oxygen may be used. Also,
In the case of TTIP, TiO ₂ can be formed without mixing oxygen. Also, instead of organic sauce, T
It may be deposited from an inorganic source such as iCl ₄ . However, in this case, it is desirable to set the reaction temperature slightly higher, for example, about 600 ° C.

The insulating film 404 of the gate does not necessarily have to be a high dielectric film as described above, but may be made of SiO ₂ or S
iN may be used.

Further, the gate insulating film formed as 404 need not be used as it is. For example, in FIG. 17, after removing the polycrystalline SiGe 406 in the gate portion, the insulating film 404 is removed once and another material (SiO ₂ , S
iN, a high dielectric film, a ferroelectric film) may be deposited and used as a gate insulating film.

At this time, of course, the gate insulating film 40
4 may be left partially. For example, in the process of FIG.
In order to sufficiently clean the surface of the TiO ₂ film 404 after removing e, the thickness may be reduced to 40 nm in advance, and the thickness may be reduced to 20 nm in this step.

As a layer for preventing a reaction between the gate insulating film and the gate electrode material, for example, a TiN layer may be provided on the TiO ₂ gate insulating film 404.

In the etching shown in FIG. 17, it is not always necessary to remove all the polycrystalline SiGe 407 in the gate portion. At this time, as shown in FIG. 11, the gate electrode has a laminated structure of metals 301 and 303 and polycrystalline SiGe 302 and 304, and the gate electrode enjoys low resistance by the metal while n-type SiGe and p-type SiGe It is possible to make the surface channel of the n-channel transistor and the p-channel transistor by the above. Of course, even in this case, the work functions of the metals placed on n and p can be set separately, so that the polycrystalline SiGe 302, 304 and the metal 301,
The contact resistance between 303 can be minimized.

On the other hand, as shown in FIG.
In the case of removing all of the e406, the polycrystalline SiGe 405 and 406 containing different impurities may not include one kind of impurity (for example, phosphorus-diffused polycrystalline SiGe) or impurities. However, in this case, it is difficult to control the etching rate of FIG. 17 to the same rate as that of the impurity-containing SiGe.

Further, single-crystal Si deposited in the SEG process
Ge 411, 414 is not limited to being doped during CVD. For example, in the step of FIG. 13, single-crystal Si containing no impurity is selectively deposited in advance on the exposed Si portions of the n-channel transistor formation region and the p-channel transistor formation region, and then the single-crystal S
iGe may be selectively deposited, and the impurities contained may be separately formed by ion implantation later. This ion implantation is performed using single crystal Si.
It may be performed immediately after Ge formation or after CMP of the insulating film 417 in FIG. However, since point defects due to ion implantation make it difficult to control impurity diffusion later, p
The n-junction cannot be precisely controlled to 10 nm to 20 nm in the substrate. Therefore, the CVD simultaneous doping method is more preferable in this case. Of course, in the doping method by CVD, the amount of impurities may not be uniform in the thickness direction of Si. For example, a variation is conceivable in which the concentration is high near the Si substrate and low when far away.

Further, pn junctions of an n-channel transistor and a p-channel transistor may be formed in advance by performing ion implantation before depositing single-crystal Si.

In the selective deposition of single-crystal Si, it is desirable to perform H ₂ annealing or vacuum annealing in a CVD apparatus at a temperature of about 800 ° C., for example, in order to maintain high selectivity. As a result, the exposure S
The natural oxide film on the surface of i can be removed, and Si with good crystallinity can be reliably formed on Si.

FIG. 17 shows the crystallinity of the deposited single crystal Si.
In addition to affecting the reproducibility of the etching in the device, the reproducibility of the contact resistance with the metal has an effect on the characteristics of the device.

In order to reduce the resistance of the source electrode and the drain electrode or the gate electrode, metal materials 418,
Although 19 uses separate n-channel transistors and p-channel transistors, it is of course possible to use one type. In this case, it is not necessary to separately form the n-channel transistor and the p-channel transistor for the recess for embedding the metal, which is effective in shortening the process. In this case, as the metal or the silicide, it is desirable to use the same SBH as the n-type Si and the p-type Si.

The metal layers 418 and 419 do not need to be one layer. For example, n-type Si, p-type Si and SB
After placing the low H material, the low resistivity material, eg, A
By installing l (aluminum), W (tungsten) or a noble metal thereon, the resistance of the source electrode and the drain electrode or the gate electrode can be reduced.

A salicide process may be used to form a metal silicide in direct contact with Si. However, if the salicide process is performed, a certain thickness of a Si layer is required before a pn junction below the salicide process. In order to reduce the thickness of the Si layer as much as possible by making the silicide very thin, etc., the rise of the parasitic capacitance between the gate electrode, the source electrode, and the drain electrode is suppressed, thereby realizing a high-speed device. It is effective for

The etching of SiGe shown in FIG. 17 is not limited to RIE, but may be isotropic plasma etching containing, for example, CF ₄ , or etching using a liquid such as hydrofluoric nitric acid. Good.

Further, when anisotropic etching and isotropic etching are used, the shapes of the final metal and the contact surfaces of the source electrode and the drain electrode are different as shown in FIGS.

Although the n-channel transistor and the p-channel transistor are formed by masking the respective regions in order to make them separately, it is not necessary to make these regions separately. , P-channel transistors.

The material having a lower SBH than p-type Si is not limited to Pt (platinum) or Pd (palladium), but may be Ir (iridium), Ni (nickel), or a silicide thereof. It is.

The material having a lower SBH than n-type Si is not limited to ErSi ₂ , but Hf (hafnium), Ta (tantalum), Sc (scandium), or a silicide thereof can be used. .

In addition, the two regions on the source region and the drain region
The lower semiconductor layer is formed of Si and the upper layer is formed of SiGe. However, the opposite may be adopted, in which the lower layer is formed of SiGe and the upper layer is formed of Si. At this time, it should be noted that the selective etching of SiGe corresponding to FIG. 17 is the selective etching of Si with respect to SiGe. At this time, it is necessary to change the etching solution. For example, by using 10 wt% ammonia water or the like, Si can be etched with high selectivity to SiGe. In this case, as the gate material in FIG.
It is better to use Si instead of iGe. In this case, the contact with the metals 418 and 419 is made of SiGe instead of Si, so that a lower contact resistance can be expected especially in a p-channel transistor.

Although the concentration of SiGe was set to 1: 1,
It is not limited to this concentration ratio. However, in single crystal growth on Si, strain is introduced due to the difference in lattice constant,
It has been pointed out that if it is too large, defects will be introduced, so it is desirable to keep the Ge concentration low enough to ensure a sufficient etching selectivity.

Further, although SiGe was used as the second semiconductor, the present invention is not limited to this, and SiC or the like may be used. In addition, any other material that can be deposited on Si with very high selectivity similar to SEG and that can be etched with a high selectivity to Si may be used.

Next, another method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS.

First, as shown in FIG. 20, an element isolation region 503, a gate insulating film (first insulating film) 504, Si films (first semiconductor layers) 505 and 50 are formed on a main surface of a semiconductor substrate.
6, gate sidewall 508, SiO ₂ insulating film 507, Si source semiconductor layer and drain semiconductor layer (first and second conductivity type second semiconductor layers) 509, 510 are formed, and shallow n ⁺ , p ⁺ diffusion The steps up to the point where the layers 511 and 512 are formed are the same as those in the method for manufacturing the semiconductor device described with reference to FIGS.

Next, as shown in FIG.
_Two films (second insulating films) 513 are deposited to a thickness of 100 nm.

Next, the gate electrodes (first semiconductor layers) 505 and 506 and the source and drain semiconductor layers (second semiconductor layers) are formed in both the n-channel transistor formation region and the p-channel transistor formation region using a CMP process. The SiO ₂ film (second insulating film) 513 is removed until the upper surfaces of 509 and 510 appear.

Then, as shown in FIG. 22, the gate electrode portion is oxidized by the heat treatment from the surface until the TiO ₂ film 504 is reached, that is, the Si films 505 and 506 are oxidized by 50 nm, and at the same time, the Si source semiconductor and the drain semiconductor (the 2) and oxidized so that a part of 509 and 510 remains, and
An O ₂ film 514 is formed. At this time, the surfaces of the source semiconductor layer and the drain semiconductor layers 509 and 510 are oxidized so that a thickness of 20 nm remains from the semiconductor substrate interface. At this time, it is desirable to use the same condition that the oxidation rate of Si doped with phosphorus and B (boron) is the same. At this time, oxidation proceeds isotropically from the surfaces of the Si source semiconductor layer and the drain semiconductor layers 509 and 510 containing impurities,
The source and drain semiconductor layers 509 and 510 form a recess.

Next, as shown in FIG. 23, after a resist (not shown) is left only on the n-channel transistor formation region by a photolithography process, the p-channel transistor formation region is diluted with a solution containing dilute HF (hydrofluoric acid). The SiO ₂ film 514 on the source and drain semiconductor layers 510 and the gate insulating film 504 is removed. At this time, the SiO ₂ film 513 formed by CVD does not contain impurities, whereas the SiO ₂ film 514 has a large amount of B (boron).
, The etching rate by the dilute HF solution is high, the SiO ₂ film 514 is etched as shown in FIG. 23, and the SiO ₂ film 513 is hardly scraped.

Next, as a source electrode, a drain electrode and a gate electrode, Schottky barrier (Schottky Barrier Height: SBH) is used for metal or silicide, especially for p-type Si.
For example, Pt (platinum), PtSi, and Pd (palladium) are deposited over the entire surface. This deposition can be performed by any of CVD, sputtering and other general deposition methods.

Next, as shown in FIG. 24, the entire surface is etched until the SiO ₂ film 513 is detected by CMP. Thus, the source and drain electrodes 515 can be formed in the concave portions formed over the source and drain semiconductor layers 510. At the same time, the gate electrode 515 can be formed in the concave portion formed over the gate insulating film 504.

Next, as shown in FIG. 25, after leaving a resist (not shown) only on the p-channel transistor formation region by a photolithography process, the source semiconductor of the n-channel transistor formation region is diluted with a solution containing dilute HF. Layer and drain semiconductor layer 514 and gate portion Si
The O ₂ film 514 is removed. At this time, Si formed by CVD
O ₂ film 513 whereas not include impurities, SiO ₂
Since the film 514 contains a large amount of phosphorus, the etching rate with a dilute HF solution is high, the SiO ₂ film 514 is etched, and the SiO ₂ film 513 is hardly removed.

Next, Schottky Barrier Height (SBH) is used as a source electrode, a drain electrode, and a gate electrode for metal or silicide, especially n-type Si.
A low-e.g. Material such as ErSi ₂ is deposited over the entire surface. This deposition can be performed by any of CVD, sputtering and other general deposition methods.

Next, the entire surface is etched by CMP until the SiO ₂ film 513 is detected. Thus, the source and drain electrodes 217 can be formed in the concave portions formed over the source and drain semiconductor layers 509. In addition, the gate electrode 514 can be formed in the concave portion formed over the gate insulating film 504 at the same time.

Next, an LSI is formed by performing a normal process of depositing a SiO ₂ film (not shown) over the entire surface, making a contact hole (not shown), and providing a wiring (not shown).

In this method of manufacturing a semiconductor device, the gate
As an example of the edge film 504, high dielectric TiO is used.₂Was used,
Without being limited to this, Ta₂O₅, Al
₂O₃, Y ₂O₃, ZrO₂, (Ba, Sr) TiO₃
A film or the like can be used.

Although TiO ₂ is formed by MOCVD, sputtering may be used.

When depositing a TiO ₂ film, a 200 W (watt) Xe (xenon) lamp may be operated so that near-ultraviolet light having a wavelength of 300 nm is irradiated onto the entire surface of the wafer through the window of the deposition apparatus. The lamp is operated before the deposition gas flows, and continues to irradiate until the deposition is completed.
By doing so, the incorporation of C and H from the organic source gas can be eliminated, and a film whose composition is completely TiO ₂ can be deposited.

The source gas for MOCVD deposition is not limited to the above combination, but may be TET (Ethyltitan).
ate) (Ti (OC ₂ H ₅ ) ₄ ) or TTIP (Titanium-tetrakis-iso
A mixed gas of propoxide and oxygen may be used. Also T
In the case of TIP, TiO ₂ can be formed without mixing oxygen. Also, instead of organic source, Ti
It may be deposited from inorganic sources such as Cl _4. However, in this case, it is desirable to set the reaction temperature slightly higher, for example, about 600 ° C.

The gate insulating film does not necessarily need to be a high dielectric film as described above, but may be SiO ₂ or SiN.

In FIG. 22, it is not always necessary to oxidize all the polycrystalline Si in the gate portion. When a part of the polycrystalline Si is left, the gate electrode has a laminated structure of a metal and a polycrystalline semiconductor layer as shown in FIG. 11, and the gate electrode enjoys low resistance by the metal while n-channel Si and p-type Si are used. The surface channel of the transistor and the p-channel transistor can be formed. Of course, even in this case, n,
Since the work function can be set separately for the metal placed on p, the contact resistance between polycrystalline Si and the metal can be minimized.

In the case where all the polycrystalline Si in the gate portion is oxidized in the thermal oxidation step of FIG. 22, the polycrystalline Si 505 and 506 containing separate impurities are one kind of impurity (for example, phosphorus diffusion polycrystalline Si) or an impurity. May not be included.
However, in this case, it is difficult to control the same rate as the impurity-containing Si by the oxidation shown in FIG.

In addition, single-crystal Si deposited in the SEG process
Layers 506, 505 are not limited to being doped during CVD. For example, single-crystal Si containing no impurity may be selectively deposited in advance on the exposed portions of the n-channel transistor and the p-channel transistor, and the impurities may be separately formed by ion implantation. This ion implantation may be performed immediately after the formation of the single-crystal Si, or the insulating film 5 shown in FIG.
13 may be performed after the CMP. However, the pn junction cannot be precisely controlled to 10 nm to 20 nm in the substrate because the presence of point defects due to ion implantation makes it difficult to control impurity diffusion later. Therefore, the CVD simultaneous doping method is more preferable. Of course, in the doping method by CVD, the amount of impurities may not be uniform in the thickness direction of Si. For example, Si
Variations can be considered in which the concentration is high near the substrate and low when far away.

Before depositing single-crystal Si, ions may be implanted to form pn junctions of an n-channel transistor and a p-channel transistor in advance.

In order to keep the selectivity high at the time of selective deposition of single-crystal Si, it is desirable to perform H ₂ anneal or vacuum anneal in a CVD apparatus at a temperature of about 800 ° C., for example. As a result, the exposure S
The natural oxide film on the surface of i can be removed, and Si with good crystallinity can be reliably formed on Si. The crystallinity of the deposited single crystal Si affects the characteristics of the device in the form of reproducibility of the contact resistance with the metal later.

In addition, one kind of metal material 516, 515 for lowering the resistance of the source electrode, the drain electrode, and the gate electrode may be used. In this case, there is no need to separately form n and p recesses for embedding the metal, which is effective in shortening the process. In this case, as the metal or the silicide, it is desirable to use the same SBH as the n-type Si and the p-type Si.

The metal layers 516 and 515 need not be one layer. For example, n-type Si and p-type Si and SB
After placing the low H material, the low resistivity material, eg, A
It is also possible to lower the resistance of the source electrode, the drain electrode, and the gate electrode by installing l, W, or a noble metal thereon.

Also, in forming metal silicide in direct contact with Si, if salicide is performed, an Si layer of a certain thickness is required before the pn junction below it.
By making the thickness of the SI layer as thin as possible by measures such as forming the silicide very thin, the rise of the parasitic capacitance between the gate electrode, the source electrode and the drain electrode is suppressed,
This is effective for realizing a high-speed device.

Further, the oxidation step shown in FIG. 22 is not limited to the step using dry oxygen, the step using steam oxygen, the step using radical oxygen, the step using dilute oxygen, and the step using HC.
Any method such as an oxidizing atmosphere in which a gas such as 1 (hydrochloric acid) is mixed can be used.

In this oxidation step, it is not necessary to oxidize all the desired thicknesses at one time.
Oxidation → etching may be repeated a plurality of times.

Although the etching of the oxide film is described as a wet type in this embodiment, a dry type method such as plasma etching may be used.

In FIG. 20, the deposited semiconductor 50
9 and 510 are formed as a single layer, but as a semiconductor film (third semiconductor film) different from Si, for example, a multilayer is formed using SiC, and the entire SiC portion is oxidized and removed due to a difference in oxidation rate. It is also possible to improve the controllability of the thickness of the remaining film Si by the method described above.

Although the n-channel transistor and the p-channel transistor are formed by masking their respective regions, they need not be formed separately, and may be formed separately from the n-channel transistor. , P-channel transistors.

The material having a lower SBH than p-type Si is not limited to Pt (platinum) or Pd (palladium), but may be Ir (iridium), Ni (nickel), or a silicide thereof. It is.

The material whose SBH is lower than that of n-type Si is not limited to ErSi ₂ , but Hf (hafnium), Ta (tantalum), Sc (scandium) or a silicide thereof can be used. .

In the field-effect transistor shown in FIG. 25, focusing on the structure on the source and drain regions 511 and 512,
9 and 510 are formed at an acute angle to the semiconductor substrate so that the parasitic capacitance between the source and drain electrodes and the gate electrode is minimized.

In addition, a concave portion is formed on the upper surface of the source semiconductor layer and the drain semiconductor layer, and the source electrode and the drain electrode are buried in the concave portion, so that the contact surface can be increased and the contact resistance can be reduced. ing. Of course, a shallow junction is formed so that the short channel effect does not occur, and the pn junction does not deteriorate in leak characteristics due to metal deposition.

Further, in consideration of the CMOS structure, the p-channel transistor and the n-channel transistor have a feature that makes it easy to use another material as a metal material.
Therefore, the parasitic resistance of both transistors can be extremely reduced at the same time.

At the same time, the gate electrode material is a material having a work function close to the level of the conduction band edge Ec of Si in the case of an n-channel transistor, while the material of the valence band edge Ev of Si is realized in the case of a p-channel transistor. Since it is possible to install a material having a work function close to the level, it is possible to design both transistors into an element having a channel formed on the surface while having a metal gate structure, which is very preferable for suppressing a short channel effect. Structure, process.

Next, another method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS.

First, as shown in FIG. 28, in order to form an element isolation region 701 on a seed surface of a semiconductor substrate, a groove for STI (Shallow Trench Isolation) is dug in the Si substrate 1 to a depth of about 0.4 μm. After that, SiO ₂ is deposited on the entire surface by the CVD method, and the CMP (Chemo-Mechanical) is performed.
(Polish) to flatten the entire surface.

Next, after the p-channel transistor formation region and the n-channel transistor formation region are respectively masked by a photolithography process, ion implantation is performed.
A mold well 703 and a p-type well 702 are formed.

Next, ions are implanted into each channel for adjusting the threshold value of the transistor.

Next, the gate is placed on a Si substrate (semiconductor substrate).
TiO to become a gate insulating film (first insulating film) 704₂Membrane 70
4 to TPT (tetra-iso-propyltitanate) (Ti (OC
₃H ₇)₄) And oxygen at 380 ° C.
20 nm thick is deposited on the surface.

Next, polycrystalline Si is formed on the gate insulating film 704.
(First semiconductor layer) is deposited on the entire surface with a thickness of 50 nm. The deposition method may be any method such as CVD and sputtering.

Next, a p-ch is formed by a photolithography process.
Mask channel formation region and n-channel formation region respectively
After that, ion implantation of P (phosphorus) and B (boron) is performed 1 ×.
10 ^Fifteencm^-2Do about.

Next, an SiO ₂ film is deposited over the entire surface to a thickness of 20 nm. The deposition method may be any method such as CVD and sputtering. Next, impurities in the polycrystalline Si are activated by annealing (at 800 ° C. for 30 minutes in N ₂ ), and the n-channel forming region is n ⁺ -type Si gate electrode 7.
05, p-channel formation region is p ⁺ type Si gate electrode 70
It becomes 6.

Next, reactive ion etching (RIE)
Gate insulating film (first insulating film) 704, polycrystalline Si gate electrodes 705 and 706, and SiO ₂ film 707
Is processed into a gate shape. At this time, the direction of the gate length is <
Processing is performed so as to be in the <100> direction instead of the 110> direction.

Next, after depositing a SiO ₂ film to a thickness of 10 nm on the entire surface by the CVD method, gate sidewalls 708 are formed on the side surfaces of the gate electrodes (first semiconductor layers) 705 and 706 by an RIE process. The thickness of the gate side wall 708 is about 10 nm from the side of the gate electrode. Next, FIG.
As shown in (1), after a SiN film is deposited over the entire surface to a thickness of 50 nm, etching is performed using a photolithography process so as to leave the SiN film 709 only on the p-channel transistor formation region.

Next, phosphorus is grown in a mixed gas of SiH ₄ , PH _3, and HCl at 600 ° C. in a vapor phase to make phosphorus 1 × 1
The thickness of the Si source semiconductor layer and the drain semiconductor layer (the second semiconductor layer of the first conductivity type) 710 containing 0 ²⁰ cm ⁻³ is selectively increased only in the exposed portion (the n-type transistor formation region) of the semiconductor substrate. Deposit 70 nm. At this time, since the SiO ₂ film 707 is not deposited on the gate electrode 705, the polycrystalline Si gate electrode 70 is not deposited.
5, silicon source semiconductor layer and drain semiconductor layer 71
The surface heights of 0 almost coincide.

Further, Si deposited at a temperature of 600 ° C. or more is a single crystal. Therefore, the portion in contact with the gate side wall becomes {110} and forms a facet.
However, in this case, the silicon grows faster than the case where facets are formed on the {111} plane, so that silicon also grows on the gate sidewall 708 and the STI 701. Therefore, the source semiconductor layer and the drain semiconductor layer 710
The side surface facing the gate electrode 705 is in contact with the gate side wall 708 with a slight film thickness from the surface of the semiconductor substrate,
From there, an acute angle is formed with respect to the semiconductor substrate surface.

Then, the SiN film 709 on the p-channel formation region is removed by hot phosphoric acid or dry etching.

Next, as shown in FIG. 30, after depositing a 50 nm-thick SiN film over the entire surface, a photolithography process is used to form a Si film only on the n-channel transistor formation region.
Etching is performed so as to leave the N film 711.

Next, in a mixed gas of SiH ₄ , B ₂ H ₆ and HCl at 600 ° C., B (boron) is 1 × 10 ²⁰ cm ^−3.
The contained Si source semiconductor layer and drain semiconductor layer (second semiconductor layer of the second conductivity type) 712 are selectively deposited to a thickness of 70 nm only on the exposed portion (p-channel transistor formation region) of the semiconductor substrate. At this time, the gate electrode 7
Since the SiO ₂ film 707 exists on the surface of the polycrystalline Si gate electrode 706 and the Si
The surface heights of the source semiconductor layer and the drain semiconductor layer 712 are almost the same.

[0219] The Si source semiconductor layer and the drain semiconductor layer 712 deposited at a deposition temperature of 600 ° C or higher are single crystals. Therefore, the portions of the source semiconductor layer 712 and the drain semiconductor layer 712 which are in contact with the gate side wall become {110} and form a facet. However, in this case, since the growth of silicon is faster than the case where facets are formed on the {111} plane, the gate side wall 708 is formed.
Also, Si grows on the STI 701. Accordingly, the gate electrodes 705 of the source and drain semiconductor layers 712
Is in contact with the gate side wall 708 at a slight film thickness from the surface of the semiconductor substrate, and forms an acute angle with respect to the surface of the semiconductor substrate therefrom.

After that, the SiN film 709 on the p-channel formation region is removed by hot phosphoric acid or dry etching.

The subsequent steps are the same as those described with reference to FIGS.

[0222]

As described above, the semiconductor device according to the present invention can be designed so that the source and drain semiconductor layers are in contact with the semiconductor substrate at an acute angle so that the parasitic capacitance is minimized. In addition, since a concave portion is formed above the source semiconductor layer and the drain semiconductor layer, and the source electrode and the drain electrode are buried in the concave portion, the contact surface can be increased and the contact resistance can be reduced.

The method of manufacturing a semiconductor device according to the present invention
Since the source electrode, the drain electrode, and the gate electrode are formed by etching back after the entire surface is deposited without using selective metal growth, there is no short circuit between the source electrode and the drain electrode, and the yield can be improved. .

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor device of the present invention.

FIG. 2 is a cross-sectional view of a semiconductor device of the present invention.

FIG. 3 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.

FIG. 4 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.

FIG. 5 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.

FIG. 6 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.

FIG. 7 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.

FIG. 8 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.

FIG. 9 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.

FIG. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.

FIG. 11 is a cross-sectional view of a semiconductor device of the present invention.

FIG. 12 is a sectional view illustrating a method for manufacturing another semiconductor device of the present invention.

FIG. 13 is a sectional view illustrating a method for manufacturing another semiconductor device of the present invention.

FIG. 14 is a sectional view illustrating a method for manufacturing another semiconductor device of the present invention.

FIG. 15 is a sectional view illustrating a method for manufacturing another semiconductor device of the present invention.

FIG. 16 is a sectional view illustrating a method for manufacturing another semiconductor device of the present invention.

FIG. 17 is a cross-sectional view illustrating a method for manufacturing another semiconductor device of the present invention.

FIG. 18 is a sectional view illustrating a method for manufacturing another semiconductor device of the present invention.

FIG. 19 is a sectional view illustrating a method for manufacturing another semiconductor device of the present invention.

FIG. 20 is a sectional view illustrating a method for manufacturing another semiconductor device of the present invention.

FIG. 21 is a cross-sectional view illustrating a method for manufacturing another semiconductor device of the present invention.

FIG. 22 is a sectional view illustrating a method for manufacturing another semiconductor device of the present invention.

FIG. 23 is a cross-sectional view illustrating another method for manufacturing a semiconductor device of the present invention.

FIG. 24 is a cross-sectional view illustrating another method for manufacturing a semiconductor device of the present invention.

FIG. 25 is a cross-sectional view illustrating a method for manufacturing another semiconductor device of the present invention.

FIG. 26 is a cross-sectional view of a conventional semiconductor device.

FIG. 27 is a cross-sectional view of a conventional semiconductor device.

FIG. 28 is a cross-sectional view illustrating another method for manufacturing a semiconductor device of the present invention.

FIG. 29 is a cross-sectional view illustrating a method for manufacturing another semiconductor device of the present invention.

FIG. 30 is a cross-sectional view illustrating a method for manufacturing another semiconductor device of the present invention.

[Explanation of symbols]

101, 200, 300, 400, 500, 1101,
1201... Si substrate 201, 401, 503... Element isolation region 202, 402, 501... P-well region 203, 403, 502. TiO ₂ ) 205, 405, 302, 505: phosphorus-doped Si 206, 406, 304, 506: B-doped Si 207, 407, 507: SiN cap 104, 208, 408, 508, 1104, 1204
... Gate sidewalls 209, 211, 409, 412 ... SiN film 105, 210, 410, 509, 1205 ... n ⁺ Si
Deposited layer 212,413,510 ... p ⁺ Si deposited layer 107,213,415,511,1105 ... n ⁺ Si
Diffusion layers 214,416,512 ... p ⁺ Si diffusion layer 106,215,417,513 ... SiO ₂ film 216,304,418,515 ... ^p + Si to SB
H is low metal 108,217,301,419,516 ... ⁿ + Si SBH low metal 411 ... to n ⁺ SiGe deposition layer 414 ... p ⁺ SiGe deposition layer 514 ... the SiO ₂ layer 1102 and 1202 ... gate SiO ₂ layer 1103, 1203: gate and other crystal Si electrode layers 1106, 1206: silicide layer

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/092 H01L 27/08 321D 29/43 321F 21/336 29/62 G 29/78 301P 301X 301Q F Terms (reference) 4M104 AA01 BB01 BB06 BB07 BB17 BB19 BB22 BB27 BB30 BB37 CC05 DD03 DD04 DD26 DD37 DD43 DD46 DD66 EE03 EE09 EE16 EE17 FF13 FF14 FF18 GG09 GG10 GG14 HH16 5F040 EC10 EC03 EC03 EC03 EC03 EC03 EC04 EF03 EF09 EH01 EH02 EH07 EK05 FA02 FA05 FC02 FC06 FC21 FC22 5F048 AA00 AA01 AC03 BA01 BA10 BB04 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB14 BC01 BE03 BF06 BF07 BF16 BG14 DA25

Claims (10)

[Claims] A semiconductor substrate; a gate insulating film formed on the semiconductor substrate; a gate electrode formed on the gate insulating film; a channel region formed below the gate insulating film; A source region and a drain region which are formed so as to be separated from each other and are provided so that the channel region is located therebetween; a source semiconductor layer formed on the source region; and a A drain electrode formed on the source semiconductor layer, a drain electrode formed on the drain semiconductor layer, and a gate electrode of the source semiconductor layer and the drain semiconductor layer. The angle formed between the opposing side surface and the surface where the source semiconductor layer and the drain semiconductor layer are in contact with the semiconductor substrate forms an acute angle, and Wherein a said source electrode and said drain electrode is formed on the upper part formed recesses of the scan semiconductor layer and the drain semiconductor layer. 2. The semiconductor device according to claim 1, wherein said semiconductor device comprises an n-channel MIS field-effect transistor and a p-channel MIS field-effect transistor, wherein said source electrode and said drain electrode of said n-channel MIS field-effect transistor are said p-channel MIS field-effect transistor. 2. The semiconductor device according to claim 1, wherein said semiconductor device is different from said source electrode and said drain electrode. 3. The semiconductor device includes an n-channel MIS field-effect transistor and a p-channel MIS field-effect transistor, wherein the gate electrode of the n-channel MIS field-effect transistor is the gate electrode of the p-channel MIS field-effect transistor. The semiconductor device according to claim 1, wherein the semiconductor device is different from the semiconductor device. 4. The semiconductor device according to claim 1, wherein said angle is not less than 10 ° and not more than 80 °. 5. The semiconductor device according to claim 1, wherein a surface where the source semiconductor layer and the drain semiconductor layer are in contact with the source electrode and the drain electrode region, respectively, is formed by anisotropic etching. 6. The semiconductor device according to claim 1, wherein a surface where said source semiconductor layer and said drain semiconductor layer are in contact with said source electrode and said drain electrode region, respectively, is formed by isotropic etching. 7. A step of forming a first insulating film on a semiconductor substrate, a step of depositing a first semiconductor layer on the first insulating film, and a step of forming the first insulating film and the first semiconductor Patterning a layer; and forming a second surface of first and second conductivity types on a main surface of the semiconductor substrate.
Forming a second insulating film on the first insulating film, the first semiconductor layer, and the second semiconductor layer; and forming the second insulating film on the first insulating film. Removing the first semiconductor layer and the second semiconductor layer until the upper surfaces thereof appear; removing the first semiconductor layer and the second semiconductor layer so that at least a part of the second semiconductor layer remains; And a step of depositing a metal or a silicide on the second semiconductor layer. 8. A step of forming a first insulating film on a semiconductor substrate, a step of depositing a first semiconductor layer on the first insulating film, and a step of forming the first insulating film and the first insulating film. Patterning a semiconductor layer; and forming a second surface of first and second conductivity types on a main surface of the semiconductor substrate.
Forming a third semiconductor layer of a first and second conductivity type having a composition different from that of the second semiconductor layer on the second semiconductor layer; Depositing a second insulating film on a first insulating film, the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer; Removing the semiconductor layer and the third semiconductor layer until the top surfaces thereof appear;
A method of removing a semiconductor layer until the upper surface of the second semiconductor layer appears, and a step of depositing a metal or a silicide on the upper surface of the second semiconductor layer. 9. A step of forming a first insulating film on a semiconductor substrate, a step of depositing a first semiconductor layer on the first insulating film, and a step of forming the first insulating film and the first insulating film. Patterning a semiconductor layer; and forming a second surface of first and second conductivity types on a main surface of the semiconductor substrate.
Forming a second insulating film on the first insulating film, the first semiconductor layer, and the second semiconductor layer; and forming the second insulating film on the first insulating film. Removing the first semiconductor layer and the second semiconductor layer until the upper surfaces thereof appear; and oxidizing the first semiconductor layer and the second semiconductor layer so that at least a part of the second semiconductor layer remains. Performing a step of removing oxidized portions of the first semiconductor layer and the second semiconductor layer; and depositing a metal or a silicide on the second semiconductor layer. A method for manufacturing a semiconductor device. 10. A step of forming a first insulating film on a semiconductor substrate, a step of depositing a first semiconductor layer on the first insulating film, and a step of forming the first insulating film and the first Patterning a semiconductor layer; and forming a second surface of first and second conductivity types on a main surface of the semiconductor substrate.
Forming a third semiconductor layer of a first and second conductivity type having a composition different from that of the second semiconductor layer on the second semiconductor layer; Depositing a second insulating film on a first insulating film, the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer; Removing the semiconductor layer and the third semiconductor layer until the upper surface thereof appears, oxidizing the first semiconductor layer and the third semiconductor layer, and removing the upper surface of the second semiconductor layer until the upper surface of the second semiconductor layer appears A method for manufacturing a semiconductor device, comprising: a step of removing an oxide film of a first semiconductor layer and a third semiconductor layer; and a step of depositing a metal or a silicide on the second semiconductor layer. .